SCLS423F − JUNE 1998 − REVISED SEPTEMBER 2003
D Operating Range 2-V to 5.5-V VCC
D 8-Bit Serial-In, Parallel-Out Shift
SN54AHC594 . . . J OR W PACKAGE
SN74AHC594 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
Registers With Storage
D Independent Direct Overriding Clears
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
QA
SER
RCLR
RCLK
SRCLK
SRCLR
QH′
SN54AHC594 . . . FK PACKAGE
(TOP VIEW)
QC
QB
description/ordering information
The ’AHC594 devices contain an 8-bit serial-in,
parallel-out shift register that feeds an 8-bit D-type
storage register. Separate clocks and direct
overriding clear (SRCLR, RCLR) inputs are
provided on the shift and storage registers. A
serial (QH′) output is provided for cascading
purposes.
QD
QE
NC
QF
QG
The shift register (SRCLK) and storage register
(RCLK) clocks are positive-edge triggered. If the
clocks are tied together, the shift register always
is one clock pulse ahead of the storage register.
NC − No internal connection
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
QH
4
SER
RCLR
NC
RCLK
SRCLK
SRCLR
D
16
2
NC
VCC
QA
D
1
GND
NC
Q H′
D
QB
QC
QD
QE
QF
QG
QH
GND
on Shift and Storage Registers
Independent Clocks for Shift and
Storage Registers
Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
ORDERING INFORMATION
PDIP − N
SN74AHC594N
Tube
SN74AHC594D
Tape and reel
SN74AHC594DR
SOP − NS
Tape and reel
SN74AHC594NSR
AHC594
SSOP − DB
Tape and reel
SN74AHC594DBR
HA594
Tube
SN74AHC594PW
Tape and reel
SN74AHC594PWR
CDIP − J
Tube
SNJ54AHC594J
SNJ54AHC594J
CFP − W
Tube
SNJ54AHC594W
SNJ54AHC594W
LCCC − FK
Tube
SNJ54AHC594FK
SNJ54AHC594FK
TSSOP − PW
−55°C
−55
C to 125
125°C
C
TOP-SIDE
MARKING
Tube
SOIC − D
−40°C
−40
C to 85
85°C
C
ORDERABLE
PART NUMBER
PACKAGE†
TA
SN74AHC594N
AHC594
HA594
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
!"#$% !%&% %'(#&% !"(($% & ' )"*+!&% &$, ("! !%'(# )$!'!&% )$( $ $(# ' $-& %("#$% &%&( .&((&%/,
("!% )(!$%0 $ % %$!$&(+/ %!+"$ $%0 ' &++
)&(&#$$(,
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1
SCLS423F − JUNE 1998 − REVISED SEPTEMBER 2003
FUNCTION TABLE
INPUTS
2
FUNCTION
SER
SRCLK
SRCLR
RCLK
RCLR
X
X
L
X
X
Shift register is cleared.
L
↑
H
X
X
First stage of shift register goes low.
Other stages store the data of previous stage, respectively.
H
↑
H
X
X
First stage of shift register goes high.
Other stages store the data of previous stage, respectively.
L
↓
H
X
X
Shift register state is not changed.
X
X
X
X
L
Storage register is cleared.
X
X
X
↑
H
Shift register data is stored in the storage register.
X
X
X
↓
H
Storage register state is not changed.
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SCLS423F − JUNE 1998 − REVISED SEPTEMBER 2003
logic diagram (positive logic)
13
RCLR
12
RCLK
10
SRCLR
SRCLK
SER
11
14
1D Q
C1
R
2D Q
C2
R
2D Q
C2
R
2D Q
C2
R
2D Q
C2
R
2D Q
C2
R
2D Q
C2
R
2D Q
C2
R
R
3D Q
C3
15
R
3D Q
C3
1
R
3D Q
C3
2
R
3D Q
C3
3
R
3D Q
C3
4
R
3D Q
C3
5
R
3D Q
C3
6
R
3D Q
C3
7
QA
QB
QC
QD
QE
QF
QG
QH
9
QH′
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
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3
SCLS423F − JUNE 1998 − REVISED SEPTEMBER 2003
timing diagram
SRCLK
SER
RCLK
SRCLR
RCLR
QA
QB
QC
QD
QE
QF
QG
QH
QH′
4
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SCLS423F − JUNE 1998 − REVISED SEPTEMBER 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±75 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54AHC594
VCC
VIH
Supply voltage
VCC = 2 V
VCC = 3 V
High-level input voltage
VCC = 5.5 V
VCC = 2 V
VIL
VI
VO
IOH
Dt/Dv
MAX
2
5.5
1.5
Input voltage
Output voltage
VCC = 2 V
VCC = 3.3 V ± 0.3 V
High-level output current
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
VCC = 3.3 V ± 0.3 V
Low-level output current
Input transition rise or fall rate
VCC = 5 V ± 0.5 V
MIN
MAX
2
5.5
UNIT
V
1.5
2.1
2.1
3.85
3.85
0.5
VCC = 3 V
VCC = 5.5 V
Low-level input voltage
VCC = 5 V ± 0.5 V
VCC = 2 V
IOL
MIN
SN74AHC594
V
0.5
0.9
0.9
1.65
1.65
V
0
5.5
0
5.5
V
0
VCC
−50
0
VCC
−50
mA
−4
−4
−8
−8
50
50
4
4
8
8
100
100
20
20
V
mA
mA
mA
ns/V
TA
Operating free-air temperature
−55
125
−40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
1 %'(#&% !%!$(% )("! % $ '(#&2$ (
$0% )&$ ' $2$+)#$%, &(&!$(! && &% $(
)$!'!&% &($ $0% 0&+, $-& %("#$% ($$(2$ $ (0 !&%0$ ( !%%"$ $$ )("! ." %!$,
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SCLS423F − JUNE 1998 − REVISED SEPTEMBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TA = 25°C
TYP
MAX
2V
1.9
2
1.9
1.9
3V
2.9
3
2.9
2.9
4.5 V
4.4
4.5
4.4
4.4
3V
2.58
2.48
2.48
3.94
3.8
3.8
IOH = −50 mA
VOH
IOH = −4 mA
QH′, IOH = −4 mA
4.5 V
QA−QH, IOH = −8 mA
IOL = 50 mA
VOL
II
ICC
VI = 5.5 V or GND
VI = VCC or GND,
3.8
SN74AHC594
MIN
MAX
UNIT
V
3.8
0.1
0.1
0.1
3V
0.1
0.1
0.1
0.1
0.1
0.1
3V
0.36
0.5
0.44
0.36
0.5
0.44
0.36
0.5
0.44
±0.1
±1*
±1
mA
4
40
40
mA
10
pF
0 V to 5.5 V
IO = 0
MAX
2V
4.5 V
QA−QH, IOL = 8 mA
MIN
4.5 V
IOL = 4 mA
QH′, IOL = 4 mA
3.94
SN54AHC594
5.5 V
Ci
VI = VCC or GND
5V
2
10
* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
V
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
RCLK or SRCLK high or low
tw
tsu
Pulse duration
Setup time
SN54AHC594
MIN
MAX
SN74AHC594
MIN
5.5
5.5
5.5
RCLR or SRCLR low
5
5
5
SER before SRCLK↑
3.5
3.5
3.5
SRCLK↑ before RCLK↑†
8
8.5
8.5
SRCLR low before RCLK↑
8
9
9
SRCLR high (inactive) before SRCLK↑
4.2
4.8
4.8
RCLR high (inactive) before RCLK↑
4.6
5.3
5.3
MAX
UNIT
ns
ns
th
Hold time
SER after SRCLK↑
1.5
1.5
1.5
ns
† This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift
register is one clock pulse ahead of the storage register.
1 %'(#&% !%!$(% )("! % $ '(#&2$ (
$0% )&$ ' $2$+)#$%, &(&!$(! && &% $(
)$!'!&% &($ $0% 0&+, $-& %("#$% ($$(2$ $ (0 !&%0$ ( !%%"$ $$ )("! ." %!$,
6
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• DALLAS, TEXAS 75265
SCLS423F − JUNE 1998 − REVISED SEPTEMBER 2003
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
RCLK or SRCLK high or low
tw
tsu
Pulse duration
Setup time
SN54AHC594
MIN
MAX
SN74AHC594
MIN
5
5
5
RCLR or SRCLR low
5.2
5.2
5.2
SER before SRCLK↑
3
3
3
SRCLK↑ before RCLK↑†
5
5
5
SRCLR low before RCLK↑
5
5
5
SRCLR high (inactive) before SRCLK↑
2.9
3.3
3.3
RCLR high (inactive) before RCLK↑
3.2
3.7
3.7
MAX
UNIT
ns
ns
th
Hold time
SER after SRCLK↑
2
2
2
ns
† This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift
register is one clock pulse ahead of the storage register.
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
TA = 25°C
TYP
MAX
SN54AHC594
SN74AHC594
LOAD
CAPACITANCE
MIN
CL = 15 pF
80*
120*
70*
70
CL = 50 pF
55
105
50
50
tPLH
tPHL
RCLK
QA−QH
CL = 15 pF
tPLH
tPHL
SRCLK
QH′
H
CL = 15 pF
tPHL
RCLR
QA−QH
tPHL
SRCLR
tPLH
tPHL
MIN
MAX
MIN
MAX
UNIT
MHz
4.6*
8*
1*
8.5*
1
8.5
4.9*
8.2*
1*
8.8*
1
8.8
5.4*
9.1*
1*
9.7*
1
9.7
5.5*
9.2*
1*
9.9*
1
9.9
CL = 15 pF
6*
9.8*
1*
10.6*
1
10.6
ns
QH′
CL = 15 pF
5.6*
9.2*
1*
10*
1
10
ns
6.9
10.5
1
11.1
1
11.1
RCLK
QA−QH
CL = 50 pF
8.1
11.9
1
13.1
1
13.1
tPLH
tPHL
7.7
11.7
1
12.4
1
12.4
SRCLK
QH′
H
CL = 50 pF
8.4
12.5
1
13.9
1
13.9
tPHL
RCLR
QA−QH
CL = 50 pF
9.1
13.1
1
14.4
1
14.4
ns
tPHL
SRCLR
QH′
CL = 50 pF
8.5
12.4
1
14
1
14
ns
ns
ns
ns
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
1 %'(#&% !%!$(% )("! % $ '(#&2$ (
$0% )&$ ' $2$+)#$%, &(&!$(! && &% $(
)$!'!&% &($ $0% 0&+, $-& %("#$% ($$(2$ $ (0 !&%0$ ( !%%"$ $$ )("! ." %!$,
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SCLS423F − JUNE 1998 − REVISED SEPTEMBER 2003
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TA = 25°C
TYP
MAX
SN54AHC594
SN74AHC594
LOAD
CAPACITANCE
MIN
CL = 15 pF
135*
170*
115*
115
CL = 50 pF
120
140
95
95
fmax
tPLH
tPHL
RCLK
QA−QH
CL = 15 pF
tPLH
tPHL
SRCLK
QH′
H
CL = 15 pF
tPHL
RCLR
QA−QH
tPHL
SRCLR
tPLH
tPHL
MIN
MAX
MIN
MAX
UNIT
MHz
3.3*
6.2*
1*
6.5*
1
6.5
3.7*
6.5*
1*
6.9*
1
6.9
3.7*
6.8*
1*
7.2*
1
7.2
4.1*
7.2*
1*
7.6*
1
7.6
CL = 15 pF
4.5*
7.6*
1*
8.2*
1
8.2
ns
QH′
CL = 15 pF
4.1*
7.1*
1*
7.6*
1
7.6
ns
4.9
7.8
1
8.3
1
8.3
RCLK
QA−QH
CL = 50 pF
5.8
8.9
1
9.7
1
9.7
tPLH
tPHL
5.5
8.6
1
9.1
1
9.1
SRCLK
QH′
H
CL = 50 pF
6
9.2
1
10.1
1
10.1
tPHL
RCLR
QA−QH
CL = 50 pF
6.6
10
1
10.7
1
10.7
ns
tPHL
SRCLR
QH′
CL = 50 pF
6
9.2
1
10.1
1
10.1
ns
ns
ns
ns
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25°C (see Note 4)
SN74AHC594
PARAMETER
MIN
TYP
MAX
UNIT
VOL(P)
Quiet output, maximum dynamic VOL
1
V
VOL(V)
Quiet output, minimum dynamic VOL
−0.6
V
VOH(V)
Quiet output, minimum dynamic VOH
3.8
V
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
3.5
V
1.5
V
TYP
UNIT
112
pF
NOTE 4: Characteristics are for surface-mount packages only.
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
No load,
1 %'(#&% !%!$(% )("! % $ '(#&2$ (
$0% )&$ ' $2$+)#$%, &(&!$(! && &% $(
)$!'!&% &($ $0% 0&+, $-& %("#$% ($$(2$ $ (0 !&%0$ ( !%%"$ $$ )("! ." %!$,
8
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f = 1 MHz
SCLS423F − JUNE 1998 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
RL = 1 kΩ
From Output
Under Test
Test
Point
S1
VCC
Open
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
tw
tsu
VCC
Input
50% VCC
50% VCC
0V
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
50% VCC
Input
50% VCC
0V
tPLH
In-Phase
Output
tPHL
50% VCC
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
Output
Waveform 1
S1 at VCC
(see Note B)
50% VCC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
50% VCC
50% VCC
0V
tPZL
tPLZ
≈VCC
50% VCC
tPZH
tPLH
VOH
50% VCC
VOL
VCC
Output
Control
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
50% VCC
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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PACKAGE OPTION ADDENDUM
www.ti.com
9-Aug-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74AHC594D
ACTIVE
SOIC
D
16
SN74AHC594DBR
ACTIVE
SSOP
DB
SN74AHC594DBRE4
ACTIVE
SSOP
SN74AHC594DE4
ACTIVE
SN74AHC594DR
40
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
DB
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SOIC
D
16
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AHC594DRE4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AHC594N
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
SN74AHC594NE4
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
SN74AHC594NSR
ACTIVE
SO
NS
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AHC594NSRE4
ACTIVE
SO
NS
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AHC594PW
ACTIVE
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AHC594PWE4
ACTIVE
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AHC594PWR
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AHC594PWRE4
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
40
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Aug-2005
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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