SCES116G − JULY 1997 − REVISED AUGUST 2003
D
D
D
D
D
D
DGV, DW, OR PW PACKAGE
(TOP VIEW)
Operates From 1.65 V to 3.6 V
Max tpd of 3.3 ns at 3.3 V
±24-mA Output Drive at 3.3 V
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
description/ordering information
This octal transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation.
The SN74ALVCH373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs.
When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
ORDERING INFORMATION
TOP-SIDE
MARKING
Tube
SN74ALVCH373DW
Tape and reel
SN74ALVCH373DWR
TSSOP − PW
Tape and reel
SN74ALVCH373PWR
VB373
TVSOP − DGV
Tape and reel
SN74ALVCH373DGVR
VB373
SOIC − DW
−40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
VFBGA − GQN
VFBGA − ZQN (Pb-free)
Tape and reel
SN74ALVCH373GQNR
SN74ALVCH373ZQNR
ALVCH373
VB373
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
!" #!$% &"'
&! #" #" (" " ") !"
&& *+' &! #", &" ""%+ %!&"
", %% #""'
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1
SCES116G − JULY 1997 − REVISED AUGUST 2003
GQN OR ZQN PACKAGE
(TOP VIEW)
1
2
3
terminal assignments
4
1
2
3
4
A
A
1Q
OE
B
2D
7D
VCC
1D
8Q
B
C
C
3Q
2Q
6Q
7Q
D
D
4D
5D
3D
6D
E
GND
4Q
LE
5Q
E
FUNCTION TABLE
(each latch)
INPUTS
OE
LE
D
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
logic diagram (positive logic)
OE
LE
1
11
C1
1D
3
2
1D
To Seven Other Channels
Pin numbers shown are for the DGV, DW, and PW packages.
2
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1Q
8D
SCES116G − JULY 1997 − REVISED AUGUST 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
GQN/ZQN package . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
VCC
VIH
Supply voltage
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
High-level input voltage
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
VIL
VI
VO
IOH
MIN
MAX
1.65
3.6
1.7
0.35 × VCC
0.7
0
0
IOL
Low-level output current
∆t/∆v
Input transition rise or fall rate
VCC = 2.7 V
VCC = 3 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
V
0.8
Output voltage
High-level output current
V
2
Input voltage
VCC = 1.65 V
VCC = 2.3 V
V
0.65 × VCC
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
Low-level input voltage
UNIT
VCC
VCC
V
V
−4
−12
−12
mA
−24
4
12
12
mA
24
5
ns/V
TA
Operating free-air temperature
−40
85
°C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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3
SCES116G − JULY 1997 − REVISED AUGUST 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = −100 µA
IOH = −4 mA
MIN
1.65 V to 3.6 V
VCC−0.2
1.2
1.65 V
IOH = −6 mA
VOH
IOH = −12 mA
IOH = −24 mA
IOL = 100 µA
2.2
3V
2.4
3V
2
0.4
2.3 V
0.7
2.7 V
0.4
3V
0.55
±5
3.6 V
1.65 V
25
1.65 V
−25
VI = 0.7 V
VI = 1.7 V
2.3 V
45
2.3 V
−45
VI = 0.8 V
VI = 2 V
3V
75
3V
−75
IO = 0
Other inputs at VCC or GND
Data inputs
V
µA
µA
3.6 V
±500
3.6 V
±10
µA
3.6 V
20
µA
3 V to 3.6 V
750
µA
Control inputs
Ci
UNIT
V
0.45
VI = 0.58 V
VI = 1.07 V
VI = VCC or GND,
One input at VCC − 0.6 V,
∆ICC
2.7 V
2.3 V
VI = 0 to 3.6 V‡
VO = VCC or GND
IOZ
ICC
1.7
1.65 V
IOL = 24 mA
VI = VCC or GND
II(hold)
2
2.3 V
0.2
IOL = 12 mA
II
2.3 V
MAX
1.65 V to 3.6 V
IOL = 4 mA
IOL = 6 mA
VOL
TYP†
VCC
4.5
VI = VCC or GND
3.3 V
pF
5
Co
Outputs
VO = VCC or GND
3.3 V
7.5
pF
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
VCC = 1.8 V
MIN
4
MAX
VCC = 2.5 V
± 0.2 V
MIN
MAX
VCC = 2.7 V
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
tw
tsu
Pulse duration, LE high
3.8
3.3
3.3
3.3
ns
Setup time, data before LE↓
1.3
0.5
0.5
0.5
ns
th
Hold time, data after LE↓
0.5
1.3
1.7
1.2
ns
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SCES116G − JULY 1997 − REVISED AUGUST 2003
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
D
Q
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
MIN
MAX
MIN
MAX
1.7
6.3
1
2
6.1
VCC = 2.7 V
MIN
VCC = 3.3 V
± 0.3 V
MAX
MIN
MAX
4
4
1
3.6
1
3.8
3.7
1
3.3
UNIT
tpd
LE
ns
ten
OE
Q
3.4
8.3
1.9
5.4
5.4
1.6
4.8
ns
tdis
OE
Q
1.6
7
1
4.4
4.4
1
4.4
ns
operating characteristics, TA = 25°C
TEST
CONDITIONS
PARAMETER
Cpd
Power dissipation capacitance
per latch
Outputs enabled
Outputs disabled
VCC = 1.8 V
TYP
CL = 0,
f = 10 MHz
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VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
31
33
37
7
7
9
UNIT
pF
5
SCES116G − JULY 1997 − REVISED AUGUST 2003
PARAMETER MEASUREMENT INFORMATION
RL
From Output
Under Test
VLOAD
Open
S1
GND
CL
(see Note A)
RL
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUT
VCC
1.8 V ± 0.15 V
2.5 ± 0.2 V
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
1.5 V
2 × VCC
2 × VCC
6V
6V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
tw
VI
Timing
Input
VM
VM
VM
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VM
VM
0V
tPLH
Output
Control
(low-level
enabling)
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLZ
VLOAD/2
VM
tPZH
tPHL
VOH
VM
VI
VM
tPZL
VI
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VI
Data
Input
VM
0V
0V
tsu
Output
VI
VM
Input
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VOH
VM
VOH − V∆
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
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MECHANICAL DATA
MPBG133C – APRIL 2000 – REVISED AUGUST 2002
GQN (R-PBGA-N20)
PLASTIC BALL GRID ARRAY
1,95 TYP
3,10
2,90
0,65
0,325
0,65
E
D
4,10
3,90
2,60
C
B
A
1
A1 Corner
2
3
4
Bottom View
1,00 MAX
0,08
Seating Plane
20×
0,45
0,35
0,25
0,15
0,05 M
4200704/D 07/2002
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
MicroStar Juniort configuration
Falls within JEDEC MO-225 variation BC.
This package is tin-lead (SnPb). Refer to the 20 ZQN package (drawing 4204492) for lead-free.
MicroStar Junior is a trademark of Texas Instruments.
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MECHANICAL DATA
MPBG297 – JULY 2002
ZQN (R-PBGA-N20)
PLASTIC BALL GRID ARRAY
1,95
0,65
3,10
2,90
0,325
0,65
E
D
4,10
3,90
2,60
C
B
A
1
2
3
4
Bottom View
A1 Corner
1,00 Max
0,08
Seating Plane
20×
0,45
0,35
0,05 M
0,25
0,15
4204492/A 06/2002
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
MicroStar Junior configuration.
Fall within JEDEC MO-225 variation BC.
This package is lead-free. Refer to the 20 GQN package (drawing 4200704) for tin-lead )SnPb).
MicroStar Junior is a trademark of Texas Instruments.
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MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
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MECHANICAL DATA
MSOI003E – JANUARY 1995 – REVISED SEPTEMBER 2001
DW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
16 PINS SHOWN
0.020 (0,51)
0.014 (0,35)
9
0.050 (1,27)
16
0.010 (0,25)
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
0.299 (7,59)
0.291 (7,39)
Gage Plane
0.010 (0,25)
1
8
0°– 8°
0.050 (1,27)
0.016 (0,40)
A
Seating Plane
0.104 (2,65) MAX
0.012 (0,30)
0.004 (0,10)
PINS **
0.004 (0,10)
16
18
20
24
28
A MAX
0.410
(10,41)
0.462
(11,73)
0.510
(12,95)
0.610
(15,49)
0.710
(18,03)
A MIN
0.400
(10,16)
0.453
(11,51)
0.500
(12,70)
0.600
(15,24)
0.700
(17,78)
DIM
4040000/E 08/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MS-013
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MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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