SN54ALS574B, SN54AS574, SN54AS575 SN74ALS574B, SN74ALS575A, SN74AS574, SN74AS575 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS165B – JUNE 1982 – REVISED JULY 1995 • • • • 3-State Buffer-Type Noninverting Outputs Drive Bus Lines Directly Bus-Structured Pinout Buffered Control Inputs SN74ALS575A and ′AS575 Have Synchronous Clear Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), Standard Plastic (N, NT) and Ceramic (J, JT) 300-mil DIPs, and Ceramic Flat (W) Packages SN54ALS574B, SN54AS574 . . . J OR W PACKAGE SN74ALS574B, SN74AS574 . . . DW OR N PACKAGE (TOP VIEW) OE 1D 2D 3D 4D 5D 6D 7D 8D GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q CLK SN54ALS574B, SN54AS574 . . . FK PACKAGE (TOP VIEW) description 2D 1D OE VCC 1Q • These octal D-type edge-triggered flip-flops feature 3-state outputs designed specifically for bus driving. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The output-enable (OE) input does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. 4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13 2Q 3Q 4Q 5Q 6Q 8D GND CLK 8Q 7Q The eight flip-flops enter data on the low-to-high transition of the clock (CLK) input. The SN74ALS575A, SN54AS575, and SN74AS575 may be synchronously cleared by taking the clear (CLR) input low. 3D 4D 5D 6D 7D SN54AS575 . . . JT OR W PACKAGE SN74ALS575A, SN74AS575 . . . DW OR NT PACKAGE (TOP VIEW) CLR OE 1D 2D 3D 4D 5D 6D 7D 8D NC GND The SN54ALS574B, SN54AS574, and SN54AS575 are characterized for operation over the full military temperature range of – 55°C to 125°C. The SN74ALS574B, SN74ALS575A, SN74AS574, and SN74AS575 are characterized for operation from 0°C to 70°C. 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC NC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q CLK NC 1D OE CLR NC VCC NC 1Q SN54AS575 . . . FK PACKAGE (TOP VIEW) 4 3 2 1 28 27 26 5 25 6 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 2Q 3Q 4Q NC 5Q 6Q 7Q 8D NC GND NC NC CLK 8Q 2D 3D 4D NC 5D 6D 7D NC – No internal connection Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ALS574B, SN54AS574, SN54AS575 SN74ALS574B, SN74ALS575A, SN74AS574, SN74AS575 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS165B – JUNE 1982 – REVISED JULY 1995 Function Tables SN54ALS574B, SN74ALS574B, SN54AS574, SN74AS574 (each flip-flop) INPUTS OE CLK D OUTPUT Q L ↑ H H L ↑ L L L L X Q0 H X X Z SN74ALS575A, SN54AS575, SN74AS575 (each flip-flop) INPUTS OE CLR CLK D OUTPUT Q L L ↑ X L L H ↑ H H L H ↑ L L L H L X Q0 H X H X Z logic symbols† SN54ALS574B, SN74ALS574B, SN54AS574, SN74AS574 OE CLK 1D 2D 3D 4D 5D 6D 7D 8D 1 11 2 SN74ALS575A, SN54AS575, SN74AS575 EN OE C1 1D CLK 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 1Q CLR 2Q 1D 3Q 2D 4Q 3D 5Q 4D 6Q 5D 7Q 6D 8Q 7D 8D 2 14 1 3 POST OFFICE BOX 655303 C1 1R 1D 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 † These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DW, J, JT, N, and NT packages. 2 EN • DALLAS, TEXAS 75265 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q SN54ALS574B, SN54AS574, SN54AS575 SN74ALS574B, SN74ALS575A, SN74AS574, SN74AS575 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS165B – JUNE 1982 – REVISED JULY 1995 logic diagrams (positive logic) SN54ALS574B, SN74ALS574B, SN54AS574, SN74AS574 SN74ALS575A, SN54AS575, SN74AS575 1 OE OE 11 CLK CLK C1 2 1D 19 CLR 2 14 1 1Q 1D C1 1D 3 22 1Q 1D To Seven Other Channels To Seven Other Channels Pin numbers shown are for the DW, J, JT, N, and NT packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range, TA: SN54ALS574B . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C SN74ALS574B, SN74ALS575A . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions SN74ALS574B SN74ALS575A SN54ALS574B UNIT MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 VCC VIH Supply voltage VIL IOH Low-level input voltage 0.7 0.8 High-level output current –1 – 2.6 mA IOL Low-level output current 12 24 mA fclock l k Clock frequency tw Pulse duration tsu Set p time before CLK↑ Setup th Hold time after CLK↑ TA Operating free-air temperature High-level input voltage 2 ′ALS574B 0 2 28 SN74ALS575A ′ALS574B, CLK high or low 16.5 Data 15 35 0 30 0 ns 0 – 55 • DALLAS, TEXAS 75265 125 0 MHz ns 15 4 V ns 15 SN74ALS575A, CLR POST OFFICE BOX 655303 0 16.5 SN74ALS575A, CLR Data V 14 SN74ALS575A, CLK high or low V 70 °C 3 SN54ALS574B, SN54AS574, SN54AS575 SN74ALS574B, SN74ALS575A, SN74AS574, SN74AS575 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS165B – JUNE 1982 – REVISED JULY 1995 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TYP† MIN VIK VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = – 18 mA IOH = – 0.4 mA VCC = 4 4.5 5V IOH = – 1 mA IOH = – 2.6 mA VOL VCC = 4 4.5 5V IOL = 12 mA IOL = 24 mA IOZH IOZL VCC = 5.5 V, VCC = 5.5 V, VO = 2.7 V VO = 0.4 V II IIH VCC = 5.5 V, VCC = 5.5 V, VI = 7 V VI = 2.7 V IIL IO‡ VCC = 5.5 V, VCC = 5.5 V, VI = 0.4 V VO = 2.25 V VOH ′ALS574B VCC = 5.5 V ICC SN74ALS575A VCC = 5.5 V SN74ALS574B SN74ALS575A SN54ALS574B TEST CONDITIONS MAX MIN TYP† – 1.2 VCC – 2 2.4 UNIT MAX – 1.2 V VCC – 2 V 3.3 2.4 0.25 – 20 3.2 0.4 0.25 0.4 0.35 0.5 V µA 20 20 – 20 – 20 µA 0.1 0.1 mA 20 20 µA – 0.2 – 0.2 mA – 112 mA – 112 – 30 Outputs high 11 18 11 18 Outputs low 17 27 17 27 Outputs disabled 17 28 17 28 Outputs high 10 17 10 17 Outputs low 15 24 15 24 Outputs disabled 16 30 16 mA 30 † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 4.5 V to 5.5 V, CL = 50 pF, R1 = 500 Ω, R2 = 500 Ω, TA = MIN to MAX§ SN54ALS574B SN74ALS574B SN74ALS575A MIN fmax tPLH tPHL tPZH tPZL tPHZ MAX 28 CLK Q OE Q MIN MAX MIN 35 4 POST OFFICE BOX 655303 MAX 30 MHz 4 22 3 14 4 14 4 17 4 14 4 14 4 21 3 18 4 18 4 26 4 18 4 18 2 10 3 13 2 16 1 10 OE Q tPLZ 2 25 2 12 § For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. • DALLAS, TEXAS 75265 UNIT ns ns ns SN54ALS574B, SN54AS574, SN54AS575 SN74ALS574B, SN74ALS575A, SN74AS574, SN74AS575 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS165B – JUNE 1982 – REVISED JULY 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range, TA: SN54AS574, SN54AS575 . . . . . . . . . . . . . . . . . . – 55°C to 125°C SN74AS574, SN74AS575 . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions SN54AS574 SN54AS575 VCC VIH Supply voltage VIL IOH Low-level input voltage IOL fclock* tw* Pulse duration tsu* Set p time before CLK↑ Setup th* Hold time after CLK↑ High-level input voltage SN74AS574 SN74AS575 UNIT MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 2 2 V V 0.8 0.8 V High-level output current – 12 – 15 mA Low-level output current 32 48 mA 90 MHz Clock frequency 0 100 0 CLK high 5 5.5 CLK low 4 5.5 Data 3 5.5 6.5 6.5 Data 3 3 ′AS575, CLR 0 0 ′AS575, CLR high or low TA Operating free-air temperature – 55 125 0 70 * On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns ns ns °C 5 SN54ALS574B, SN54AS574, SN54AS575 SN74ALS574B, SN74ALS575A, SN74AS574, SN74AS575 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS165B – JUNE 1982 – REVISED JULY 1995 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER SN54AS574 SN54AS575 TEST CONDITIONS MIN VIK VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = – 18 mA IOH = – 2 mA VCC = 4 4.5 5V IOH = – 12 mA IOH = – 15 mA VOL VCC = 4 4.5 5V IOL = 32 mA IOL = 48 mA IOZH IOZL VCC = 5.5 V, VCC = 5.5 V, VO = 2.7 V VO = 0.4 V II IIH VCC = 5.5 V, VCC = 5.5 V, VI = 7 V VI = 2.7 V VOH IIL OE, CLK, CLR D IO‡ ′AS574 VCC = 5 5.5 5V V, VI = 0 0.4 4V VCC = 5.5 V, VO = 2.25 V Outputs high VCC = 5.5 V ICC ′AS575 VCC = 5.5 V TYP† SN74AS574 SN74AS575 MAX MIN TYP† – 1.2 VCC – 2 2.4 UNIT MAX – 1.2 V VCC – 2 V 3.2 2.4 0.29 3.3 0.5 0.34 – 30 0.5 V µA 50 50 – 50 – 50 µA 0.1 0.1 mA µA 20 20 – 0.5 – 0.5 –3 –2 – 112 – 30 – 112 73 116 73 116 Outputs low 85 134 85 134 Outputs disabled 84 134 84 134 Outputs high 78 126 78 126 Outputs low 89 142 89 142 mA mA mA Outputs disabled 88 142 88 142 † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 4.5 V to 5.5 V, CL = 50 pF, R1 = 500 Ω, R2 = 500 Ω, TA = MIN to MAX§ SN54AS574 SN54AS575 MIN fmax* tPLH tPHL tPZH tPZL tPHZ MAX 100 CLK An Q Any OE An Q Any UNIT SN74AS574 SN74AS575 MIN MAX 90 MHz 3 11 3 8 4 11 4 9 2 7 2 6 3 11 3 10 2 7 2 6 OE Any Q tPLZ 2 7 2 6 * On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested. § For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns ns ns SN54ALS574B, SN54AS574, SN54AS575 SN74ALS574B, SN74ALS575A, SN74AS574, SN74AS575 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS165B – JUNE 1982 – REVISED JULY 1995 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7V RL = R1 = R2 VCC S1 RL R1 Test Point From Output Under Test CL (see Note A) From Output Under Test RL Test Point From Output Under Test CL (see Note A) CL (see Note A) LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS 3.5 V Timing Input Test Point LOAD CIRCUIT FOR 3-STATE OUTPUTS 3.5 V High-Level Pulse 1.3 V R2 1.3 V 1.3 V 0.3 V 0.3 V Data Input tw th tsu 3.5 V 1.3 V 3.5 V Low-Level Pulse 1.3 V 0.3 V 1.3 V 0.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATIONS 3.5 V Output Control (low-level enabling) 1.3 V 1.3 V 0.3 V tPZL Waveform 1 S1 Closed (see Note B) tPLZ [3.5 V 1.3 V tPHZ tPZH Waveform 2 S1 Open (see Note B) 1.3 V VOL 0.3 V VOH 1.3 V 0.3 V [0 V 3.5 V 1.3 V Input 1.3 V 0.3 V tPHL tPLH VOH In-Phase Output 1.3 V 1.3 V VOL tPLH tPHL VOH Out-of-Phase Output (see Note C) 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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