TI SN74ALS874BNT

SN54ALS874B, SN74ALS874B, SN74ALS876A
SN74AS874, SN74AS876
DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS
SDAS061C – APRIL 1982 – REVISED JANUARY 1995
•
•
•
•
•
3-State Buffer-Type Outputs Drive Bus
Lines Directly
Bus-Structured Pinout
Choice of True or Inverting Logic
– SN54ALS874B, SN74ALS874B,
SN74AS874 Have True Outputs
– SN74ALS876A, SN74AS876 Have
Inverting Outputs
Asynchronous Clear
Package Options Include Plastic
Small-Outline (DW) Packages, Plastic (FN)
and Ceramic (FK) Chip Carriers, and
Standard Plastic (NT) and Ceramic (JT)
300-mil DIPs
SN54ALS874B . . . JT PACKAGE
SN74ALS874B, SN74AS874 . . . DW OR NT PACKAGE
(TOP VIEW)
1CLR
1OE
1D1
1D2
1D3
1D4
2D1
2D2
2D3
2D4
2OE
GND
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VCC
1CLK
1Q1
1Q2
1Q3
1Q4
2Q1
2Q2
2Q3
2Q4
2CLK
2CLR
description
The edge-triggered flip-flops enter data on the
low-to-high transition of the clock (CLK) input.
The SN54ALS874B, SN74ALS874B, and
SN74AS874 have clear (CLR) inputs and
noninverting Q outputs. The SN74ALS876A and
SN74AS876 have preset (PRE) inputs and
inverting Q outputs; taking PRE low causes the
four Q or Q outputs to go low independently of the
clock.
The SN54ALS874B is characterized for operation
over the full military temperature range of – 55°C
to 125°C. The SN74ALS874B, SN74ALS876A,
SN74AS874, and SN74AS876 devices are
characterized for operation from 0°C to 70°C.
1D1
1OE
1CLR
NC
VCC
1CLK
1Q1
SN54ALS874B . . . FK PACKAGE
(TOP VIEW)
1D2
1D3
1D4
NC
2D1
2D2
2D3
5
4
3 2 1 28 27 26
25
6
24
7
23
8
22
9
21
10
20
19
11
12 13 14 15 16 17 18
1Q2
1Q3
1Q4
NC
2Q1
2Q2
2Q3
2D4
2OE
GND
NC
2CLR
2CLK
2Q4
These dual 4-bit D-type edge-triggered flip-flops
feature 3-state outputs designed specifically as
bus drivers. They are particularly suitable for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
NC – No internal connection
SN74ALS876A, SN74AS876 . . . DW OR NT PACKAGE
(TOP VIEW)
1PRE
1OE
1D1
1D2
1D3
1D4
2D1
2D2
2D3
2D4
2OE
GND
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VCC
1CLK
1Q1
1Q2
1Q3
1Q4
2Q1
2Q2
2Q3
2Q4
2CLK
2PRE
Copyright  1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54ALS874B, SN74ALS874B, SN74ALS876A
SN74AS874, SN74AS876
DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS
SDAS061C – APRIL 1982 – REVISED JANUARY 1995
Function Tables
SN54ALS874B, SN74ALS874B, SN74AS874
(each flip-flop)
INPUTS
OE
D
OUTPUT
Q
CLR
CLK
L
L
X
X
L
L
H
↑
H
H
L
H
↑
L
L
L
H
L
X
Q0
H
X
X
X
Z
SN74ALS876A, SN74AS876
(each flip-flop)
INPUTS
OE
D
OUTPUT
Q
PRE
CLK
L
L
X
X
L
L
H
↑
H
L
L
H
↑
L
H
L
H
L
X
Q0
H
X
X
X
Z
logic symbols†
SN54ALS874B, SN74ALS874B, SN74AS874
1OE
1CLK
1CLR
1D1
1D2
1D3
1D4
2OE
2CLK
2CLR
2D1
2D2
2D3
2D4
2
EN
23
1
3
1PRE
1D
22
21
20
6
19
1D1
1Q2
1D2
1Q3
1D3
1Q4
1D4
2OE
2CLK
C1
R
1D
2PRE
18
8
17
9
16
10
1Q1
EN
14
7
1CLK
C1
5
13
1OE
R
4
11
SN74ALS876A, SN74AS876
15
2Q1
2D1
2Q2
2D2
2Q3
2D3
2Q4
2D4
2
1
3
POST OFFICE BOX 655303
C1
S
1D
22
4
21
5
20
6
19
11
13
7
1Q2
1Q3
1Q4
C1
S
1D
18
8
17
9
16
10
15
• DALLAS, TEXAS 75265
1Q1
EN
14
† These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DW, JT, and NT packages.
2
EN
23
2Q1
2Q2
2Q3
2Q4
SN54ALS874B, SN74ALS874B, SN74ALS876A
SN74AS874, SN74AS876
DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS
SDAS061C – APRIL 1982 – REVISED JANUARY 1995
logic diagrams (positive logic)
SN54ALS874B, SN74ALS874B, SN74AS874
(each quad flip-flop)
SN74ALS876A, SN74AS876
(each quad flip-flop)
OE
OE
CLK
CLK
CLR
PRE
R
S
C1
D1
C1
Q1
D1
1D
R
S
C1
D2
C1
Q2
D2
1D
R
C1
Q3
D3
1D
R
Q3
1D
S
C1
D4
Q2
1D
S
C1
D3
Q1
1D
C1
Q4
D4
1D
Q4
1D
Pin numbers shown are for the DW, JT, and NT packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range, TA: SN54ALS874B . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
SN74ALS874B, SN74ALS876A . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54ALS874B, SN74ALS874B, SN74ALS876A
SN74AS874, SN74AS876
DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS
SDAS061C – APRIL 1982 – REVISED JANUARY 1995
recommended operating conditions
SN74ALS874B
SN74ALS876A
SN54ALS874B
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
0.7
0.8
High-level output current
–1
– 2.6
IOL
fclock
Low-level output current
12
24
mA
30
MHz
tw
Pulse duration
High-level input voltage
2
Clock frequency
2
0
tsu
Set p time before CLK↑
Setup
th
TA
Hold time, data after CLK↑
25
PRE or CLR low
15
10
20
16.5
CLK low
20
16.5
Data
15
15
PRE or CLR inactive
15
10
4
Operating free-air temperature
V
0
CLK high
125
V
mA
ns
ns
0
– 55
V
ns
0
70
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
MIN
VIK
VCC = 4.5 V,
VCC = 4.5 V to 5.5 V,
II = – 18 mA
IOH = – 0.4 mA
VCC = 4
4.5
5V
IOH = – 1 mA
IOH = – 2.6 mA
VOL
5V
VCC = 4
4.5
IOL = 12 mA
IOL = 24 mA
IOZH
IOZL
VCC = 5.5 V,
VCC = 5.5 V,
VO = 2.7 V
VO = 0.4 V
II
IIH
VCC = 5.5 V,
VCC = 5.5 V,
VI = 7 V
VI = 2.7 V
IIL
IO‡
VCC = 5.5 V,
VCC = 5.5 V,
VI = 0.4 V
VO = 2.25 V
VOH
′ALS874B
VCC = 5.5 V
ICC
SN74ALS876A
VCC = 5.5 V
SN74ALS874B
SN74ALS876A
SN54ALS874B
TEST CONDITIONS
TYP†
MAX
MIN
TYP†
– 1.2
VCC – 2
2.4
UNIT
MAX
– 1.2
V
VCC – 2
V
3.3
2.4
0.25
– 20
0.4
3.2
0.25
0.4
0.35
0.5
V
µA
20
20
– 20
– 20
µA
0.1
0.1
mA
20
20
µA
– 0.2
– 0.2
mA
– 112
mA
– 112
– 30
Outputs high
14
21
14
21
Outputs low
19
30
19
30
Outputs disabled
20
32
20
32
Outputs high
14
21
Outputs low
18
29
mA
Outputs disabled
20
31
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54ALS874B, SN74ALS874B, SN74ALS876A
SN74AS874, SN74AS876
DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS
SDAS061C – APRIL 1982 – REVISED JANUARY 1995
switching characteristics (see Figure 1)
PARAMETER
FROM
(INPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
R1 = 500 Ω,
R2 = 500 Ω,
TA = MIN to MAX†
TO
(OUTPUT)
SN54ALS874B
MIN
fmax
tPLH
tPHL
tPHL
tPZH
tPZL
tPHZ
SN74ALS874B
MAX
MIN
25
CLK
An Q
Any
CLR
Any Q
OE
An Q
Any
UNIT
MAX
30
MHz
4
18
4
14
4
16
4
14
5
23
5
17
4
24
4
18
4
21
4
18
2
10
3
12
2
15
OE
Any Q
tPLZ
3
22
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
ns
ns
ns
ns
switching characteristics (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
R1 = 500 Ω,
R2 = 500 Ω,
TA = MIN to MAX†
UNIT
SN74ALS876A
MIN
fmax
tPLH
tPHL
tPHL
tPZH
tPZL
tPHZ
MAX
30
CLK
An Q
Any
PRE
Any Q
OE
An Q
Any
MHz
4
14
4
14
6
19
4
18
4
18
2
OE
Any Q
tPLZ
3
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
10
13
ns
ns
ns
ns
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Operating free-air temperature range, TA: SN74AS874, SN74AS876 . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SN54ALS874B, SN74ALS874B, SN74ALS876A
SN74AS874, SN74AS876
DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS
SDAS061C – APRIL 1982 – REVISED JANUARY 1995
recommended operating conditions
SN74AS874
SN74AS876
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
0.8
0.8
V
High-level output current
– 15
– 15
mA
IOL
fclock
Low-level output current
48
48
mA
80
MHz
tw
High-level input voltage
2
Clock frequency
Pulse duration
0
2
125
2
4.5
CLK high
3
6.2
CLK low
4
6.2
Data
2
4.5
PRE or CLR inactive
4
5
tsu
Set p time before CLK↑
Setup
th
TA
Hold time, data after CLK↑
1
Operating free-air temperature
0
V
0
PRE or CLR low
ns
ns
2
70
V
ns
0
70
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN74AS874
SN74AS876
MIN
VIK
VOH
VOL
IOZH
IOZL
II
IIH
IIL
D
All others
IO‡
SN74AS874
VCC = 4.5 V,
VCC = 4.5 V to 5.5 V,
II = – 18 mA
IOH = – 2 mA
VCC = 4.5 V,
VCC = 4.5 V,
IOH = – 15 mA
IOL = 48 mA
VCC = 5.5 V,
VCC = 5.5 V,
VO = 2.7 V
VO = 0.4 V
VCC = 5.5 V,
VCC = 5.5 V,
VI = 7 V
VI = 2.7 V
5V
VCC = 5
5.5
V,
4V
VI = 0
0.4
VCC = 5.5 V,
VO = 2.25 V
Outputs high
VCC = 5.5 V
Outputs low
Outputs disabled
ICC
Outputs high
SN74AS876
VCC = 5.5 V
Outputs low
Outputs disabled
TYP†
UNIT
MAX
– 1.2
VCC – 2
2.4
V
3.3
0.35
0.5
V
50
µA
– 50
µA
0.1
mA
20
µA
–2
– 0.5
– 30
– 112
82
133
92
149
100
160
88
142
94
150
mA
mA
mA
160
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
100
V
SN54ALS874B, SN74ALS874B, SN74ALS876A
SN74AS874, SN74AS876
DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS
SDAS061C – APRIL 1982 – REVISED JANUARY 1995
switching characteristics (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
R1 = 500 Ω,
R2 = 500 Ω,
TA = MIN to MAX†
UNIT
SN74AS874
MIN
fmax
tPLH
tPHL
tPHL
tPZH
tPZL
tPHZ
MAX
125
CLK
An Q
Any
CLR
Any Q
OE
An Q
Any
MHz
3
8.5
4
10.5
4
9.5
2
7
3
10.5
2
OE
Any Q
tPLZ
2
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
6
7.5
ns
ns
ns
ns
switching characteristics (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
R1 = 500 Ω,
R2 = 500 Ω,
TA = MIN to MAX†
UNIT
SN74AS876
MIN
fmax
tPLH
tPHL
tPHL
tPZH
tPZL
tPHZ
MAX
80
CLK
An Q
Any
PRE
Any Q
OE
An Q
Any
3
8.5
4
10.5
4
9.5
2
7
3
11
2
OE
Any Q
tPLZ
2
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MHz
7
7
ns
ns
ns
ns
7
SN54ALS874B, SN74ALS874B, SN74ALS876A
SN74AS874, SN74AS876
DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS
SDAS061C – APRIL 1982 – REVISED JANUARY 1995
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7V
RL = R1 = R2
VCC
S1
RL
R1
Test
Point
From Output
Under Test
CL
(see Note A)
From Output
Under Test
RL
Test
Point
From Output
Under Test
CL
(see Note A)
CL
(see Note A)
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
3.5 V
Timing
Input
Test
Point
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3.5 V
High-Level
Pulse
1.3 V
R2
1.3 V
1.3 V
0.3 V
0.3 V
Data
Input
tw
th
tsu
3.5 V
1.3 V
3.5 V
Low-Level
Pulse
1.3 V
0.3 V
1.3 V
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
Output
Control
(low-level
enabling)
1.3 V
1.3 V
0.3 V
tPZL
Waveform 1
S1 Closed
(see Note B)
tPLZ
[3.5 V
1.3 V
tPHZ
tPZH
Waveform 2
S1 Open
(see Note B)
1.3 V
VOL
0.3 V
VOH
1.3 V
0.3 V
[0 V
3.5 V
1.3 V
Input
1.3 V
0.3 V
tPHL
tPLH
VOH
In-Phase
Output
1.3 V
1.3 V
VOL
tPLH
tPHL
VOH
Out-of-Phase
Output
(see Note C)
1.3 V
1.3 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
84010013A
ACTIVE
LCCC
FK
28
8401001KA
OBSOLETE
CFP
W
24
1
TBD
Lead/Ball Finish
MSL Peak Temp (3)
POST-PLATE N / A for Pkg Type
TBD
Call TI
Call TI
8401001LA
ACTIVE
CDIP
JT
24
1
TBD
A42 SNPB
N / A for Pkg Type
SN54ALS874BJT
ACTIVE
CDIP
JT
24
1
TBD
A42 SNPB
N / A for Pkg Type
SN74ALS874BDW
ACTIVE
SOIC
DW
24
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS874BDWE4
ACTIVE
SOIC
DW
24
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS874BDWG4
ACTIVE
SOIC
DW
24
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS874BDWR
ACTIVE
SOIC
DW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS874BDWRE4
ACTIVE
SOIC
DW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS874BDWRG4
ACTIVE
SOIC
DW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS874BNSR
ACTIVE
SO
NS
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS874BNSRE4
ACTIVE
SO
NS
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS874BNSRG4
ACTIVE
SO
NS
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS874BNT
ACTIVE
PDIP
NT
24
15
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74ALS874BNTE4
ACTIVE
PDIP
NT
24
15
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74ALS876ADW
ACTIVE
SOIC
DW
24
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS876ADWE4
ACTIVE
SOIC
DW
24
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS876ADWG4
ACTIVE
SOIC
DW
24
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS876ADWR
ACTIVE
SOIC
DW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS876ADWRE4
ACTIVE
SOIC
DW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS876ADWRG4
ACTIVE
SOIC
DW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS876ANT
ACTIVE
PDIP
NT
24
15
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74ALS876ANTE4
ACTIVE
PDIP
NT
24
15
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74AS874DW
ACTIVE
SOIC
DW
24
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AS874DWE4
ACTIVE
SOIC
DW
24
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AS874DWG4
ACTIVE
SOIC
DW
24
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AS874DWR
ACTIVE
SOIC
DW
24
2000 Green (RoHS &
CU NIPDAU
Level-1-260C-UNLIM
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74AS874DWRE4
ACTIVE
SOIC
DW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AS874DWRG4
ACTIVE
SOIC
DW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AS874NT
ACTIVE
PDIP
NT
24
15
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74AS874NTE4
ACTIVE
PDIP
NT
24
15
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74AS876DW
ACTIVE
SOIC
DW
24
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AS876DWE4
ACTIVE
SOIC
DW
24
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AS876DWG4
ACTIVE
SOIC
DW
24
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AS876DWR
ACTIVE
SOIC
DW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AS876DWRE4
ACTIVE
SOIC
DW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AS876DWRG4
ACTIVE
SOIC
DW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AS876NT
ACTIVE
PDIP
NT
24
15
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74AS876NTE4
ACTIVE
PDIP
NT
24
15
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SNJ54ALS874BFK
ACTIVE
LCCC
FK
28
1
TBD
SNJ54ALS874BJT
ACTIVE
CDIP
JT
24
1
TBD
Lead/Ball Finish
MSL Peak Temp (3)
no Sb/Br)
POST-PLATE N / A for Pkg Type
A42 SNPB
N / A for Pkg Type
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN74ALS874BDWR
Package Package Pins
Type Drawing
SOIC
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
DW
24
2000
330.0
24.4
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.75
15.7
2.7
12.0
24.0
Q1
SN74ALS874BNSR
SO
NS
24
2000
330.0
24.4
8.2
15.4
2.5
12.0
24.0
Q1
SN74ALS876ADWR
SOIC
DW
24
2000
330.0
24.4
10.75
15.7
2.7
12.0
24.0
Q1
SN74AS874DWR
SOIC
DW
24
2000
330.0
24.4
10.75
15.7
2.7
12.0
24.0
Q1
SN74AS876DWR
SOIC
DW
24
2000
330.0
24.4
10.75
15.7
2.7
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74ALS874BDWR
SOIC
DW
24
2000
346.0
346.0
41.0
SN74ALS874BNSR
SO
NS
24
2000
346.0
346.0
41.0
SN74ALS876ADWR
SOIC
DW
24
2000
346.0
346.0
41.0
SN74AS874DWR
SOIC
DW
24
2000
346.0
346.0
41.0
SN74AS876DWR
SOIC
DW
24
2000
346.0
346.0
41.0
Pack Materials-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
A
B
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
9
22
8
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
7
52
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
25
5
26
27
28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
Falls within JEDEC MS-004
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MPDI004 – OCTOBER 1994
NT (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
24 PINS SHOWN
PINS **
A
24
28
A MAX
1.260
(32,04)
1.425
(36,20)
A MIN
1.230
(31,24)
1.385
(35,18)
B MAX
0.310
(7,87)
0.315
(8,00)
B MIN
0.290
(7,37)
0.295
(7,49)
DIM
24
13
0.280 (7,11)
0.250 (6,35)
1
12
0.070 (1,78) MAX
B
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0°– 15°
0.010 (0,25) M
0.010 (0,25) NOM
4040050 / B 04/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MCFP007 – OCTOBER 1994
W (R-GDFP-F24)
CERAMIC DUAL FLATPACK
0.375 (9,53)
0.340 (8,64)
Base and Seating Plane
0.006 (0,15)
0.004 (0,10)
0.090 (2,29)
0.045 (1,14)
0.045 (1,14)
0.026 (0,66)
0.395 (10,03)
0.360 (9,14)
0.360 (9,14)
0.240 (6,10)
1
0.360 (9,14)
0.240 (6,10)
24
0.019 (0,48)
0.015 (0,38)
0.050 (1,27)
0.640 (16,26)
0.490 (12,45)
0.030 (0,76)
0.015 (0,38)
12
13
30° TYP
1.115 (28,32)
0.840 (21,34)
4040180-5 / B 03/95
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Falls within MIL-STD-1835 GDFP2-F24 and JEDEC MO-070AD
Index point is provided on cap for terminal identification only.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MCER004A – JANUARY 1995 – REVISED JANUARY 1997
JT (R-GDIP-T**)
CERAMIC DUAL-IN-LINE
24 LEADS SHOWN
PINS **
A
13
24
B
1
24
28
A MAX
1.280
(32,51)
1.460
(37,08)
A MIN
1.240
(31,50)
1.440
(36,58)
B MAX
0.300
(7,62)
0.291
(7,39)
B MIN
0.245
(6,22)
0.285
(7,24)
DIM
12
0.070 (1,78)
0.030 (0,76)
0.100 (2,54) MAX
0.320 (8,13)
0.290 (7,37)
0.015 (0,38) MIN
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.014 (0,36)
0.008 (0,20)
0.100 (2,54)
4040110/C 08/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification.
Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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