SN74AUP1G126 www.ti.com SCES596F – JULY 2004 – REVISED MAY 2010 LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT Check for Samples: SN74AUP1G126 FEATURES 1 • • • • • • • Available in the Texas Instruments NanoStar™ Package Low Static-Power Consumption (ICC = 0.9 mA Max) Low Dynamic-Power Consumption (Cpd = 4 pF Typ at 3.3 V) Low Input Capacitance (Ci = 1.5 pF Typ) Low Noise – Overshoot and Undershoot <10% of VCC Input-Disable Feature Allows Floating Input Conditions Ioff Supports Partial-Power-Down Mode Operation A 2 GND 3 VCC 5 1 1 6 VCC A 2 5 N.C. GND 3 4 Y • • • • OE 1 A 2 GND 3 DRL PACKAGE (TOP VIEW) VCC 5 OE 1 A 2 GND 3 5 VCC 4 Y Y 4 Y 4 DRY PACKAGE (TOP VIEW) OE • • • Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at Input Wide Operating VCC Range of 0.8 V to 3.6 V Optimized for 3.3-V Operation 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation tpd = 4.6 ns Max at 3.3 V Suitable for Point-to-Point Applications Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Performance Tested Per JESD 22− – 2000-V Human-Body Model (A114-B, Class II) – 1000-V Charged-Device Model (C101) DCK PACKAGE (TOP VIEW) DBV PACKAGE (TOP VIEW) OE • DSF PACKAGE (TOP VIEW) OE 1 6 VCC A 2 5 N.C. GND 3 4 Y YFP PACKAGE (TOP VIEW) OE A GND A1 1 6 A2 B1 2 5 B2 C1 3 4 C2 VCC N.C. Y YZP PACKAGE (TOP VIEW) OE A GND A1 1 B1 2 C1 3 5 A2 VCC 4 C2 Y N.C. – No internal connection. See mechanical drawings for dimensions. DESCRIPTION/ORDERING INFORMATION The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable applications. This family ensures a very low static and dynamic power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see Figure 1 and Figure 2 ). 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2010, Texas Instruments Incorporated SN74AUP1G126 SCES596F – JULY 2004 – REVISED MAY 2010 www.ti.com Switching Characteristics (1) at 25 MHz 3.3-V Logic(1) (1) 3.3-V Logic(1) Single, dual, and triple gates (1) Figure 1. AUP – The Lowest-Power Family AUP1G08 data at CL = 15 pF Figure 2. Excellent Signal Integrity This bus buffer gate is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is low. This device has the input-disable feature, which allows floating input signals. To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION (1) –40°C to 85°C Reel of 3000 SN74AUP1G126YFPR _ _ _ HN _ NanoStar™ – WCSP (DSBGA) 0.23-mm Large Bump – YZP (Pb-free) Reel of 3000 SN74AUP1G126YZPR _ _ _ HN _ QFN – DRY Reel of 5000 SN74AUP1G126DRYR HN mQFN – DSF Reel of 5000 SN74AUP1G126DSFR HN Reel of 3000 SN74AUP1G126DBVR Reel of 250 SN74AUP1G126DBVT Reel of 3000 SN74AUP1G126DCKR Reel of 250 SN74AUP1G126DCKT Reel of 4000 SN74AUP1G126DRLR SOT (SC-70) – DCK SOT (SOT-553) – DRL (2) (3) TOP-SIDE MARKING (3) NanoStar™ – WCSP (DSBGA) 0.23-mm Large Bump – YFP SOT (SOT-23) – DBV (1) ORDERABLE PART NUMBER PACKAGE (2) TA H26_ HN_ HN_ For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. DBV/DCK/DRL: The actual top-side marking has one additional character that designates the wafer fab/assembly site. YZP/YZT: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). FUNCTION TABLE INPUTS (1) 2 OE A H H OUTPUT Y H H L L L X (1) Z Floating inputs allowed Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): SN74AUP1G126 SN74AUP1G126 www.ti.com SCES596F – JULY 2004 – REVISED MAY 2010 LOGIC DIAGRAM (POSITIVE LOGIC) Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): SN74AUP1G126 3 SN74AUP1G126 SCES596F – JULY 2004 – REVISED MAY 2010 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 4.6 V VI Input voltage range (2) –0.5 4.6 V VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 4.6 V –0.5 VCC + 0.5 (2) UNIT VO Output voltage range in the high or low state IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±20 mA Continuous current through VCC or GND ±50 mA qJA Package thermal impedance (3) DBV package 206 DCK package 252 DRL package 142 DSF package TBD DRY package 234 YFP/YZP/YZT package Tstg (1) (2) (3) 4 Storage temperature range V °C/W 132 –65 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7. Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): SN74AUP1G126 SN74AUP1G126 www.ti.com SCES596F – JULY 2004 – REVISED MAY 2010 RECOMMENDED OPERATING CONDITIONS (1) VCC MIN MAX 0.8 3.6 VCC 3.6 0.65 × VCC 3.6 1.6 3.6 2 3.6 VCC = 1.1 V to 1.95 V 0 0.35 × VCC VCC = 2.3 V to 2.7 V 0 0.7 VCC = 3 V to 3.6 V 0 0.9 Active state 0 VCC 3-state 0 3.6 Supply voltage VCC = 0.8 V VIH High-level input voltage VCC = 1.1 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 0.8 V VIL Low-level input voltage VO Output voltage IOH High-level output current IOL Low-level output current Input transition rise or fall rate TA Operating free-air temperature (1) V V 0 VCC = 0.8 V –20 VCC = 1.1 V –1.1 VCC = 1.4 V –1.7 VCC = 1.65 V –1.9 VCC = 2.3 V –3.1 VCC = 3 V –4 VCC = 0.8 V 20 VCC = 1.1 V 1.1 VCC = 1.4 V 1.7 VCC = 1.65 V 1.9 VCC = 2.3 V 3.1 VCC = 3 V Δt/Δv UNIT V V mA mA mA mA 4 VCC = 0.8 V to 3.6 V –40 200 ns/V 85 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow of Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): SN74AUP1G126 5 SN74AUP1G126 SCES596F – JULY 2004 – REVISED MAY 2010 www.ti.com ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOL TEST CONDITIONS TA = –40°C to 85°C MAX MIN 0.8 V to 3.6 V VCC – 0.1 VCC – 0.1 1.1 V 0.75 × VCC 0.7 × VCC IOH = –1.7 mA 1.4 V 1.11 1.03 IOH = –1.9 mA 1.65 V 1.32 1.3 2.05 1.97 IOH = –2.7 mA IOH = –4 mA 2.3 V 3V 1.9 1.85 2.72 2.67 2.6 2.55 MAX UNIT V IOL = 20 mA 0.8 V to 3.6 V 0.1 0.1 IOL = 1.1 mA 1.1 V 0.3 × VCC 0.3 × VCC IOL = 1.7 mA 1.4 V 0.31 0.37 IOL = 1.9 mA 1.65 V 0.31 0.35 0.31 0.33 0.44 0.45 0.31 0.33 0.44 0.45 0 V to 3.6 V 0.1 0.5 mA IOL = 2.3 mA IOL = 3.1 mA IOL = 2.7 mA IOL = 4 mA II TYP IOH = –1.1 mA IOH = –3.1 mA A or OE input TA = 25°C MIN IOH = –20 mA IOH = –2.3 mA VOL VCC VI = GND to 3.6 V 2.3 V 3V V Ioff VI or VO = 0 V to 3.6 V 0V 0.2 0.6 mA ΔIoff VI or VO = 0 V to 3.6 V 0 V to 0.2 V 0.2 0.6 mA IOZ VO = VCC or GND 0.5 mA ICC VI = GND or (VCC to 3.6 V), OE = GND, IO = 0 0.9 mA A input ΔICC OE input All inputs 3.3 V VI = GND to 3.6 V, OE = VCC (2) 0.8 V to 3.6 V VI = VCC or GND Co VO = VCC or GND 6 0.8 V to 3.6 V VI = VCC – 0.6 V (1), IO = 0 Ci (1) (2) 3.6 V 0.5 0V 1.5 3.6 V 1.5 3.6 V 3 40 50 110 120 0 0 mA pF pF One input at VCC – 0.6 V, other input at VCC or GND To show ICC is very low when the input-disable feature is enabled Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): SN74AUP1G126 SN74AUP1G126 www.ti.com SCES596F – JULY 2004 – REVISED MAY 2010 SWITCHING CHARACTERISTICS over recommended operating free-air temperature range, CL = 5 pF (unless otherwise noted) (see Figure 3 and Figure 4) PARAMETER FROM (INPUT) TO (OUTPUT) MIN 0.8 V tpd A Y OE Y OE Y UNIT MAX MIN MAX 1.2 V ± 0.1 V 4.3 7.4 12.6 2.7 15.3 1.5 V ± 0.1 V 3.3 5.2 8.5 1 10.2 1.8 V ± 0.15 V 2.6 4.1 6.8 1.3 8.3 2.5 V ± 0.2 V 2 2.9 4.7 1.1 5.8 3.3 V ± 0.3 V 1.7 2.4 3.8 1 4.6 ns 19.1 1.2 V ± 0.1 V 5.1 9.3 15.9 3.6 19.2 1.5 V ± 0.1 V 4.1 6.6 10.5 2.5 12.7 1.8 V ± 0.15 V 3.2 5.3 8.7 2.1 10.3 2.5 V ± 0.2 V 2.5 3.8 6 1.6 7.2 3.3 V ± 0.3 V 2.1 3.2 4.9 1.4 5.9 0.8 V tdis TYP 18.1 0.8 V ten TA = –40°C to 85°C TA = 25°C VCC ns 12.1 1.2 V ± 0.1 V 2.4 4.1 6.9 2.2 7.7 1.5 V ± 0.1 V 1.8 2.9 4.5 1.7 5.1 1.8 V ± 0.15 V 1 2.9 4.3 1.5 4.7 2.5 V ± 0.2 V 1 1.8 2.7 1 3.3 3.3 V ± 0.3 V 1.2 2.2 3.2 1.1 4 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): SN74AUP1G126 ns 7 SN74AUP1G126 SCES596F – JULY 2004 – REVISED MAY 2010 www.ti.com SWITCHING CHARACTERISTICS over recommended operating free-air temperature range, CL = 10 pF (unless otherwise noted) (see Figure 3 and Figure 4) PARAMETER FROM (INPUT) TO (OUTPUT) MIN 0.8 V tpd A or B Y OE Y 8 OE Y MAX 20.5 13.7 UNIT MIN MAX 4.6 8.4 9.3 3.6 16.6 1.5 V ± 0.1 V 3.5 5.9 7.5 2.4 11.1 1.8 V ± 0.15 V 3.9 4.7 5.3 1.3 9.1 2.5 V ± 0.2 V 2.3 3.4 4.3 1.6 6.4 3.3 V ± 0.3 V 2.1 2.8 1.4 5.2 21.8 16.8 1.2 V ± 0.1 V 4.9 10.2 11.2 4.4 20.2 1.5 V ± 0.1 V 3.9 7.3 9.2 3.3 13.5 1.8 V ± 0.15 V 3.4 5.8 6.4 2.7 11 2.5 V ± 0.2 V 2.5 4.3 5.4 2.1 7.8 3.3 V ± 0.3 V 2.1 3.7 1.9 6.4 0.8 V tdis TYP 1.2 V ± 0.1 V 0.8 V ten TA = –40°C to 85°C TA = 25°C VCC ns ns 13 1.2 V ± 0.1 V 3.8 6.6 11.7 1.2 14 1.5 V ± 0.1 V 2.2 4.7 7.9 1.3 9.3 1.8 V ± 0.15 V 2.4 4.4 6.4 2.2 7.5 2.5 V ± 0.2 V 1.3 3.1 4.9 1.2 5.4 3.3 V ± 0.3 V 1.9 3.4 5 1.9 5.6 Submit Documentation Feedback ns Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): SN74AUP1G126 SN74AUP1G126 www.ti.com SCES596F – JULY 2004 – REVISED MAY 2010 SWITCHING CHARACTERISTICS over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 3 and Figure 4) PARAMETER FROM (INPUT) TO (OUTPUT) MIN 0.8 V tpd A or B Y OE Y OE Y UNIT MAX MIN MAX 1.2 V ± 0.1 V 5.8 9.3 15.1 4.3 17.9 1.5 V ± 0.1 V 4.4 6.6 10.2 3 12.1 1.8 V ± 0.15 V 3.5 5.3 8.3 2.3 9.9 2.5 V ± 0.2 V 2.7 3.9 5.8 1.9 7 3.3 V ± 0.3 V 2.4 3.2 4.7 1.8 5.7 ns 25.2 1.2 V ± 0.1 V 7 11.3 18.1 5.4 21.4 1.5 V ± 0.1 V 5.5 8.1 12.2 4.1 14.5 1.8 V ± 0.15 V 4.3 6.5 10.1 3.3 12 2.5 V ± 0.2 V 3.4 4.8 7.1 2.6 8.4 3.3 V ± 0.3 V 2.9 4.1 5.9 2.3 6.9 11 0.8 V tdis TYP 22.5 0.8 V ten TA = –40°C to 85°C TA = 25°C VCC ns 14 1.2 V ± 0.1 V 3.7 5.8 8.2 3.3 1.5 V ± 0.1 V 5.5 3.9 5.9 2.1 8 1.8 V ± 0.15 V 3.3 4.5 6.6 2.9 7.4 2.5 V ± 0.2 V 2.3 3.2 4.3 1.8 5.1 3.3 V ± 0.3 V 2.4 4.8 6.2 3.1 6.7 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): SN74AUP1G126 ns 9 SN74AUP1G126 SCES596F – JULY 2004 – REVISED MAY 2010 www.ti.com SWITCHING CHARACTERISTICS over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 3 and Figure 4) PARAMETER FROM (INPUT) TO (OUTPUT) MIN 0.8 V tpd A or B Y OE Y OE Y UNIT MAX MIN MAX 1.2 V ± 0.1 V 7.4 12 18.7 6.6 21.4 1.5 V ± 0.1 V 5.7 8.6 12.5 4.9 14.7 1.8 V ± 0.15 V 4.8 6.9 10.1 3.1 12 2.5 V ± 0.2 V 3.9 5.1 7.2 3.3 8.7 3.3 V ± 0.3 V 3.5 4.8 6 3 7 ns 33.4 1.2 V ± 0.1 V 8.8 14.1 21.8 7.4 25.5 1.5 V ± 0.1 V 6.9 10.1 14.6 5.6 17.4 1.8 V ± 0.15 V 5.6 8.1 12 4.7 14.1 2.5 V ± 0.2 V 4.3 6.1 8.5 3.8 10 3.3 V ± 0.3 V 3.7 5.2 7.1 3.4 8.3 3.7 16 0.8 V tdis TYP 29 0.8 V ten TA = –40°C to 85°C TA = 25°C VCC ns 17.7 1.2 V ± 0.1 V 5.8 10 16 1.5 V ± 0.1 V 5.7 7.7 10.9 1 10.7 1.8 V ± 0.15 V 4.5 7.7 9.8 4.4 12.5 2.5 V ± 0.2 V 3.9 5.6 7.4 3.2 9 3.3 V ± 0.3 V 3.3 8.4 10.7 6.6 10.8 ns OPERATING CHARACTERISTICS TA = 25°C PARAMETER TEST CONDITIONS Outputs enabled Cpd Power dissipation capacitance Outputs disable 10 f = 10 MHz f = 10 MHz Submit Documentation Feedback VCC TYP 0.8 V 3.8 1.2 V ± 0.1 V 3.7 1.5 V ±0.1 V 3.7 1.8 V ± 0.15 V 3.7 2.5 V ± 0.2 V 3.9 3.3 V ± 0.3 V 4 0.8 V 0 1.2 V ± 0.1 V 0 1.5 V ±0.1 V 0 1.8 V ± 0.15 V 0 2.5 V ± 0.2 V 0 2.5 V ± 0.2 V 0 3.3 V ± 0.3 V 0 UNIT pF Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): SN74AUP1G126 SN74AUP1G126 www.ti.com SCES596F – JULY 2004 – REVISED MAY 2010 PARAMETER MEASUREMENT INFORMATION (Propagation Delays, Setup and Hold Times, and Pulse Width) From Output Under Test CL (see Note A) 1 MΩ LOAD CIRCUIT CL VM VI VCC = 0.8 V VCC = 1.2 V ± 0.1 V VCC = 1.5 V ± 0.1 V VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V 5, 10, 15, 30 pF VCC/2 VCC 5, 10, 15, 30 pF VCC/2 VCC 5, 10, 15, 30 pF VCC/2 VCC 5, 10, 15, 30 pF VCC/2 VCC 5, 10, 15, 30 pF VCC/2 VCC 5, 10, 15, 30 pF VCC/2 VCC tw VCC Input VCC/2 VCC/2 VI VM Input 0V VM VOLTAGE WAVEFORMS PULSE DURATION 0V tPHL tPLH VOH VM Output VM VOL tPHL VCC Timing Input VCC/2 0V tPLH tsu VOH VM Output VCC VM VOL Data Input VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS NOTES: A. B. C. D. E. th VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES CL includes probe and jig capacitance. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf = 3 ns. The outputs are measured one at a time, with one transition per measurement. tPLH and tPHL are the same as tpd. All parameters and waveforms are not applicable to all devices. Figure 3. Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): SN74AUP1G126 11 SN74AUP1G126 SCES596F – JULY 2004 – REVISED MAY 2010 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) (Enable and Disable Times) 2 × VCC S1 5 kΩ From Output Under Test GND CL (see Note A) 5 kΩ TEST S1 tPLZ/tPZL tPHZ/tPZH 2 × VCC GND LOAD CIRCUIT CL VM VI V∆ VCC = 0.8 V VCC = 1.2 V ± 0.1 V VCC = 1.5 V ± 0.1 V VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V 5, 10, 15, 30 pF VCC/2 VCC 0.1 V 5, 10, 15, 30 pF VCC/2 VCC 0.1 V 5, 10, 15, 30 pF VCC/2 VCC 0.1 V 5, 10, 15, 30 pF VCC/2 VCC 0.15 V 5, 10, 15, 30 pF VCC/2 VCC 0.15 V 5, 10, 15, 30 pF VCC/2 VCC 0.3 V VCC Output Control Output Waveform 1 S1 at 2 × VCC (see Note B) VCC/2 0V tPLZ tPZL VCC VCC/2 VOL + V∆ VOL tPHZ tPZH Output Waveform 2 S1 at GND (see Note B) VCC/2 VCC/2 VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf = 3 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. All parameters and waveforms are not applicable to all devices. Figure 4. Load Circuit and Voltage Waveforms 12 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): SN74AUP1G126 PACKAGE OPTION ADDENDUM www.ti.com 27-Apr-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 74AUP1G126DBVRE4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74AUP1G126DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74AUP1G126DBVTE4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74AUP1G126DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74AUP1G126DCKRE4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74AUP1G126DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74AUP1G126DCKTE4 ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74AUP1G126DCKTG4 ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74AUP1G126DRLRG4 ACTIVE SOT DRL 5 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G126DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G126DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G126DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G126DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G126DRLR ACTIVE SOT DRL 5 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G126DRYR ACTIVE SON DRY 6 5000 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM SN74AUP1G126DSFR ACTIVE SON DSF 6 5000 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM SN74AUP1G126YFPR ACTIVE DSBGA YFP 6 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM SN74AUP1G126YZPR ACTIVE DSBGA YZP 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 27-Apr-2010 package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 27-Apr-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ SN74AUP1G126DBVR SOT-23 3000 180.0 9.2 DBV 5 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.23 3.17 1.37 4.0 8.0 Q3 SN74AUP1G126DBVT SOT-23 DBV 5 250 180.0 9.2 3.23 3.17 1.37 4.0 8.0 Q3 SN74AUP1G126DCKR SC70 DCK 5 3000 180.0 9.2 2.24 2.34 1.22 4.0 8.0 Q3 SN74AUP1G126DCKT SC70 DCK 5 250 180.0 9.2 2.24 2.34 1.22 4.0 8.0 Q3 SN74AUP1G126DRLR SOT DRL 5 4000 180.0 9.2 1.78 1.78 0.69 4.0 8.0 Q3 SN74AUP1G126YZPR DSBGA YZP 5 3000 180.0 8.4 1.02 1.52 0.63 4.0 8.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 27-Apr-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AUP1G126DBVR SOT-23 DBV 5 3000 202.0 201.0 28.0 SN74AUP1G126DBVT SOT-23 DBV 5 250 202.0 201.0 28.0 SN74AUP1G126DCKR SC70 DCK 5 3000 202.0 201.0 28.0 SN74AUP1G126DCKT SC70 DCK 5 250 202.0 201.0 28.0 SN74AUP1G126DRLR SOT DRL 5 4000 202.0 201.0 28.0 SN74AUP1G126YZPR DSBGA YZP 5 3000 220.0 220.0 34.0 Pack Materials-Page 2 X: Max = 930 µm, Min = 870 µm Y: Max = 1430 µm, Min = 1370 µm X: Max = 930 µm, Min = 870 µm Y: Max = 1430 µm, Min = 1370 µm IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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