TI SN74BCT574N

SN54BCT574, SN74BCT574
OCTAL TRANSPARENT D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS074C – SEPTEMBER 1991 – REVISED MARCH 2003
D
D
Operating Voltage Range of 4.5 V to 5.5 V
State-of-the-Art BiCMOS Design
Significantly Reduces ICCZ
Full Parallel Access for Loading
SN54BCT574 . . . J OR W PACKAGE
SN74BCT574 . . . DB, DW, N, OR NS PACKAGE
(TOP VIEW)
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
2D
1D
OE
VCC
1
SN54BCT574 . . . FK PACKAGE
(TOP VIEW)
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
CLK
3D
4D
5D
6D
7D
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
2Q
3Q
4Q
5Q
6Q
8D
GND
CLK
8Q
7Q
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
1Q
D
D
description/ordering information
These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
The eight flip-flops of the ’BCT574 devices are edge-triggered D-type flip-flops. On the positive transition of the
clock (CLK) input, the Q outputs are set to the logic levels that were set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without interface or pullup components.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
PDIP – N
0°C to 70°C
–55°C to 125°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TOP-SIDE
MARKING
Tube
SN74BCT574N
Tube
SN74BCT574DW
Tape and reel
SN74BCT574DWR
SOP – NS
Tape and reel
SN74BCT574NSR
BCT574
SSOP – DB
Tape and reel
SN74BCT574DBR
BT574
CDIP – J
Tube
SNJ54BCT574J
SNJ54BCT574J
CFP – W
Tube
SNJ54BCT574W
SNJ54BCT574W
LCCC – FK
Tube
SNJ54BCT574FK
SOIC – DW
SN74BCT574N
BCT574
SNJ54BCT574FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54BCT574, SN74BCT574
OCTAL TRANSPARENT D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS074C – SEPTEMBER 1991 – REVISED MARCH 2003
description/ordering information (continued)
OE does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
FUNCTION TABLE
(each flip-flop)
INPUTS
OE
CLK
D
OUTPUT
Q
L
↑
H
H
L
↑
L
L
L
H or L
X
Q0
H
X
X
Z
logic diagram (positive logic)
OE
CLK
1
11
C1
1D
2
19
1Q
1D
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Voltage range applied to any output in the disabled or power-off state, VO . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Voltage range applied to any output in the high state, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 mA
Current into any output in the low state: SN54BCT574 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74BCT574 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54BCT574, SN74BCT574
OCTAL TRANSPARENT D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS074C – SEPTEMBER 1991 – REVISED MARCH 2003
recommended operating conditions (see Note 3)
SN54BCT574
SN74BCT574
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
IIK
Low-level input voltage
0.8
0.8
V
Input clamp current
–18
–18
mA
IOH
IOL
High-level output current
–12
–15
mA
Low-level output current
48
64
mA
High-level input voltage
2
2
V
V
TA
Operating free-air temperature
–55
125
0
70
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
SN54BCT574
TYP†
MAX
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V
MIN
II = –18 mA
IOH = –3 mA
SN74BCT574
TYP†
MAX
MIN
–1.2
IOH = –12 mA
IOH = –15 mA
2.4
3.3
2
3.2
–1.2
2.4
V
3.3
V
2
0.38
UNIT
3.1
VOL
VCC = 4
4.5
5V
IOL = 48 mA
IOL = 64 mA
0.55
II
IIH
VCC = 5.5 V,
VCC = 5.5 V,
VI = 5.5 V
VI = 2.7 V
IIL
IOS‡
VCC = 5.5 V,
VCC = 5.5 V,
VI = 0.5 V
VO = 0
IOZH
IOZL
VCC = 5.5 V,
VCC = 5.5 V,
VO = 2.7 V
VO = 0.5 V
–50
µA
ICCL
ICCH
VCC = 5.5 V,
VCC = 5.5 V,
Outputs open
38.1
62
38.1
62
mA
Outputs open
4.9
8
4.9
8
mA
ICCZ
Ci
VCC = 5.5 V,
VCC = 5 V,
Outputs open
4.5
8
4.9
8
mA
0.42
V
0.4
0.4
mA
20
20
µA
–0.6
–100
0.55
–225
–100
50
–50
VI = 2.5 V or 0.5 V
VO = 2.5 V or 0.5 V
Co
VCC = 5 V,
† All typical values are at VCC = 5 V, TA = 25°C.
‡ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
–0.6
mA
–225
mA
50
µA
5.5
pF
7.5
pF
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
VCC = 5 V,
TA = 25°C
MIN
fclock
tw
Clock frequency
tsu
Setup time,
time data before CLK↑
th
Hold time, data after CLK↑
MAX
SN54BCT574
MIN
77
Pulse duration, CLK high or low
MAX
SN74BCT574
MIN
77
77
6.5
6.5
6.5
High
4.5
4.5
4.5
Low
6
6
6
High or low
0
1
0
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
MAX
MHz
ns
ns
ns
3
SN54BCT574, SN74BCT574
OCTAL TRANSPARENT D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS074C – SEPTEMBER 1991 – REVISED MARCH 2003
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
4
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
TA = 25°C
MIN
TYP
SN54BCT574
MAX
77
CLK
Q
OE
Q
OE
Q
POST OFFICE BOX 655303
MIN
MAX
77
SN74BCT574
MIN
77
MHz
2.2
6.5
8.6
2.2
11.2
2.2
10
2.8
6.1
8
2.8
9.7
2.8
8.9
2.5
6.4
8.1
2.5
10.9
2.5
10.4
3.7
7.3
9.2
3.7
11.3
3.7
10.9
1
4.4
7.4
1
8
1
7.5
1.3
4.2
5.8
1.3
7.1
1.3
6.4
• DALLAS, TEXAS 75265
UNIT
MAX
ns
ns
ns
SN54BCT574, SN74BCT574
OCTAL TRANSPARENT D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS074C – SEPTEMBER 1991 – REVISED MARCH 2003
PARAMETER MEASUREMENT INFORMATION
7 V (tPZL, tPLZ, O.C.)
S1
Open
(all others)
From Output
Under Test
Test
Point
CL
(see Note A)
R1
From Output
Under Test
R1
Test
Point
CL
(see Note A)
R2
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
RL = R1 = R2
LOAD CIRCUIT FOR
3-STATE AND OPEN-COLLECTOR OUTPUTS
High-Level
Pulse
(see Note B)
3V
Timing Input
(see Note B)
3V
1.5 V
1.5 V
0V
1.5 V
tw
0V
Data Input
(see Note B)
3V
th
tsu
Low-Level
Pulse
3V
1.5 V
1.5 V
0V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
3V
Input
(see Note B)
1.5 V
1.5 V
0V
tPLH
In-Phase
Output
(see Note D)
VOH
1.5 V
1.5 V
VOL
VOH
1.5 V
1.5 V
0V
tPLZ
1.5 V
Waveform 1
(see Notes C and D)
3.5 V
VOL
tPHZ
tPLH
1.5 V
1.5 V
tPZL
tPHL
tPHL
Out-of-Phase
Output
(see Note D)
Output
Control
(low-level enable)
0.3 V
tPZH
Waveform 2
(see Notes C and D)
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (see Note D)
VOH
1.5 V
0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, tr = tf ≤ 2.5 ns, duty cycle = 50%.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
E. When measuring propagation delay times of 3-state outputs, switch S1 is open.
F. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
5962-9583601Q2A
ACTIVE
LCCC
FK
20
1
TBD
5962-9583601QRA
ACTIVE
CDIP
J
20
1
TBD
POST-PLATE N / A for Pkg Type
5962-9583601QSA
ACTIVE
CFP
W
20
1
TBD
SN74BCT574DBR
ACTIVE
SSOP
DB
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74BCT574DBRE4
ACTIVE
SSOP
DB
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74BCT574DBRG4
ACTIVE
SSOP
DB
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74BCT574DW
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74BCT574DWE4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74BCT574DWG4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74BCT574DWR
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74BCT574DWRE4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74BCT574DWRG4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74BCT574N
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74BCT574NE4
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74BCT574NSR
ACTIVE
SO
NS
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74BCT574NSRE4
ACTIVE
SO
NS
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74BCT574NSRG4
ACTIVE
SO
NS
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SNJ54BCT574FK
ACTIVE
LCCC
FK
20
1
TBD
SNJ54BCT574J
ACTIVE
CDIP
J
20
1
TBD
A42 SNPB
N / A for Pkg Type
SNJ54BCT574W
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
A42 SNPB
N / A for Pkg Type
A42
N / A for Pkg Type
POST-PLATE N / A for Pkg Type
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2007
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-May-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
Device
19-May-2007
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74BCT574DBR
DB
20
MLA
330
16
8.2
7.5
2.5
12
16
Q1
SN74BCT574DWR
DW
20
MLA
330
24
10.8
13.0
2.7
12
24
Q1
SN74BCT574NSR
NS
20
MLA
330
24
8.2
13.0
2.5
12
24
Q1
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
SN74BCT574DBR
DB
20
MLA
342.9
336.6
28.58
SN74BCT574DWR
DW
20
MLA
333.2
333.2
31.75
SN74BCT574NSR
NS
20
MLA
333.2
333.2
31.75
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-May-2007
Pack Materials-Page 3
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
A
B
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
9
22
8
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
7
52
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
25
5
26
27
28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
Falls within JEDEC MS-004
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
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