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SCDS142A − OCTOBER 2003 − REVISED NOVEMBER 2003 D High-Bandwidth Data Path D D D D D D D D D Data and Control Inputs Provide (Up To 500 MHz†) 5-V Tolerant I/Os with Device Powered-Up or Powered-Down Low and Flat ON-State Resistance (ron) Characteristics Over Operating Range (ron = 4.5 Ω Typical) Rail-to-Rail Switching on Data I/O Ports − 0- to 5-V Switching With 3.3-V VCC − 0- to 3.3-V Switching With 2.5-V VCC B-Port Outputs Are Precharged by Bias Voltage (BIASV) to Minimize Signal Distortion During Live Insertion and Hot-Plugging Supports PCI Hot Plug Bidirectional Data Flow, With Near-Zero Propagation Delay Low Input/Output Capacitance Minimizes Loading and Signal Distortion (Cio(OFF) = 3.5 pF Typical) Fast Switching Frequency (fON = 20 MHz Max) D D D D D D D D Undershoot Clamp Diodes Low Power Consumption (ICC = 0.75 mA Typical) VCC Operating Range From 2.3 V to 3.6 V Data I/Os Support 0 to 5-V Signaling Levels (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V) Control Inputs Can be Driven by TTL or 5-V/3.3-V CMOS Outputs Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Performance Tested Per JESD 22 − 2000-V Human-Body Model (A114-B, Class II) − 1000-V Charged-Device Model (C101) Supports Both Digital and Analog Applications: PCI Interface, Differential Signal Interface, Memory Interleaving, Bus Isolation, Low-Distortion Signal Gating † For additional information regarding the performance characteristics of the CB3Q family, refer to the TI application report, CBT-C, CB3T, and CB3Q Signal-Switch Families, literature number SCDA008. DBQ, DGV, OR PW PACKAGE (TOP VIEW) ON A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 GND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 BIASV Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated "#$%&'()"%# "* +,&&-#) (* %$ .,/0"+()"%# 1()- &%1,+)* +%#$%&' )% *.-+"$"+()"%#* .-& )2- )-&'* %$ -3(* #*)&,'-#)* *)(#1(&1 4(&&(#)5 &%1,+)"%# .&%+-**"#6 1%-* #%) #-+-**(&"05 "#+0,1)-*)"#6 %$ (00 .(&('-)-&* POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 !! SCDS142A − OCTOBER 2003 − REVISED NOVEMBER 2003 description/ordering information The SN74CB3Q6800 is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state resistance allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Specifically designed to support high-bandwidth applications, the SN74CB3Q6800 provides an optimized interface solution ideally suited for broadband communications, networking, and data-intensive computing systems. The SN74CB3Q6800 is a 10-bit bus switch with a single output-enable (ON) input. When ON is low, the 10-bit bus switch is ON and the A port is connected to the B port, allowing bidirectional data flow between ports. When ON is high, the 10-bit bus switch is OFF and a high-impedance state exists between the A and B ports. The B port is precharged to bias voltage (BIASV) through the equivalent of a 10-kΩ resistor when ON is high, or if the device is powered down (VCC = 0 V). During insertion (or removal) of a card into (or from) an active bus, the card’s output voltage may be close to GND. When the connector pins make contact, the card’s parasitic capacitance tries to force the bus signal to GND, creating a possible glitch on the active bus. This glitching effect can be reduced by using a bus switch with precharged bias voltage (BIASV) of the bus switch equal to the input threshold voltage level of the receivers on the active bus. This method will ensure that any glitch produced by insertion (or removal) of the card will not cross the input threshold region of the receivers on the active bus, minimizing the effects of live-insertion noise. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry prevents damaging current backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, ON should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION SSOP (QSOP) − DBQ −40°C to 85°C ORDERABLE PART NUMBER PACKAGE† TA TSSOP − PW Tape and reel SN74CB3Q6800DBQR Tube SN74CB3Q6800PW Tape and reel SN74CB3Q6800PWR TOP-SIDE MARKING CB3Q6800 BY800 TVSOP − DGV Tape and reel SN74CB3Q6800DGVR BY800 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE 2 INPUT ON INPUT/OUTPUT A FUNCTION L B A port = B port H Z Disconnect B port = BIASV POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 !! SCDS142A − OCTOBER 2003 − REVISED NOVEMBER 2003 logic diagram (positive logic) 13 BIASV 2 A1 23 B1 SW 11 A10 14 B10 SW 1 ON simplified schematic, each FET switch (SW) BIASV B A VCC Charge Pump EN† † EN is the internal enable signal applied to the switch. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 !! SCDS142A − OCTOBER 2003 − REVISED NOVEMBER 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V BIAS supply voltage range, BIASV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Control input voltage range, VIN (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Switch I/O voltage range, VI/O (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Control input clamp current, IIK (VIN < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA I/O port clamp current, II/OK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA ON-state switch current, II/O (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±64 mA Continuous current through VCC or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 5): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to ground unless otherwise specified. 2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. VI and VO are used to denote specific conditions for VI/O. 4. II and IO are used to denote specific conditions for II/O. 5. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 6) VCC BIASV Supply voltage Bias supply voltage VIH High-level control input voltage VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VIL Low-level control input voltage VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VI/O TA Data input/output voltage Operating free-air temperature MIN MAX 2.3 3.6 UNIT V V 0 5 1.7 5.5 2 5.5 0 0.7 0 0.8 0 5.5 V −40 85 °C V V NOTE 6: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. BIASV is a supply voltage, not a control input. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 !! SCDS142A − OCTOBER 2003 − REVISED NOVEMBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK IIN TEST CONDITIONS MIN VCC = 3.6 V, VCC = 3.6 V, II = −18 mA VIN = 0 to 5.5 V VCC = 3.V, BIASV = 2.4 V, VO = 0, Switch OFF, VIN = VCC or GND IOZ‡ VCC = 3.6 V, VO = 0 to 5.5 V, VI = 0, Switch OFF, VIN = VCC or GND Ioff VCC = 0, VI = 0 ICC VCC = 3.6 V, VO = 0 to 5.5 V, II/O = 0, Switch ON or OFF, One input at 3 V, Other inputs at VCC or GND Control inputs IO B port ∆ICC§ Control inputs ICCD¶ Per control input Cin Control inputs VCC = 3.3 V, Cio(OFF) A port VCC = 3.3 V, Cio(ON) ron# VCC = 3.6 V, VCC = 3.6 V, TYP† MAX UNIT −1.8 V ±1 µA 0.2 VIN = VCC or GND 0.75 mA ±1 µA 1 µA 2 mA 30 A and B ports open, Control input switching at 50% duty cycle VIN = 5.5 V, 3.3 V, or 0 Switch OFF, VI/O = 5.5 V, 3.3 V, or 0 VIN = VCC or GND, µA 0.38 0.45 mA/ MHz 2.5 3.5 pF 3.5 5 pF 9 11 pF VCC = 3.3 V, Switch ON, VIN = VCC or GND, VI/O = 5.5 V, 3.3 V, or 0 VCC = 2.3 V, TYP at VCC = 2.5 V VI = 0, VI = 1.7 V, IO = 30 mA IO = −15 mA 4.5 8 4.8 9 VCC = 3 V VI = 0, VI = 2.4 V, IO = 30 mA IO = −15 mA 4.5 6 4.6 8 Ω VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins. † All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C. ‡ For I/O ports, the parameter IOZ includes the input leakage current. § This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. ¶ This parameter specifies the dynamic power-supply current associated with the operating frequency of a single control input (see Figure 2). # Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages of the two (A or B) terminals. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3) PARAMETER TEST CONDITIONS fON|| tpdk tPZH BIASV = GND tPZL BIASV = 3 V tPHZ BIASV = GND tPLZ BIASV = 3 V FROM (INPUT) TO (OUTPUT) VCC = 2.5 V ± 0.2 V MIN MAX VCC = 3.3 V ± 0.3 V MIN UNIT MAX ON A or B 10 20 A or B B or A 0.135 0.225 ON A or B ON A or B 1.5 8.5 1.5 6.7 1.5 8.5 1.5 6.7 1 5 1 5 1 6.9 1 6.9 MHz ns ns ns || Maximum switching frequency for control input (VO > VCC, VI = 5 V, RL ≥ 1 MΩ, CL = 0). k The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 !! SCDS142A − OCTOBER 2003 − REVISED NOVEMBER 2003 TYPICAL ron vs VI r on − ON-State Resistance − Ω 16 VCC = 3.3 V TA = 25°C IO = −15 mA 14 12 10 8 6 4 2 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VI − V Figure 1. Typical ron vs VI, VCC = 3.3 V and IO = −15 mA TYPICAL ICC vs ON SWITCHING FREQUENCY 12 VCC = 3.3 V TA = 25°C A and B ports Open, BIASV Open 10 ICC − mA 8 6 4 2 0 0 2 4 6 8 10 12 14 16 ON Switching Frequency − MHz Figure 2. Typical ICC vs ON Switching Frequency, VCC = 3.3 V 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 18 20 !! SCDS142A − OCTOBER 2003 − REVISED NOVEMBER 2003 PARAMETER MEASUREMENT INFORMATION VCC Input Generator VIN 50 Ω 50 Ω VG1 TEST CIRCUIT DUT Input Generator VI S1 RL VO 50 Ω VG2 CL (see Note A) RL TEST VCC S1 RL VI CL tpd(s) 2.5 V ± 0.2 V 3.3 V ± 0.3 V Open Open 500 Ω 500 Ω VCC or GND VCC or GND 30 pF 50 pF tPLZ/tPZL 2.5 V ± 0.2 V 3.3 V ± 0.3 V 2 × VCC 2 × VCC 500 Ω 500 Ω GND GND 30 pF 50 pF 0.15 V 0.3 V tPHZ/tPZH 2.5 V ± 0.2 V 3.3 V ± 0.3 V GND GND 500 Ω 500 Ω VCC VCC 30 pF 50 pF 0.15 V 0.3 V Output Control (VIN) V∆ VCC VCC/2 VCC VCC/2 0V tPLH VOH Output VCC/2 Output Waveform 1 S1 at 2 × VCC (see Note B) tPLZ VCC VCC/2 tPZH tPHL VCC/2 VOL VCC/2 0V tPZL VCC/2 Open GND 50 Ω Output Control (VIN) 2 × VCC Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (tpd(s)) VOL + V∆ VOL tPHZ VCC/2 VOH − V∆ VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). H. All parameters and waveforms are not applicable to all devices. Figure 3. Test Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°–8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSOI004E JANUARY 1995 – REVISED MAY 2002 DBQ (R–PDSO–G**) PLASTIC SMALL–OUTLINE PACKAGE 0.012 (0,30) 0.008 (0,20) 0.025 (0,64) 0.005 (0,13) 13 24 0.244 (6,20) 0.228 (5,80) 0.157 (3,99) 0.150 (3,81) 0.008 (0,20) NOM Gauge Plane 1 12 0.010 (0,25) A 0°–8° 0.035 (0,89) 0.016 (0,40) 0.069 (1,75) MAX Seating Plane 0.010 (0,25) 0.004 (0,10) 0.004 (0,10) PINS ** 16 20 24 28 A MAX 0.197 (5,00) 0.344 (8,74) 0.344 (8,74) 0.394 (10,01) A MIN 0.189 (4,80) 0.337 (8,56) 0.337 (8,56) 0.386 (9,80) M0–137 VARIATION AB AD AE AF DIM D 4073301/F 02/02 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). D. Falls within JEDEC MO–137. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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