SN54HCT74, SN74HCT74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCLS169B – DECEMBER 1982 – REVISED MAY 1997 D D SN54HCT74 . . . J OR W PACKAGE SN74HCT74 . . . D, N, OR PW PACKAGE (TOP VIEW) Inputs Are TTL-Voltage Compatible Package Options Include Plastic Small-Outline (D), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs 1CLR 1D 1CLK 1PRE 1Q 1Q GND description 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D 2CLK 2PRE 2Q 2Q The ’HCT74 contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs. 1CLK NC 1PRE NC 1Q The SN54HCT74 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74HCT74 is characterized for operation from –40°C to 85°C. NC – No internal connection 1D 1CLR NC VCC 2CLR SN54HCT74 . . . FK PACKAGE (TOP VIEW) 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2D NC 2CLK NC 2PRE 1Q GND NC 2Q 2Q 4 FUNCTION TABLE OUTPUT INPUTS PRE CLR CLK D Q Q L H X X H L H L X X L L X X L H† H H† H H ° H H L H H ° L L H H H L X Q0 Q0 † This configuration is unstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1997, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54HCT74, SN74HCT74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCLS169B – DECEMBER 1982 – REVISED MAY 1997 logic symbol† 1PRE 1CLK 1D 1CLR 2PRE 2CLK 2D 2CLR 4 S 3 5 C1 2 6 1D 1 1Q 1Q R 10 9 11 12 8 13 2Q 2Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, N, PW, and W packages. logic diagram (positive logic) PRE CLK C C Q TG C C C C C D TG TG TG Q C C C CLR absolute maximum ratings over operating free-air temperature range‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54HCT74, SN74HCT74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCLS169B – DECEMBER 1982 – REVISED MAY 1997 recommended operating conditions SN54HCT74 SN74HCT74 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage 0 0.8 0 0.8 V Input voltage 0 0 Output voltage 0 0 VCC VCC V VO tt VCC VCC 0 500 0 500 ns TA Operating free-air temperature –55 125 –40 85 °C High-level input voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V 2 Input transition (rise and fall) time 2 V V V electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC VOH VI = VIH or VIL IOH = –20 µA IOH = –4 mA 45V 4.5 VOL VI = VIH or VIL IOL = 20 µA IOL = 4 mA 45V 4.5 II ICC VI = VCC or 0 VI = VCC or 0, ∆ICC† MIN MIN MAX SN74HCT74 MIN 4.4 4.499 4.4 4.4 4.3 3.7 3.84 5.5 V 4.5 V to 5.5 V MAX UNIT V 0.001 0.1 0.1 0.1 0.17 0.26 0.4 0.33 ±0.1 ±100 ±1000 ±1000 nA 4 80 40 µA 1.4 2.4 3 2.9 mA 3 10 10 10 pF 5.5 V Ci SN54HCT74 3.98 5.5 V IO = 0 One input at 0.5 V or 2.4 V, Other inputs at 0 or VCC TA = 25°C TYP MAX V † This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC. timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC fclock l k Clock frequency lo PRE or CLR low tw Pulse duration CLK high or low Data tsu ↑ Setup time before CLK↑ PRE or CLR inactive inacti e th Hold time, time data after CLK↑ TA = 25°C MIN MAX SN54HCT74 SN74HCT74 MIN MAX MIN MAX 4.5 V 0 27 0 18 0 22 5.5 V 0 30 0 20 0 24 4.5 V 16 24 20 5.5 V 14 21 18 4.5 V 18 27 23 5.5 V 16 24 21 4.5 V 12 18 15 5.5 V 11 16 14 4.5 V 0 0 0 5.5 V 0 0 0 4.5 V 0 0 0 5.5 V 0 0 0 UNIT MHz ns ns ns PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54HCT74, SN74HCT74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCLS169B – DECEMBER 1982 – REVISED MAY 1997 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax PRE or CLR Q or Q tpd d CLK Q or Q tt Q or Q VCC MIN TA = 25°C TYP MAX SN54HCT74 MIN MAX SN74HCT74 MIN 4.5 V 27 40 18 22 5.5 V 30 46 20 24 MAX UNIT MHz 4.5 V 21 35 53 44 5.5 V 17 31 48 40 4.5 V 20 28 42 35 5.5 V 18 25 38 31 4.5 V 8 15 22 19 5.5 V 7 14 20 17 ns ns operating characteristics, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance per flip-flop No load TYP 35 UNIT pF PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point 3V High-Level Pulse 1.3 V 0V CL = 50 pF (see Note A) tw 1.3 V 1.3 V 0V 3V 1.3 V 3V Low-Level Pulse LOAD CIRCUIT Input 1.3 V VOLTAGE WAVEFORMS PULSE DURATIONS 1.3 V 0V tPLH In-Phase Output 1.3 V 10% tPHL 90% 90% tr Out-ofPhase Output tPHL 90% VOH Reference 1.3 V Input 10% V OL tf tPLH 1.3 V 10% tf 1.3 V 10% 90% VOH Data Input 1.3 V 0.3 V 3V 1.3 V 0V tsu 2.7 V VOL tr tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES th 2.7 V 3V 1.3 V 0.3 V 0 V tf VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time with one input transition per measurement. E. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. 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