54ACT11109, 74ACT11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCAS451 – FEBRUARY 1987 – REVISED APRIL 1993 • • • 1PRE 1Q 1Q GND 2Q 2Q 2PRE 2CLK 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 1CLK 1K 1J 1CLR VCC 2CLR 2J 2K 54ACT11109 . . . FK PACKAGE (TOP VIEW) 1J 1CLR NC VCC description These devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (1PRE or 2PRE) or clear (1CLR or 2CLR) input sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K and tying J high. They also can perform as D-type flip-flops if J and K are tied together. 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 1Q GND NC 1K 1CLK NC 1PRE 1Q 2CLR • 54ACT11109 . . . J PACKAGE 74ACT11109 . . . D OR N PACKAGE (TOP VIEW) Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs 2J 2K NC 2CLK 2PRE 2Q 2Q • • NC – No internal connection The 54ACT11109 is characterized for operation over the full military temperature range of – 55°C to 125°C. The 74ACT11109 is characterized for operation from – 40°C to 85°C. FUNCTION TABLE INPUTS OUTPUTS PRE CLR CLK J K Q Q L H X X X H L H L X X X L H L L X X X H† H† H H ↑ L L L H H H ↑ H L H H ↑ L H Q0 Q0 H H ↑ H H H L H H L X X Q0 Toggle Q0 † This configuration is nonstable; that is, it will not persist when either PRE or CLR returns to the inactive (high) level. EPIC is a trademark of Texas Instruments Incorporated. Copyright 1993, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–1 54ACT11109, 74ACT11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCAS451 – FEBRUARY 1987 – REVISED APRIL 1993 logic symbol† 1 1PRE 1J 1CLK S 14 16 1CLR 2PRE 2J 2CLK 1Q C1 15 1K 2 1J 3 1K 13 1Q R 7 10 6 2Q 8 9 5 2K 2Q 11 2CLR † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 100 mA Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. recommended operating conditions 54ACT11109 MAX MIN MAX 4.5 5.5 4.5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 0 VO IOH Output voltage 0 IOL ∆t /∆v Low-level output current TA Operating free-air temperature 2–2 High-level input voltage 74ACT11109 MIN 2 2 0.8 High-level output current VCC VCC 0 0 – 24 24 Input transition rise or fall rate POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT V V 0.8 V VCC VCC V – 24 mA V 24 mA 0 10 0 10 ns/ V – 55 125 – 40 85 °C 54ACT11109, 74ACT11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCAS451 – FEBRUARY 1987 – REVISED APRIL 1993 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 4.5 V IOH = – 50 µA VOH IOH = – 24 mA IOH = – 50 mA† IOH = – 75 mA† TA = 25°C TYP MAX 54ACT11109 MIN MAX IOL = 50 mA† IOL = 75 mA† MIN 4.4 4.4 5.5 V 5.4 5.4 5.4 4.5 V 3.94 3.7 3.8 5.5 V 4.94 4.7 4.8 ∆ICC‡ One input at 3.4 V, Other inputs at VCC or GND IO = 0 V 4.5 V 0.1 0.1 5.5 V 0.1 0.1 0.1 0.1 4.5 V 0.36 0.5 0.44 5.5 V 0.36 0.5 0.44 V 1.65 5.5 V VI = VCC or GND VI = VCC or GND, UNIT 3.85 5.5 V II ICC MAX 3.85 5.5 V IOL = 24 mA 74ACT11109 4.4 5.5 V IOL = 50 µA VOL MIN 1.65 5.5 V ± 0.1 ±1 ±1 µA 5.5 V 4 80 40 µA 5.5 V 0.9 1 1 mA Ci VI = VCC or GND 5V 3.5 † Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. ‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC. pF timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX fclock Clock frequency 0 tw Pulse duration tsu Setup time before CLK↑ th Hold time, data after CLK↑ 100 54ACT11109 74ACT11109 MIN MAX MIN MAX 0 100 0 100 PRE or CLR low 5.5 5.5 5.5 CLK high or low 5 5 5 Data high or low 5.5 5.5 5.5 2 2 2 0 0 0 PRE or CLR inactive UNIT MHz ns ns ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL FROM (INPUT) TO (OUTPUT) PRE or CLR Q or Q CLK Q or Q POST OFFICE BOX 655303 MIN TA = 25°C TYP MAX 54ACT11109 MIN MAX MIN MAX 100 125 1.5 5.5 8.6 1.5 9.8 1.5 9.2 1.5 6 10.8 1.5 12.6 1.5 11.8 1.5 6 8.3 1.5 9.7 1.5 9.1 1.5 5.5 7.6 1.5 9 1.5 8.3 • DALLAS, TEXAS 75265 100 74ACT11109 100 UNIT MHz ns ns 2–3 54ACT11109, 74ACT11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCAS451 – FEBRUARY 1987 – REVISED APRIL 1993 operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance per flip-flop CL = 50 pF, f = 1 MHz TYP UNIT 31 pF PARAMETER MEASUREMENT INFORMATION From Output Under Test tw CL = 50 pF (see Note A) 3V 500 Ω Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS LOAD CIRCUIT 3V Input (see Note B) 3V Timing Input (see Note B) 0V tsu Data Input 1.5 V 0V tPHL tPLH 1.5 V th 1.5 V In-Phase Output 50% VCC 3V 1.5 V tPLH tPHL 1.5 V 0V Out-of-Phase Output VOH 50% VCC VOL 50% VCC VOH 50% VCC VOL VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 2–4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. 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