SN54/74LS323 8-BIT SHIFT/STORAGE REGISTER WITH 3-STATE OUTPUTS The SN54 / 74LS323 is an 8-Bit Universal Shift / Storage Register with 3-state outputs. Its function is similar to the SN54 / 74LS299 with the exception of Synchronous Reset. Parallel load inputs and flip-flop outputs are multiplexed to minimize pin count. Separate inputs and outputs are provided for flip-flops Q0 and Q7 to allow easy cascading. Four operation modes are possible: hold (store), shift left, shift right, and parallel load. All modes are activated on the LOW-to-HIGH transition of the Clock. 8-BIT SHIFT/STORAGE REGISTER WITH 3-STATE OUTPUTS LOW POWER SCHOTTKY • Common I/O for Reduced Pin Count • Four Operation Modes: Shift Left, Shift Right, Parallel Load and Store • Separate Continuous Inputs and Outputs from Q0 and Q7 Allow Easy • • • • Cascading Fully Synchronous Reset 3-State Outputs for Bus Oriented Applications Input Clamp Diodes Limit High-Speed Termination Effects ESD > 3500 Volts J SUFFIX CERAMIC CASE 732-03 20 1 N SUFFIX PLASTIC CASE 738-03 20 1 CONNECTION DIAGRAM DIP (TOP VIEW) VCC S1 20 19 DS7 Q7 18 17 I/O7 I/O5 I/O3 I/O1 CP 16 15 14 13 12 DS0 11 DW SUFFIX SOIC CASE 751D-03 20 1 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 1 S0 8 2 3 4 5 6 7 OE1 OE2 I/O6 I/O4 I/O2 I/O0 Q0 ORDERING INFORMATION SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXDW SOIC 9 10 SR GND PIN NAMES CP DS0 DS7 I/On OE1, OE2 Q0, Q7 S0, S1 SR LOADING (Note a) Clock Pulse (active positive going edge) Input Serial Data Input for Right Shift Serial Data Input for Left Shift Parallel Data Input or Parallel Output (3-State) (Note c) 3-State Output Enable (active LOW) Inputs Serial Outputs (Note b) Mode Select Inputs Synchronous Reset (active LOW) Input NOTES: a) 1 TTL LOAD = 40 µA HIGH/1.6 mA LOW. b) The output LOW drive factor is 2.5 U.L for Military (54) and 5 U.L. for Commercial Temperature Ranges. c) The output LOW drive factor is 7.5 U.L for Military (54) and 15 U.L. for Commercial Temperature Ranges. The output HIGH drive factor is 25 U.L. for Military (54) and 65 U.L. for Commercial Temperature Ranges. FAST AND LS TTL DATA 5-1 HIGH LOW 0.5 U.L. 0.5 U.L. 0.5 U.L. 1.0 U.L. 65 (25) U.L. 0.5 U.L. 10 U.L. 1 U.L. 0.5 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.5 U.L. 15 (7.5) U.L. 0.25 U.L. 5 (2.5) U.L. 0.25 U.L. SN54/74LS323 S1 19 S0 LOGIC DIAGRAM 1 18 DS7 DS0 11 9 SR 12 CP Q0 OE1 OE2 D CP Q 8 D CP Q D CP Q D CP Q 13 6 14 D CP Q D CP Q D CP Q D CP Q 17 Q7 2 7 3 I/O0 I/O1 I/O2 5 I/O3 I/O4 15 I/O5 4 I/O6 16 I/O7 FUNCTIONAL DESCRIPTION 2. When S0 = S1 = 1, I/O0–I/O7 are parallel inputs to flip-flops Q0–Q7 respectively, and the outputs of Q0–Q7 are in the high impedance state regardless of the state of OE1 or OE2. The logic diagram and truth table indicate the functional characteristics of the SN54/74LS323 Universal Shift/Storage Register. This device is similar in operation to the SN54/74LS299 except for synchronous reset. A partial list of the common features are described below: An important unique feature of the SN54/74LS323 is a fully Synchronous Reset that requires only to be stable at least one setup time prior to the positive transition of the Clock Pulse. 1. They use eight D-type edge-triggered flip-flops that respond only to the LOW-to-HIGH transition of the Clock (CP). The only timing restriction, therefore, is that the mode control (S0, S1) and data inputs (DS0, DS7, I/O0–I/O7) may be stable at least a setup time prior to the positive transition of the Clock Pulse. TRUTH TABLE INPUTS SR S1 S0 OE1 OE2 L L L X X H X X H H X X L L L X X L H H L L H H RESPONSE CP DS0 DS7 X H X X X X X X X Synchronous Reset; Q0 = Q7 = LOW I/O voltage undetermined L L L L X X X X Synchronous Reset; Q0 = Q7 = LOW I/O voltage LOW H H X L X L D D X X Shift Right; Dº Q0; Q0º Q1; etc. Shift Right; Dº Q0 & I/O0; Q0º Q1 & I/O1; etc. H H L L X L X L X X D D Shift Left; Dº Q7; Q7º Q6; etc. Shift Left; Dº Q7 & I/O7; Q7º Q6 & I/O6; etc. H H H X X X X Parallel Load I/Onº Qn H H L L L L H X X H X X X X X X Hold; I/O Voltage Undetermined H L L L L X X X Hold; I/On = Qn H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial FAST AND LS TTL DATA 5-2 SN54/74LS323 GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 74 4.5 4.75 5.0 5.0 5.5 5.25 V TA Operating Ambient Temperature Range 54 74 – 55 0 25 25 125 70 °C IOH Output Current — High Q0, Q7 54, 74 – 0.4 mA IOL Output Current — Low Q0, Q7 Q0, Q7 54 74 4.0 8.0 mA IOH Output Current — High I/O0 – I/O7 I/O0 – I/O7 54 74 – 1.0 – 2.6 mA IOL Output Current — Low I/O0 – I/O7 I/O0 – I/O7 54 74 12 24 mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Min Parameter Typ Max Unit 2.0 Test Conditions V Guaranteed Input HIGH Voltage for All Inputs V Guaranteed Input LOW Voltage for All Inputs V VCC = MIN, IIN = – 18 mA VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage Output HIGH Voltage I/O0 – I/O7 54 2.4 3.2 V VOH 74 2.4 3.1 V Output HIGH Voltage Q0, Q7 54 2.5 3.4 V VOH 74 2.7 3.4 V Output LOW Voltage I/O0 – I/O7 54, 74 0.25 0.4 V VOL IOL = 12 mA 74 0.35 0.5 V IOL = 24 mA Output LOW Voltage Q0 – Q7 54, 74 0.4 V VOL IOL = 4.0 mA 74 0.5 V IOL = 8.0 mA 54 0.7 74 0.8 – 0.65 – 1.5 VCC = MIN, IOH = MAX VCC = MIN, IOH = MAX VCC = VCC MIN, VIN = VIL or VIH per Truth Table VCC = VCC MIN, VIN = VIL or VIH per Truth Table IOZH Output Off Current HIGH I/O0 – I/O7 40 µA VCC = MAX, VOUT = 2.7 V IOZL Output Off Current LOW I/O0 – I/O7 – 400 µA VCC = MAX, VOUT = 0.4 V Others 20 µA S0, S1, I/O0 – I/O7 40 µA Others 0.1 mA S0, S1 0.2 mA I/O0 – I/O7 0.1 mA Others – 0.4 mA S0, S1 – 0.8 mA IIH Input HIGH Current Input LOW Current IIL IOS ICC Short Circuit Current (Note 1) VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 5.5 V VCC = MAX, VIN = 0.4 V Qo, Q7 – 20 –100 mA VCC = MAX I/O0 – I/O7 – 30 –130 mA VCC = MAX 53 mA VCC = MAX Power Supply Current Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 5-3 SN54/74LS323 AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Limits Symbol Parameter Min Typ 25 35 Max Unit Test Conditions fMAX Maximum Clock Frequency MHz tPHL tPLH Propagation Delay, Clock to Q0 or Q7 26 22 39 33 ns tPHL tPLH Propagation Delay, Clock to I/O0 – I/O7 25 17 39 25 ns tPZH tPZL Output Enable Time 14 20 21 30 ns tPHZ tPLZ Output Disable Time 10 10 15 15 ns CL = 5.0 pF Max Unit Test Conditions CL = 15 pF CL = 45 pF, RL = 667 Ω AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V) Limits Symbol Parameter Min Typ tW Clock Pulse Width HIGH 25 ns tW Clock Pulse Width LOW 15 ns tW Clear Pulse Width LOW 20 ns ts Data Setup Time 20 ns ts Select Setup Time 35 ns th Data Hold Time 0 ns th Select Hold Time 10 ns trec Recovery Time 20 ns FAST AND LS TTL DATA 5-4 VCC = 5.0 V SN54/74LS323 3-STATE WAVEFORMS VIN 1.3 V tPLH VOUT 1.3 V Figure 1 VE tPHL 1.3 V 1.3 V VE 1.5 V tPZL VOUT 1.3 V Figure 2 VE 1.5 V 1.3 V tPLH tPHL 1.3 V VOUT VIN 1.3 V 1.5 V VE tPLZ 1.5 V 0.5 V ≈ 1.5 V VOL 1.5 V tPHZ tPZH ≥ VOH ≈ 1.5 V 0.5 V 1.5 V VOUT Figure 3 Figure 4 AC LOAD CIRCUIT VCC RL SWITCH POSITIONS SW1 TO OUTPUT UNDER TEST 5 kΩ CL* SW2 * Includes Jig and Probe Capacitance. Figure 5 FAST AND LS TTL DATA 5-5 SYMBOL SW1 SW2 tPZH Open Closed tPZL Closed Open tPLZ Closed Closed tPHZ Closed Closed