SN54/74LS164 SERIAL-IN PARALLEL-OUT SHIFT REGISTER The SN54 / 74LS164 is a high speed 8-Bit Serial-In Parallel-Out Shift Register. Serial data is entered through a 2-Input AND gate synchronous with the LOW to HIGH transition of the clock. The device features an asynchronous Master Reset which clears the register setting all outputs LOW independent of the clock. It utilizes the Schottky diode clamped process to achieve high speeds and is fully compatible with all Motorola TTL products. • • • • • • SERIAL-IN PARALLEL-OUT SHIFT REGISTER LOW POWER SCHOTTKY Typical Shift Frequency of 35 MHz Asynchronous Master Reset Gated Serial Data Input Fully Synchronous Data Transfers Input Clamp Diodes Limit High Speed Termination Effects ESD > 3500 Volts J SUFFIX CERAMIC CASE 632-08 14 1 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 14 Q7 13 Q6 12 Q5 11 Q4 10 MR CP 9 8 N SUFFIX PLASTIC CASE 646-06 14 1 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. D SUFFIX SOIC CASE 751A-02 14 1 A 2 B 3 Q0 4 Q1 5 Q2 6 Q3 1 7 GND ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD PIN NAMES LOADING (Note a) LOW HIGH A, B CP MR Q0 – Q7 Ceramic Plastic SOIC Data Inputs Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input Outputs (Note b) 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L. NOTES: a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges. LOGIC SYMBOL 1 2 8 A LS164 B 8-BIT SHIFT REGISTER CP MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 9 3 4 5 6 10 11 12 13 VCC = PIN 14 GND = PIN 7 FAST AND LS TTL DATA 5-1 SN54/74LS164 LOGIC DIAGRAM 1 2 A D Q D CD 8 9 Q D Q D Q D Q D Q D Q D Q B CD CD CD CD CD CD CD CP MR VCC = PIN 14 GND = PIN 7 = PIN NUMBERS Q0 Q1 3 4 Q2 Q3 Q4 Q5 Q6 Q7 5 6 10 11 12 13 FUNCTIONAL DESCRIPTION Each LOW-to-HIGH transition on the Clock (CP) input shifts data one place to the right and enters into Q0 the logical AND of the two data inputs (A•B) that existed before the rising clock edge. A LOW level on the Master Reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all Q outputs LOW. The LS164 is an edge-triggered 8-bit shift register with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs (A or B); either of these inputs can be used as an active HIGH Enable for data entry through the other input. An unused input must be tied HIGH, or both inputs connected together. MODE SELECT — TRUTH TABLE OPERATING MODE Reset (Clear) Shift INPUTS OUTPUTS MR A B Q0 Q1–Q7 L X X L L–L H H H H I I h h I h I h L L L H q0 – q6 q0 – q6 q0 – q6 q0 – q6 L (l) = LOW Voltage Levels H (h) = HIGH Voltage Levels X = Don’t Care qn = Lower case letters indicate the state of the referenced input or output one qn = set-up time prior to the LOW to HIGH clock transition. GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 74 4.5 4.75 5.0 5.0 5.5 5.25 V TA Operating Ambient Temperature Range 54 74 – 55 0 25 25 125 70 °C IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 74 4.0 8.0 mA FAST AND LS TTL DATA 5-2 SN54/74LS164 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Min Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage IIH Input HIGH Current IIL Input LOW Current IOS Short Circuit Current (Note 1) ICC Power Supply Current Typ Max 2.0 54 0.7 74 0.8 – 0.65 54 74 2.5 2.7 – 1.5 Unit Test Conditions V Guaranteed Input HIGH Voltage for All Inputs V Guaranteed Input LOW Voltage for All Inputs V VCC = MIN, IIN = – 18 mA V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table 3.5 3.5 54, 74 0.25 0.4 V IOL = 4.0 mA 74 0.35 0.5 V IOL = 8.0 mA – 20 VCC = VCC MIN, VIN = VIH or VIL per Truth Table 20 µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V – 0.4 mA VCC = MAX, VIN = 0.4 V –100 mA VCC = MAX 27 mA VCC = MAX Max Unit Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C) Limits Symbol Parameter Min Typ 25 36 fMAX Maximum Clock Frequency tPHL Propagation Delay MR to Output Q 24 36 ns tPLH tPHL Propagation Delay Clock to Output Q 17 21 27 32 ns Max Unit Test Conditions MHz VCC = 5.0 V CL = 15 pF AC SETUP REQUIREMENTS (TA = 25°C) Limits Symbol Parameter Min Typ tW CP, MR Pulse Width 20 ns ts Data Setup Time 15 ns th Data Hold Time 5.0 ns trec MR to Clock Recovery Time 20 ns FAST AND LS TTL DATA 5-3 Test Conditions VCC = 5.0 V SN54/74LS164 AC WAVEFORMS *The shaded areas indicate when the input is permitted to change for predictable output performance. I/fmax 1.3 V MR tW 1.3 V CP trec tW tPLH tPHL Q 1.3 V 1.3 V 1.3 V 1.3 V CP 1.3 V 1.3 V tPHL CONDITIONS: MR = H Q Figure 1. Clock to Output Delays and Clock Pulse Width 1.3 V Figure 2. Master Reset Pulse Width, Master Reset to Output Delay and Master Reset to Clock Recovery Time 1/fmax tW 1.3 V CP ts(H) D * 1.3 V 1.3 V th(H) 1.3 V ts(L) 1.3 V 1.3 V Q 1.3 V th(L) 1.3 V 1.3 V Figure 3. Data Setup and Hold Times FAST AND LS TTL DATA 5-4 1.3 V