SN74LV14A-EP HEX SCHMITT-TRIGGER INVERTER www.ti.com SCLS499C – MAY 2003 – REVISED JUNE 2006 FEATURES • • • • • • • • • (1) Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –55°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree (1) Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C Supports Mixed-Mode Voltage Operation on All Ports Ioff Supports Partial-Power-Down Mode Operation • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) D OR PW PACKAGE (TOP VIEW) 1A 1Y 2A 2Y 3A 3Y GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 6A 6Y 5A 5Y 4A 4Y Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. DESCRIPTION/ORDERING INFORMATION This hex Schmitt-trigger inverter is designed for 2-V to 5.5-V VCC operation. The SN74LV14A contains six independent inverters. This device performs the Boolean function Y = A. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION PACKAGE (1) TA –40°C to 105°C –55°C to 125°C (1) ORDERABLE PART NUMBER TOP-SIDE MARKING TSSOP – PW Tape and reel SN74LV14ATPWREP LV14AEP SOIC – D Tape and reel SN74LV14AMDREP LV14AEP TSSOP – PW Tape and reel SN74LV14AMPWREP LV14AEP Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each inverter) INPUT A OUTPUT Y H L L H Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2006, Texas Instruments Incorporated SN74LV14A-EP HEX SCHMITT-TRIGGER INVERTER www.ti.com SCLS499C – MAY 2003 – REVISED JUNE 2006 LOGIC DIAGRAM, EACH INVERTER (POSITIVE LOGIC) A Y Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCC MIN MAX Supply voltage range –0.5 7 V range (2) VI Input voltage –0.5 7 V VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 7 V VO Output voltage range (2) (3) –0.5 VCC + 0.5 V IIK Input clamp current VI < 0 –20 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current VO = 0 to VCC ±25 mA ±50 mA Continuous current through VCC or GND θJA Thermal impedance (4) Tstg Storage temperature range (1) (2) (3) (4) 2 UNIT D package 133.5 PW package 113 –65 150 °C/W °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. This value is limited to 5.5 V maximum. The package thermal impedance is calculated in accordance with JESD 51-7. Submit Documentation Feedback SN74LV14A-EP HEX SCHMITT-TRIGGER INVERTER www.ti.com SCLS499C – MAY 2003 – REVISED JUNE 2006 Recommended Operating Conditions VCC (1) Supply voltage VCC = 2 V VIH High-level input voltage MIN MAX 2 5.5 Low-level input voltage VI Input voltage VO Output voltage VCC = 2.3 V to 2.7 V VCC × 0.7 VCC = 3 V to 3.6 V VCC × 0.7 VCC = 4.5 V to 5.5 V VCC × 0.7 VCC = 2.3 V to 2.7 V VCC × 0.3 VCC = 3 V to 3.6 V VCC × 0.3 VCC × 0.3 5.5 0 VCC V –50 µA VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V –6 50 VCC = 2.3 V to 2.7 V (1) Operating free-air temperature µA 2 VCC = 3 V to 3.6 V 6 VCC = 4.5 V to 5.5 V TA mA –12 VCC = 2 V Low-level output current V –2 VCC = 4.5 V to 5.5 V IOL V 0 VCC = 2 V High-level output current V 0.5 VCC = 4.5 V to 5.5 V IOH V 1.5 VCC = 2 V VIL UNIT mA 12 SN74LV14AT –40 105 SN74LV14AM –55 125 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback 3 SN74LV14A-EP HEX SCHMITT-TRIGGER INVERTER www.ti.com SCLS499C – MAY 2003 – REVISED JUNE 2006 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC VT+ Positive-going threshold VT– Negative-going threshold ∆VT Hysteresis (VT+ – VT–) VOH VOL II TYP SN74LV14AM MAX MIN TYP MAX 1.75 1.78 3.3 V 2.31 2.31 5V 3.5 3.5 2.5 V 0.75 0.75 3.3 V 0.99 0.97 5V 1.5 1.5 2.5 V 0.25 1 0.25 1 3.3 V 0.33 1.32 0.33 1.37 5V 0.5 2 0.5 2 2 V to 5.5 V IOH = –2 mA 2.3 V IOH = –6 mA VCC – 0.1 VCC – 0.1 2 2 3V 2.48 2.48 4.5 V 3.8 2.3 V 0.4 0.4 IOL = 6 mA 3V 0.44 0.44 IOL = 12 mA 4.5 V 0.55 0.55 Ioff VI or VO = 0 to 5.5 V V 3.8 IOL = 2 mA VI = VCC or GND, IO = 0 V V 2 V to 5.5 V VI = VCC or GND UNIT V IOL = 50 µA ICC Ci MIN 2.5 V IOH = –50 µA IOH = –12 mA SN74LV14AT 0.1 0.1 V 0 to 5.5 V ±1 ±1 µA 5.5 V 20 20 µA 0V 5 5 µA VI = VCC or GND 3.3 V 2.3 2.3 5V 2.3 2.3 pf Switching Characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tpd A Y CL = 50 pF TA = 25°C MIN TYP MAX 9.6 16.3 MIN MAX 1 20.4 UNIT ns Switching Characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) 4 PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tpd A Y CL = 50 pF Submit Documentation Feedback TA = 25°C MIN TYP MAX 6.7 10.6 MIN MAX 1 14 UNIT ns SN74LV14A-EP HEX SCHMITT-TRIGGER INVERTER www.ti.com SCLS499C – MAY 2003 – REVISED JUNE 2006 Noise Characteristics (1) VCC = 3.3 V, CL = 50 pF, TA = 25°C PARAMETER MIN TYP MAX UNIT VOL(P) Quiet output, maximum dynamic VOL 0.2 0.8 V VOL(V) Quiet output, minimum dynamic VOL –0.1 –0.8 V VOH(V) Quiet output, minimum dynamic VOH VIH(D) High-level dynamic input voltage VIL(D) Low-level dynamic input voltage (1) 3.1 V 2.31 V 0.99 V UNIT Characteristics are for surface-mount packages only. Operating Characteristics TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS CL = 50 pF, Submit Documentation Feedback f = 10 MHz VCC TYP 3.3 V 8.8 5V 9.6 pF 5 SN74LV14A-EP HEX SCHMITT-TRIGGER INVERTER www.ti.com SCLS499C – MAY 2003 – REVISED JUNE 2006 PARAMETER MEASUREMENT INFORMATION VCC From Output Under Test Test Point RL = 1 kΩ From Output Under Test CL (see Note A) S1 Open TEST GND CL (see Note A) LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC Input 50% VCC th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC 50% VCC Input 50% VCC tPLH 50% VCC tPHL 50% VCC VOL VOH 50% VCC VOL tPLZ ≈VCC 50% VCC tPZH Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 50% VCC 0V Output Waveform 1 S1 at VCC (see Note B) tPLH 50% VCC 50% VCC tPZL tPHL VOH In-Phase Output Out-of-Phase Output 0V VCC Output Control VOL + 0.3 V VOL tPHZ 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time, with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuits and Voltage Waveforms 6 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 22-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74LV14AMDREP ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV14AMPWREP ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV14AMPWREPG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV14ATPWREP ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/03662-01XE ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/03662-02XE ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/03662-02YE ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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OTHER QUALIFIED VERSIONS OF SN74LV14A-EP : SN74LV14A • Catalog: • Automotive: SN74LV14A-Q1 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 22-Sep-2008 • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74LV14AMDREP SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74LV14AMPWREP TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LV14ATPWREP TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LV14AMDREP SOIC D 14 2500 367.0 367.0 38.0 SN74LV14AMPWREP TSSOP PW 14 2000 367.0 367.0 35.0 SN74LV14ATPWREP TSSOP PW 14 2000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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