SCLS450G − DECEMBER 1999 − REVISED APRIL 2005
D 2-V to 5.5-V VCC Operation
D Max tpd of 11 ns at 5 V
D Support Mixed-Mode Voltage Operation on
D
D
D
D Ioff Supports Partial-Power-Down Mode
D
All Ports
Schmitt-Trigger Circuitry on A, B, and CLR
Inputs for Slow Input Transition Rates
Overriding Clear Terminates Output Pulse
Glitch-Free Power-Up Reset on Outputs
D
SN54LV221A . . . FK PACKAGE
(TOP VIEW)
1
16
2
15
3
14
4
13
5
12
11
7
10
8
9
VCC
1Rext/Cext
1Cext
1Q
2Q
2CLR
2B
2A
1CLR
1Q
NC
2Q
2Cext
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
1Cext
1Q
NC
2Q
2CLR
2R ext /Cext
GND
NC
2A
2B
6
1B
1A
NC
VCC
1R ext /C ext
SN54LV221A . . . J OR W PACKAGE
SN74LV221A . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
1A
1B
1CLR
1Q
2Q
2Cext
2Rext/Cext
GND
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
NC − No internal connection
description/ordering information
ORDERING INFORMATION
TOP-SIDE
MARKING
Tube of 40
SN74LV221AD
Reel of 2500
SN74LV221ADR
SOP − NS
Reel of 2000
SN74LV221ANSR
74LV221A
SSOP − DB
Reel of 2000
SN74LV221ADBR
LV221A
Tube of 90
SN74LV221APW
Reel of 2000
SN74LV221APWR
Reel of 250
SN74LV221APWT
TVSOP − DGV
Reel of 2000
SN74LV221ADGVR
LV221A
CDIP − J
Tube of 25
SNJ54LV221AJ
SNJ54LV221AJ
CFP − W
Tube of 150
SNJ54LV221AW
SNJ54LV221AW
LCCC − FK
Tube of 55
SNJ54LV221AFK
SNJ54LV221AFK
SOIC − D
−40°C to 85°C
TSSOP − PW
−55°C
−55
C to 125
125°C
C
ORDERABLE
PART NUMBER
PACKAGE†
TA
LV221A
LV221A
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2005, Texas Instruments Incorporated
!"#$%& "!&'& &(!)$'!& "#))%& ' !( *#+,"'!& '%- )!#" "!&(!)$ !
*%"("'!& *%) % %)$ !( %.' &)#$%& '&') /'))'&0)!#"!& *)!"%&1 !% &! &%"%'),0 &",#% %&1 !( ',,
*')'$%%)POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SCLS450G − DECEMBER 1999 − REVISED APRIL 2005
description/ordering information (continued)
The ’LV221A devices are dual multivibrators designed for 2-V to 5.5-V VCC operation. Each multivibrator has
a negative-transition-triggered (A) input and a positive-transition-triggered (B) input, either of which can be used
as an inhibit input.
These edge-triggered multivibrators feature output pulse-duration control by three methods. In the first method,
the A input is low and the B input goes high. In the second method, the B input is high and the A input goes low.
In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.
The output pulse duration is programmable by selecting external resistance and capacitance values. The
external timing capacitor must be connected between Cext and Rext/Cext(positive) and an external resistor
connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistor
between Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR low.
Pulse triggering occurs at a particular voltage level and is not related directly to the transition time of the input
pulse. The A, B, and CLR inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition
rates with jitter-free triggering at the outputs.
Once triggered, the outputs are independent of further transitions of the A and B inputs and are a function of
the timing components, or the output pulses can be terminated by the overriding clear. Input pulses can be of
any duration relative to the output pulse. Output pulse duration can be varied by choosing the appropriate timing
components. Output rise and fall times are TTL compatible and independent of pulse duration. Typical triggering
and clearing sequences are illustrated in the input/output timing diagram.
The variance in output pulse duration from device to device typically is less than ±0.5% for given external timing
components. An example of this distribution for the ’LV221A is shown in Figure 8. Variations in output pulse
duration versus supply voltage and temperature are shown in Figure 5.
During power up, Q outputs are in the low state, and Q outputs are in the high state. The outputs are glitch free,
without applying a reset pulse.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
Pin assignments are identical to those of the ’AHC123A and ’AHCT123A devices, so the ’LV221A can be
substituted for those devices not using the retrigger feature.
For additional application information on multivibrators, see the application report Designing With The
SN74AHC123A and SN74AHCT123A, literature number SCLA014.
2
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SCLS450G − DECEMBER 1999 − REVISED APRIL 2005
FUNCTION TABLE
(each multivibrator)
INPUTS
CLR
OUTPUTS
A
B
Q
Q
FUNCTION
L
X
X
L
H
Reset
H
H
X
L
H
Inhibit
H
X
L
L
H
Inhibit
H
L
↑
Outputs enabled
H
↑†
↓
H
Outputs enabled
L
H
Outputs enabled
† This condition is true only if the output of the latch formed by the
NAND gate has been conditioned to the logic 1 state prior to CLR
going high. This latch is conditioned by taking either A high or B
low while CLR is inactive (high).
logic diagram, each multivibrator (positive logic)
Rext/Cext
A
Cext
B
Q
CLR
R
Q
input/output timing diagram
A
B
CLR
Rext/Cext
Q
Q
tw
tw
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• DALLAS, TEXAS 75265
tw
3
SCLS450G − DECEMBER 1999 − REVISED APRIL 2005
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Output voltage range in high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range in power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4
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SCLS450G − DECEMBER 1999 − REVISED APRIL 2005
recommended operating conditions (see Note 4)
SN54LV221A
VCC
VIH
Supply voltage
High-level input voltage
VIL
Low-level input voltage
VI
VO
Input voltage
IOH
IOL
VCC = 2 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
High-level output current
Low-level output current
Rext
External timing resistance
Cext
External timing capacitance
∆t/∆VCC
TA
Power-up ramp rate
MIN
MAX
2
5.5
1.5
MIN
MAX
2
5.5
VCC × 0.7
VCC × 0.7
VCC × 0.7
VCC × 0.7
0.5
0
0
VCC = 2 V
VCC = 2.3 V to 2.7 V
VCC × 0.3
5.5
VCC
−50
V
VCC × 0.3
VCC × 0.3
0
0
V
VCC
−50
µA
−6
−6
−12
VCC = 2 V
VCC = 2.3 V to 2.7 V
50
50
2
2
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
6
6
12
12
5k
5k
1k
1k
No restriction
No restriction
1
Operating free-air temperature
−55
−40
mA
µA
mA
Ω
pF
1
125
V
−2
−12
VCC = 2 V
VCC ≥ 3 V
V
VCC × 0.3
5.5
−2
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
V
0.5
VCC × 0.3
VCC × 0.3
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
UNIT
1.5
VCC × 0.7
VCC × 0.7
VCC = 2 V
VCC = 2.3 V to 2.7 V
Output voltage
SN74LV221A
ms/V
85
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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5
SCLS450G − DECEMBER 1999 − REVISED APRIL 2005
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV221A
PARAMETER
IOH = −50 µA
IOH = −2 mA
VOH
ICC
MIN
2 V to 5.5 V
VI = 5.5 V or GND
Quiescent
VI = VCC or GND,
Active state
(per circuit)
Ioff
3V
2.48
2.48
4.5 V
3.8
TYP
MAX
3.8
0.1
2.3 V
0.4
0.4
3V
0.44
0.44
4.5 V
0.55
0.55
2 V to 5.5 V
±2.5
±2.5
±1
±1
0 to 5.5 V
±1
±1
5.5 V
20
20
2.3 V
220
220
IO = 0
VI = VCC or GND,
Rext/Cext = 0.5 VCC
3V
280
280
4.5 V
650
650
5.5 V
975
975
0
5
3.3 V
1.9
1.9
5V
1.9
1.9
VI = VCC or GND
UNIT
V
0.1
VI or VO = 0 to 5.5 V
Ci
MIN
VCC−0.1
2
0
A, B, and CLR
SN74LV221A
MAX
2 V to 5.5 V
IOL = 6 mA
IOL = 12 mA
VI = 5.5 V or GND
TYP
VCC−0.1
2
2.3 V
IOL = 50 µA
IOL = 2 mA
Rext/Cext†
ICC
VCC
IOH = −6 mA
IOH = −12 mA
VOL
II
TEST CONDITIONS
V
µA
µA
µA
A
µA
pF
† This test is performed with the terminal in the off-state condition.
timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
tw
Pulse duration
SN54LV221A
MIN
MAX
SN74LV221A
MIN
CLR
6
6.5
6.5
A or B trigger
6
6.5
6.5
MAX
UNIT
ns
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
tw
Pulse duration
SN54LV221A
MIN
MAX
SN74LV221A
MIN
CLR
5
5
5
A or B trigger
5
5
5
MAX
UNIT
ns
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
tw
Pulse duration
MIN
MAX
SN74LV221A
MIN
CLR
5
5
5
A or B trigger
5
5
5
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6
SN54LV221A
POST OFFICE BOX 655303
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MAX
UNIT
ns
SCLS450G − DECEMBER 1999 − REVISED APRIL 2005
switching characteristics over recommended operating
VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER
tpd
tpd
FROM
(INPUT)
TO
(OUTPUT)
A or B
Q or Q
CLR
Q or Q
CLR trigger
TEST
CONDITIONS
MIN
free-air
TA = 25°C
TYP
MAX
temperature
SN54LV221A
SN74LV221A
MIN
MAX
MIN
MAX
14.6*
31.4*
1*
37*
1
37
13.2*
25*
1*
29.5*
1
29.5
Q or Q
15.2*
33.4*
1*
39*
1
39
A or B
Q or Q
16.7
36
1
42
1
42
CLR
Q or Q
15
32.8
1
34.5
1
34.5
CLR trigger
Q or Q
17.4
38
1
44
1
44
203
260
90
100
110
90
110
0.9
1
1.1
0.9
1.1
tw†
CL = 15 pF
CL = 50 pF
CL = 50 pF,
Cext = 28 pF,
Rext = 2 kΩ
CL = 50 pF,
Cext = 0.01 µF,
Rext = 10 kΩ
Q or Q
CL = 50 pF,
Cext = 0.1 µF,
Rext = 10 kΩ
∆tw‡
320
UNIT
ns
ns
320
ns
90
110
ms
0.9
1.1
ms
±1
CL = 50 pF
range,
%
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
† tw = Pulse duration at Q and Q outputs
‡ ∆tw = Output pulse-duration variation (Q and Q) between circuits in same package
switching characteristics over recommended operating
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
tpd
tpd
tw†
FROM
(INPUT)
TO
(OUTPUT)
A or B
Q or Q
CLR
Q or Q
CLR trigger
TEST
CONDITIONS
free-air
TA = 25°C
MIN
TYP
MAX
temperature
SN54LV221A
SN74LV221A
MIN
MAX
MIN
MAX
10.2*
20.6*
1*
24*
1
24
9.3*
15.8*
1*
18.5*
1
18.5
Q or Q
10.6*
22.4*
1*
26*
1
26
A or B
Q or Q
11.8
24.1
1
27.5
1
27.5
CLR
Q or Q
10.6
19.3
1
22
1
22
CLR trigger
Q or Q
12.3
25.9
1
29.5
1
29.5
186
240
90
100
110
90
110
0.9
1
1.1
0.9
1.1
Q or Q
CL = 15 pF
CL = 50 pF
CL = 50 pF,
Cext = 28 pF,
Rext = 2 kΩ
CL = 50 pF,
Cext = 0.01 µF,
Rext = 10 kΩ
CL = 50 pF,
Cext = 0.1 µF,
Rext = 10 kΩ
∆tw‡
±1
CL = 50 pF
range,
300
UNIT
ns
ns
300
ns
90
110
ms
0.9
1.1
ms
%
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
† tw = Pulse duration at Q and Q outputs
‡ ∆tw = Output pulse-duration variation (Q and Q) between circuits in same package
&(!)$'!& "!&"%)& *)!#" & % (!)$'2% !)
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7
SCLS450G − DECEMBER 1999 − REVISED APRIL 2005
switching characteristics over recommended operating
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
tpd
tpd
FROM
(INPUT)
TO
(OUTPUT)
A or B
Q or Q
CLR
Q or Q
CLR trigger
TEST
CONDITIONS
MIN
free-air
TA = 25°C
TYP
MAX
temperature
SN54LV221A
SN74LV221A
MIN
MAX
MIN
MAX
7.1*
12*
1*
14*
1
14
6.5*
9.4*
1*
11*
1
11
Q or Q
7.3*
12.9*
1*
15*
1
15
A or B
Q or Q
8.2
14
1
16
1
16
CLR
Q or Q
7.4
11.4
1
13
1
13
CLR trigger
Q or Q
8.6
14.9
1
17
1
17
171
200
90
100
110
90
110
0.9
1
1.1
0.9
1.1
tw†
CL = 15 pF
CL = 50 pF
CL = 50 pF,
Cext = 28 pF,
Rext = 2 kΩ
CL = 50 pF,
Cext = 0.01 µF,
Rext = 10 kΩ
Q or Q
CL = 50 pF,
Cext = 0.1 µF,
Rext = 10 kΩ
∆tw‡
240
UNIT
ns
ns
240
ns
90
110
ms
0.9
1.1
ms
±1
CL = 50 pF
range,
%
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
† tw = Pulse duration at Q and Q outputs
‡ ∆tw = Output pulse-duration variation (Q and Q) between circuits in same package
operating characteristics, TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
CL = 50 pF,
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8
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f = 10 MHz
VCC
3.3 V
TYP
5V
51
UNIT
50
pF
SCLS450G − DECEMBER 1999 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
Test
Point
tw
CL
(see Note A)
VCC
Inputs or
Outputs
50% VCC
50% VCC
0V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
Input A
(see Note B)
50% VCC
0V
VCC
Input B
(see Note B)
50% VCC
50% VCC
0V
50% VCC
tPLH
VOH
In-Phase
Output
50% VCC
In-Phase
Output
VOL
VOH
VOL
50% VCC
Out-of-Phase
Output
VOH
50% VCC
VOL
tPLH
tPHL
tPHL
50% VCC
tPHL
tPLH
0V
Out-of-Phase
Output
VCC
Input CLR
(see Note B)
50% VCC
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
DELAY TIMES
VOLTAGE WAVEFORMS
DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr + 3 ns, tf + 3 ns.
C. The outputs are measured one at a time, with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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9
SCLS450G − DECEMBER 1999 − REVISED APRIL 2005
APPLICATION INFORMATION
caution in use
To prevent malfunctions due to noise, connect a high-frequency capacitor between VCC and GND, and keep
the wiring between the external components and Cext and Rext/Cext terminals as short as possible.
power-down considerations
Large values of Cext can cause problems when powering down the ’LV221A because of the amount of energy
stored in the capacitor. When a system containing this device is powered down, the capacitor can discharge
from VCC through the protection diodes at pin 2 or pin 14. Current through the input protection diodes must be
limited to 30 mA; therefore, the turn-off time of the VCC power supply must not be faster than
t = VCC × Cext/30 mA. For example, if VCC = 5 V and Cext = 15 pF, the VCC supply must turn off no faster than
t = (5 V) × (15 pF)/30 mA = 2.5 ns. Usually, this is not a problem because power supplies are heavily filtered
and cannot discharge at this rate. When a more rapid decrease of VCC to zero occurs, the ’LV221A can sustain
damage. To avoid this possibility, use external clamping diodes.
output pulse duration
The output pulse duration, tw, is determined primarily by the values of the external capacitance (CT) and timing
resistance (RT). The timing components are connected as shown in Figure 2.
VCC
RT
CT
To Rext/Cext
Terminal
To Cext
Terminal
Figure 2. Timing-Component Connections
The pulse duration is given by:
tw + K
RT
CT
(1)
if CT is ≥ 1000 pF, K = 1.0
or
if CT is < 1000 pF, K can be determined from Figure 7
where:
tw
RT
CT
K
= pulse duration in ns
= external timing resistance in kΩ
= external capacitance in pF
= multiplier factor
Equation 1 and Figure 3 or 4 can be used to determine values for pulse duration, external resistance, and
external capacitance.
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCLS450G − DECEMBER 1999 − REVISED APRIL 2005
APPLICATION INFORMATION†
OUTPUT PULSE DURATION
vs
EXTERNAL TIMING CAPACITANCE
OUTPUT PULSE DURATION
vs
EXTERNAL TIMING CAPACITANCE
1.00E+07
1.00E+07
VCC = 4.5 V
TA = 25°C
1.00E+06
t w − Output Pulse Duration − ns
t w − Output Pulse Duration − ns
VCC = 3 V
TA = 25°C
RT = 1 MΩ
1.00E+05
RT = 100 kΩ
1.00E+04
RT = 10 kΩ
1.00E+03
1.00E+06
RT = 1 MΩ
1.00E+05
RT = 100 kΩ
1.00E+04
RT = 10 kΩ
1.00E+03
RT = 1 kΩ
1.00E+02
101
RT = 1 kΩ
102
103
104
105
1.00E+02
101
102
103
104
105
CT − External Timing Capacitance − pF
CT − External Timing Capacitance − pF
Figure 3
Figure 4
VARIATION IN OUTPUT PULSE DURATION
vs
TEMPERATURE
14%
Variation in Output Pulse Duration
12%
10%
8%
tw = 866 ns at:
VCC = 5 V
RT = 10 kΩ
CT = 50 pF
TA = 25°C
VCC = 2.5 V
VCC = 3 V
VCC = 3.5 V
VCC = 4 V
VCC = 5 V
6%
VCC = 6 V
VCC = 7 V
4%
2%
0%
−2%
−4%
−6%
−60
−40
−20
0
20
40
60
80
100
120
140
160
180
Temperature − °C
Figure 5
† Operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
SCLS450G − DECEMBER 1999 − REVISED APRIL 2005
APPLICATION INFORMATION†
OUTPUT PULSE DURATION CONSTANT
vs
SUPPLY VOLTAGE
EXTERNAL CAPACITANCE
vs
MULTIPLIER FACTOR
1.20
For Capacitor Values of
0.001 µF or Greater, K = 1.0
(K is Independent of R)
Output Pulse Duration Constant − K
C T − External Capacitor Value − µF
0.001
0.0001
0.00001
TA = 25°C
VCC = 5 V
1.00
1.50
2.00
2.50
3.00
3.50
4.00
RT = 10 kΩ
TA = 25°C
tw = K × C T × R T
1.15
1.10
CT = 1000 pF
1.05
CT = 0.01 µF
1.00
CT = 0.1 µF
0.95
0.90
1.5
4.50
2
2.5
3
3.5
4
4.5
5
5.5
6
VCC − Supply Voltage − V
Multiplier Factor − K
Figure 6
Figure 7
Relative Frequency of Occurrence
DISTRIBUTION OF UNITS
vs
OUTPUT PULSE DURATION
VCC = 5 V
TA = 25°C
CT = 50 pF
RT = 10 kΩ
Mean = 856 ns
Median = 856 ns
Std. Dev. = 3.5 ns
−3 Std. Dev.
99% of Data Units
+3 Std. Dev.
Median
tw − Output Pulse Duration
Figure 8
† Operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
6-May-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
SN74LV221AD
ACTIVE
SOIC
D
16
40
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74LV221ADBR
ACTIVE
SSOP
DB
16
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74LV221ADGVR
ACTIVE
TVSOP
DGV
16
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74LV221ADR
ACTIVE
SOIC
D
16
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74LV221ANSR
ACTIVE
SO
NS
16
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74LV221APW
ACTIVE
TSSOP
PW
16
90
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74LV221APWE4
ACTIVE
TSSOP
PW
16
90
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74LV221APWR
ACTIVE
TSSOP
PW
16
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74LV221APWRE4
ACTIVE
TSSOP
PW
16
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74LV221APWT
ACTIVE
TSSOP
PW
16
250
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74LV221APWTE4
ACTIVE
TSSOP
PW
16
250
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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