SCES226I − APRIL 1999 − REVISED MAY 2005 D Individual Switch Controls D Extremely Low Input Current D Ioff Supports Partial-Power-Down Mode <0.8 V at VCC = 3.3 V, TA = 25°C D Typical VOHV (Output VOH Undershoot) 16 2 15 3 14 4 5 13 12 6 11 7 10 8 9 VCC QK QJ QH QI CLR CLK QA QF QE QG QD QC QB 16 QF QL 1 2 15 3 14 4 13 5 12 6 11 10 7 8 9 SN54LV4040A . . . FK PACKAGE (TOP VIEW) QK QJ QH QI CLR CLK QE QG NC QD QC 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 QJ QH NC QI CLR QB GND NC QA CLK 1 VCC QL QF QE QG QD QC QB GND SN74LV4040A . . . RGY PACKAGE (TOP VIEW) QA SN54LV4040A . . . J OR W PACKAGE SN74LV4040A . . . D, DB, DGV, N, NS, OR PW PACKAGE (TOP VIEW) D QL D D Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) D GND D >2.3 V at VCC = 3.3 V, TA = 25°C Support Mixed-Mode Voltage Operation on All Ports High On-Off Output-Voltage Ratio Low Crosstalk Between Switches NC VCC QK D 2-V to 5.5-V VCC Operation D Typical VOLP (Output Ground Bounce) NC − No internal connection description/ordering information ORDERING INFORMATION PACKAGE† TA Tube of 25 SN74LV4040AN SN74LV4040AN QFN − RGY Reel of 1000 SN74LV4040ARGYR LW040A Tube of 40 SN74LV4040AD Reel of 2500 SN74LV4040ADR SOP − NS Reel of 2000 SN74LV4040ANSR 74LV4040A SSOP − DB Reel of 2000 SN74LV4040ADBR LW040A Tube of 90 SN74LV4040APW Reel of 2000 SN74LV4040APWR TSSOP − PW −55°C 125°C −55 C to 125 C TOP-SIDE MARKING PDIP − N SOIC − D −40°C to 85°C ORDERABLE PART NUMBER LV4040A LW040A Reel of 250 SN74LV4040APWT TVSOP − DGV Reel of 2000 SN74LV4040ADGVR LW040A CDIP − J Tube of 25 SNJ54LV4040AJ SNJ54LV4040AJ CFP − W Tube of 150 SNJ54LV4040AW SNJ54LV4040AW LCCC − FK Tube of 55 SNJ54LV4040AFK SNJ54LV4040AFK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2005, Texas Instruments Incorporated !"#$% !%&% ' %()#&% !"))$% & ( *"+,!&% &$- ')"! !%()# *$!(!&% *$) $ $)# ( $.& %)"#$% &%&) /&))&%0')"!% *)!$%1 $ % %$!$&),0 %!,"$ $%1 ( &,, *&)&#$$)POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCES226I − APRIL 1999 − REVISED MAY 2005 description/ordering information (continued) The ’LV4040A devices are 12-bit asynchronous binary counters with the outputs of all stages available externally. A high level at the clear (CLR) input asynchronously clears the counter and resets all outputs low. The count is advanced on a high-to-low transition at the clock (CLK) input. Applications include time-delay circuits, counter controls, and frequency-dividing circuits. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. FUNCTION TABLE (each buffer) INPUTS FUNCTION CLK CLR ↑ L No change ↓ L Advance to next stage X H All outputs L logic diagram (positive logic) CLR 11 R CLK 10 R T R R T T 4 QF QG T T T 7 6 5 3 QB QC QD QE R R T 13 QH R T 12 POST OFFICE BOX 655303 R T 14 QI Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, RGY, and W packages. 2 R QA T 2 R 9 R T R • DALLAS, TEXAS 75265 QJ T 15 QK 1 QL SCES226I − APRIL 1999 − REVISED MAY 2005 absolute maximum ratings over operating free-air temperature range† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W (see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W (see Note 3): N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W (see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W (see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W (see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 4. The package thermal impedance is calculated in accordance with JESD 51-5. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SCES226I − APRIL 1999 − REVISED MAY 2005 recommended operating conditions (see Note 5) VCC Supply voltage VIH VCC = 2 V VCC = 2.3 V to 2.7 V High-level input voltage VIL Low-level input voltage VI VO Input voltage VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V MAX MIN MAX 2 5.5 2 5.5 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 0 VCC = 2 V VCC = 2.3 V to 2.7 V VCC × 0.3 5.5 0 VCC −50 V VCC × 0.3 5.5 V VCC −50 µA 0 V −2 −6 −6 −12 −12 50 50 VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V 2 2 6 6 VCC = 4.5 V to 5.5 V VCC = 2.3 V to 2.7 V 12 12 200 200 100 100 20 20 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V Input transition rise or fall rate 0.5 VCC × 0.3 VCC × 0.3 −2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2 V V V 0.5 VCC × 0.3 VCC × 0.3 0 UNIT 1.5 VCC × 0.7 VCC × 0.7 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V Low-level output current ∆t/∆v MIN VCC = 2 V VCC = 2.3 V to 2.7 V High-level output current IOL SN74LV4040A 1.5 Output voltage IOH SN54LV4040A mA µA mA ns/V TA Operating free-air temperature −55 125 −40 85 °C NOTE 5: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54LV4040A PARAMETER VOH VOL TEST CONDITIONS VCC MIN TYP MIN IOH = −50 µA IOH = −2 mA 2 V to 5.5 V 2.3 V VCC − 0.1 2 VCC − 0.1 2 IOH = −6 mA IOH = −12 mA 3V 2.48 2.48 4.5 V 3.8 TYP MAX 3.8 2 V to 5.5 V 0.1 0.1 2.3 V 0.4 0.4 IOL = 6 mA IOL = 12 mA 3V 0.44 0.44 4.5 V II ICC VI = 5.5 V or GND VI = VCC or GND, Ioff Ci VI or VO = 0 to 5.5 V VI = VCC or GND IO = 0 UNIT V IOL = 50 µA IOL = 2 mA V 0.55 0.55 0 to 5.5 V ±1 ±1 µA 5.5 V 20 20 µA 0 5 5 µA 3.3 V 1.9 ' ' %()#&% !%!$)% *)"! % $ ()#&2$ ) $1% *&$ ( $2$,*#$%- &)&!$)! && &% $) *$!(!&% &)$ $1% 1&,- $.& %)"#$% )$$)2$ $ )1 !&%1$ ) !%%"$ $$ *)"! /" %!$- 4 SN74LV4040A MAX POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1.9 pF SCES226I − APRIL 1999 − REVISED MAY 2005 timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX CLK high or low tw Pulse duration tsu Setup time SN54LV4040A MIN MAX SN74LV4040A MIN 7 7 7 CLR high 6.5 6.5 6.5 CLR inactive before CLK↓ 6.5 6.5 6.5 MAX UNIT ns ns timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX tw Pulse duration tsu Setup time SN54LV4040A MIN MAX SN74LV4040A MIN CLK high or low 5 5 5 CLR high 5 5 5 CLR inactive before CLK↓ 5 5 5 MAX UNIT ns ns timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX tw Pulse duration tsu Setup time FROM (INPUT) TO (OUTPUT) fmax MIN MAX SN74LV4040A MIN CLK high or low 5 5 5 CLR high 5 5 5 CLR inactive before CLK↓ 5 5 5 switching characteristics over recommended operating VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER SN54LV4040A TA = 25°C TYP MAX free-air SN54LV4040A ns range, SN74LV4040A MIN CL = 15 pF 50* 115* 40* 40 CL = 50 pF 40 95 35 35 MAX UNIT ns temperature LOAD CAPACITANCE MIN MAX MIN MAX UNIT MHz tPLH tPHL 8.7* 19.4* 1* 23* 1 23 CLK QA CL = 15 pF 8.7* 19.4* 1* 23* 1 23 tPHL CLR Any Q CL = 15 pF 9.3* 19.9* 1* 24* 1 24 tPLH tPHL 10.5 24.1 1 28 1 28 CLK QA CL = 50 pF 10.5 24.1 1 28 1 28 tPHL CLR Any Q CL = 50 pF 11.7 24.5 1 28 1 28 ns ∆tpd Qn Qn+1 CL = 50 pF 1.7 5.9 7 ns 7 ns ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. ' ' %()#&% !%!$)% *)"! % $ ()#&2$ ) $1% *&$ ( $2$,*#$%- &)&!$)! && &% $) *$!(!&% &)$ $1% 1&,- $.& %)"#$% )$$)2$ $ )1 !&%1$ ) !%%"$ $$ *)"! /" %!$- POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SCES226I − APRIL 1999 − REVISED MAY 2005 switching characteristics over recommended operating VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax TA = 25°C TYP MAX free-air temperature SN54LV4040A SN74LV4040A LOAD CAPACITANCE MIN CL = 15 pF 75* 160* 75* 75 CL = 50 pF 55 130 50 50 MIN MAX range, MIN MAX UNIT MHz tPLH tPHL 6.1* 11.9* 1* 14* 1 14 CLK QA CL = 15 pF 6.1* 11.9* 1* 14* 1 14 tPHL CLR Any Q CL = 15 pF 7.1* 12.8* 1* 15* 1 15 tPLH tPHL 7.5 15.4 1 17.5 1 17.5 CLK QA CL = 50 pF 7.5 15.4 1 17.5 1 17.5 tPHL CLR Any Q CL = 50 pF 9 16.3 1 18.5 1 18.5 ns ∆tpd Qn Qn+1 CL = 50 pF 1.2 4.4 5 ns 5 ns ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. switching characteristics over recommended operating VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax LOAD CAPACITANCE TA = 25°C MIN TYP MAX free-air temperature SN54LV4040A MIN MAX range, SN74LV4040A MIN CL = 15 pF 150* 235* 125* 125 CL = 50 pF 95 185 80 80 MAX UNIT MHz tPLH tPHL 4.2* 7.3* 1* 8.5* 1 8.5 CLK QA CL = 15 pF 4.2* 7.3* 1* 8.5* 1 8.5 tPHL CLR Any Q CL = 15 pF 5.3* 8.6* 1* 10* 1 10 5.3 9.3 1 10.5 1 10.5 ns ns tPLH tPHL CLK QA CL = 50 pF 5.3 9.3 1 10.5 1 10.5 tPHL CLR Any Q CL = 50 pF 6.8 10.6 1 12 1 12 ns ∆tpd Qn Qn+1 CL = 50 pF 0.8 3.1 3.5 ns 3.5 ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 6) SN74LV4040A PARAMETER MIN TYP MAX UNIT VOL(P) VOL(V) Quiet output, maximum dynamic VOL 0.5 0.8 V Quiet output, minimum dynamic VOL −0.5 −0.8 V VIH(D) VIL(D) High-level dynamic input voltage 2.31 V Low-level dynamic input voltage 0.99 V VCC 3.3 V TYP UNIT 5V 13.1 NOTE 6: Characteristics are for surface-mount packages only. operating characteristics, TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS CL = 50 pF, ' ' %()#&% !%!$)% *)"! % $ ()#&2$ ) $1% *&$ ( $2$,*#$%- &)&!$)! && &% $) *$!(!&% &)$ $1% 1&,- $.& %)"#$% )$$)2$ $ )1 !&%1$ ) !%%"$ $$ *)"! /" %!$- 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 10 MHz 11.9 pF SCES226I − APRIL 1999 − REVISED MAY 2005 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point S1 VCC Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input tw tsu VCC 50% VCC Input 50% VCC 0V th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VCC 50% VCC Input 50% VCC 0V tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output VOH 50% VCC VOL Output Waveform 1 S1 at VCC (see Note B) VOH 50% VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 50% VCC 50% VCC 0V tPZL tPLZ ≈VCC 50% VCC tPZH tPLH 50% VCC VCC Output Control Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time, with one input transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74LV4040AD ACTIVE SOIC D 16 SN74LV4040ADBR ACTIVE SSOP DB SN74LV4040ADBRE4 ACTIVE SSOP SN74LV4040ADE4 ACTIVE SN74LV4040ADG4 40 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM DB 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV4040ADGVR ACTIVE TVSOP DGV 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV4040ADGVRE4 ACTIVE TVSOP DGV 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV4040ADR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV4040ADRE4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV4040ADRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV4040AN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74LV4040ANE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74LV4040ANSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV4040ANSRE4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV4040APW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV4040APWE4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV4040APWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV4040APWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV4040APWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV4040APWT ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV4040APWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV4040ARGYR ACTIVE QFN RGY 16 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR SN74LV4040ARGYRG4 ACTIVE QFN RGY 16 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°–8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Low Power Wireless www.ti.com/lpw Mailing Address: Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2006, Texas Instruments Incorporated