SCES554A − MARCH 2004 − REVISED OCTOBER 2004 D Available in the Texas Instruments D D D D D D D D D D DCT OR DCU PACKAGE (TOP VIEW) NanoStar and NanoFree Packages Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 4 ns at 3.3 V Low Power Consumption, 10-µA Max ICC ±24-mA Output Drive at 3.3 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) 1A 1B 2Y GND 1 8 2 7 3 6 4 5 VCC 1Y 2B 2A YEP OR YZP PACKAGE (BOTTOM VIEW) GND 2Y 1B 1A 4 5 3 6 2 7 1 8 2A 2B 1Y VCC description/ordering information The SN74LVC2G38 is designed for 1.65-V to 5.5-V VCC operation. This device is a dual two-input NAND buffer gate with open-drain outputs. It performs the Boolean function Y = A • B or Y = A + B in positive logic. NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package. ORDERING INFORMATION ORDERABLE PART NUMBER PACKAGE† TA NanoStar − WCSP (DSBGA) 0.23-mm Large Bump − YEP −40°C to 85°C NanoFree − WCSP (DSBGA) 0.23-mm Large Bump − YZP (Pb-free) SSOP − DCT VSSOP − DCU TOP-SIDE MARKING‡ SN74LVC2G38YEPR Reel of 3000 _ _ _D7_ SN74LVC2G38YZPR Reel of 3000 SN74LVC2G38DCTR Reel of 3000 SN74LVC2G38DCUR Reel of 250 SN74LVC2G38DCUT C38_ _ _ C38_ † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ‡ DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site. DCU: The actual top-side marking has one additional character that designates the assembly/test site. YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar and NanoFree are trademarks of Texas Instruments. Copyright 2004, Texas Instruments Incorporated ! "#$ ! %#&'" ($) (#"! " !%$""! %$ *$ $! $+! !#$! !(( ,-) (#" %"$!!. ($! $"$!!'- "'#($ $!. '' %$$!) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCES554A − MARCH 2004 − REVISED OCTOBER 2004 description/ordering information (continued) This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. FUNCTION TABLE (each gate) INPUTS A B OUTPUT Y L L H L H H H L H H H L logic diagram (positive logic) 1A 1B 2A 2B 1 7 2 5 6 3 1Y 2Y absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 3): DCT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C/W DCU package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227°C/W YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 102°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCES554A − MARCH 2004 − REVISED OCTOBER 2004 recommended operating conditions (see Note 4) Operating VCC VIH Supply voltage Data retention only VIL Low-level input voltage VI VO Input voltage MAX 1.65 5.5 V 0.65 × VCC 1.7 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V V 2 0.7 × VCC 0.35 × VCC VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 0.3 × VCC 0 5.5 V 0 VCC 4 V VCC = 1.65 V VCC = 2.3 V ∆t/∆v V 0.8 Output voltage IOL UNIT 1.5 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage MIN 8 16 Low-level output current VCC = 3 V Input transition rise or fall rate mA 24 VCC = 4.5 V VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 32 VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V 10 20 ns/V 5 TA Operating free-air temperature −40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOL = 100 mA IOL = 4 mA 0.1 0.45 2.3 V 0.3 0.4 3V 0.55 ±1 mA mA 1.65 V to 5.5 V 10 mA 3 V to 5.5 V 500 mA 0 to 5.5 V 0 VI = 5.5 V or GND, One input at VCC − 0.6 V, Ci VI = VCC or GND IO = 0 Other inputs at VCC or GND Co VO = VCC or GND † All typical values are at VCC = 3.3 V, TA = 25°C. POST OFFICE BOX 655303 V ±10 VI = 5.5 V or GND VI or VO = 5.5 V ICC ∆ICC UNIT 0.55 4.5 V IOL = 32 mA A or B inputs MAX 1.65 V IOL = 24 mA II Ioff TYP† 1.65 V to 5.5 V IOL = 8 mA IOL = 16 mA VOL MIN • DALLAS, TEXAS 75265 3.3 V 4 pF 3.3 V 4.5 pF 3 SCES554A − MARCH 2004 − REVISED OCTOBER 2004 switching characteristics over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1) PARAMETER tpd FROM (INPUT) TO (OUTPUT) A or B Y VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V MIN MAX MIN MAX MIN MAX MIN MAX 2.5 8.5 1.5 5.2 1.3 4 0.9 3 UNIT ns switching characteristics over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 2) PARAMETER tpd FROM (INPUT) TO (OUTPUT) A or B Y VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V MIN MAX MIN MAX MIN MAX MIN MAX 2.8 10 1.6 6 1.4 4.5 1 3.9 UNIT ns operating characteristics, TA = 25°C PARAMETER Cpd 4 Power dissipation capacitance TEST CONDITIONS VCC = 1.8 V TYP VCC = 2.5 V TYP f = 10 MHz 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 VCC = 3.3 V TYP 7 VCC = 5 V TYP 9 UNIT pF SCES554A − MARCH 2004 − REVISED OCTOBER 2004 PARAMETER MEASUREMENT INFORMATION (OPEN DRAIN) From Output Under Test VLOAD Open S1 RL TEST GND RL CL (see Note A) S1 tPZL (see Notes E and F) tPLZ (see Notes E and G) VLOAD VLOAD tPHZ/tPZH VLOAD LOAD CIRCUIT INPUT VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI VM tr/tf ≤ 2 ns ≤ 2 ns ≤ 2.5 ns ≤ 2.5 ns VCC VCC 3V VCC VLOAD VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC CL RL V∆ 15 pF 15 pF 15 pF 15 pF 1 MΩ 1 MΩ 1 MΩ 1MΩ 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI VM Input VM th VM Data Input VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input 0V tPHL VM VM VOL tPHL tPLZ VLOAD/2 VM VM VOL Output Waveform 2 S1 at VLOAD (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + V∆ VOL tPHZ tPZH VOH Output VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH VM VM tPZL VOH Output VI Output Control VM tPLH VI VM VLOAD/2 VLOAD/2 − V∆ ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. Since this device has open-drain outputs, tPLZ and tPZL are the same as tpd. F. tPZL is measured at VM. G. tPLZ is measured at VOL + V∆. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SCES554A − MARCH 2004 − REVISED OCTOBER 2004 PARAMETER MEASUREMENT INFORMATION (OPEN DRAIN) From Output Under Test VLOAD Open S1 RL TEST GND RL CL (see Note A) S1 tPZL (see Notes E and F) tPLZ (see Notes E and G) VLOAD VLOAD tPHZ/tPZH VLOAD LOAD CIRCUIT INPUT VCC VI 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VM tr/tf ≤ 2 ns ≤ 2 ns ≤ 2.5 ns ≤ 2.5 ns VCC VCC 3V VCC VLOAD VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC CL RL V∆ 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI VM Input VM th VM Data Input VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input 0V tPHL VM VM VOL tPHL tPLZ VLOAD/2 VM VM VOL Output Waveform 2 S1 at VLOAD (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + V∆ VOL tPHZ tPZH VOH Output VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH VM VM tPZL VOH Output VI Output Control VM tPLH VI VM VLOAD/2 VLOAD/2 − V∆ ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. Since this device has open-drain outputs, tPLZ and tPZL are the same as tpd. F. tPZL is measured at VM. G. tPLZ is measured at VOL + V∆. H. All parameters and waveforms are not applicable to all devices. Figure 2. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MPDS049B – MAY 1999 – REVISED OCTOBER 2002 DCT (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,15 0,65 8 0,13 M 5 0,15 NOM ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ 2,90 2,70 4,25 3,75 Gage Plane PIN 1 INDEX AREA 1 0,25 4 0° – 8° 3,15 2,75 0,60 0,20 1,30 MAX Seating Plane 0,10 0,10 0,00 NOTES: A. B. C. D. 4188781/C 09/02 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion Falls within JEDEC MO-187 variation DA. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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