SCES617 − OCTOBER 2004
D Qualification in Accordance With
D
D
D
D
D
D
D
D
D Inputs and Open-Drain Outputs Accept
AEC-Q100†
Qualified for Automotive Applications
Customer-Specific Configuration Control
Can Be Supported Along With
Major-Change Approval
Supports 5-V VCC Operation
Max tpd of 3.4 ns at 3.3 V
Low Power Consumption, 10-µA Max ICC
±24-mA Output Drive at 3.3 V
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
D
D
D
Voltages Up To 5.5 V
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
DBV OR DCK PACKAGE
(TOP VIEW)
1A
GND
2A
† Contact factory for details. Q100 qualification data available on
request.
1
6
2
5
3
4
1Y
VCC
2Y
description/ordering information
This dual inverter buffer/driver is designed for 1.65-V to 5.5-V VCC operation.
The output of the SN74LVC2G06 device is open drain and can be connected to other open-drain outputs to
implement active-low wired-OR or active-high wired-AND functions. The maximum sink current is 32 mA.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
−40°C to 125°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TOP-SIDE
MARKING‡
SOT (SOT-23) − DBV
Tape and reel
SN74LVC2G06QDBVRQ1
C06_
SOT (SC-70) − DCK
Tape and reel
SN74LVC2G06QDCKRQ1
CT_
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
FUNCTION TABLE
(each inverter)
INPUT
A
OUTPUT
Y
H
L
L
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2004, Texas Instruments Incorporated
!"#$%! & '("")% $& ! *(+,'$%! -$%).
"!-('%& '!!"# %! &*)''$%!& *)" %/) %)"#& ! )0$& &%"(#)%&
&%$-$"- 1$""$%2. "!-('%! *"!')&&3 -!)& !% )')&&$",2 ',(-)
%)&%3 ! $,, *$"$#)%)"&.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SCES617 − OCTOBER 2004
logic diagram (positive logic)
1A
2A
1
6
3
4
1Y
2Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165°C/W
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
2
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SCES617 − OCTOBER 2004
recommended operating conditions (see Note 4)
Operating
VCC
VIH
Supply voltage
Data retention only
VIL
Low-level input voltage
VI
VO
Input voltage
MAX
1.65
5.5
V
0.65 × VCC
1.7
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
V
2
0.7 × VCC
0.35 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
0.7
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
0.3 × VCC
0
5.5
V
0
5.5
V
VCC = 1.65 V
VCC = 2.3 V
4
8
16
Low-level output current
∆t/∆v
V
0.8
Output voltage
IOL
UNIT
1.5
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
High-level input voltage
MIN
VCC = 3 V
Input transition rise or fall rate
mA
24
VCC = 4.5 V
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
32
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
10
20
ns/V
5
TA
Operating free-air temperature
−40
125
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
IOL = 100 mA
IOL = 4 mA
0.1
0.45
2.3 V
0.3
II
Ioff
ICC
∆ICC
A inputs
3V
0.65
0 to 5.5 V
±5
mA
0
±10
mA
1.65 V to 5.5 V
10
mA
3 V to 5.5 V
500
mA
VI = 5.5 V or GND
VI or VO = 5.5 V
Ci
VI = VCC or GND
† All typical values are at VCC = 3.3 V, TA = 25°C.
POST OFFICE BOX 655303
0.65
4.5 V
TA = 125°C
IO = 0
Other inputs at VCC or GND
V
0.55
TA = −40°C to 85°C
VI = 5.5 V or GND,
One input at VCC − 0.6 V,
0.45
0.55
TA = 125°C
IOL = 32 mA
UNIT
0.4
3V
TA = −40°C to 85°C
IOL = 24 mA
MAX
1.65 V
TA = −40°C to 85°C
TA = 125°C
VOL
TYP†
1.65 V to 5.5 V
IOL = 8 mA
IOL = 16 mA
MIN
3.3 V
• DALLAS, TEXAS 75265
3.5
pF
3
SCES617 − OCTOBER 2004
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A
Y
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
1.8
7.2
1
3.9
1
3.4
1
2.9
UNIT
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
4
Power dissipation capacitance
TEST CONDITIONS
VCC = 1.8 V
TYP
VCC = 2.5 V
TYP
f = 10 MHz
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2
VCC = 3.3 V
TYP
3
VCC = 5 V
TYP
4
UNIT
pF
SCES617 − OCTOBER 2004
PARAMETER MEASUREMENT INFORMATION
(OPEN DRAIN)
RL
From Output
Under Test
VLOAD
Open
S1
TEST
GND
CL
(see Note A)
RL
S1
tPZL (see Notes E and F)
tPLZ (see Notes E and G)
VLOAD
VLOAD
tPHZ/tPZH
VLOAD
LOAD CIRCUIT
INPUT
VCC
VI
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VM
tr/tf
≤ 2 ns
≤ 2 ns
≤ 2.5 ns
≤ 2.5 ns
VCC
VCC
3V
VCC
VLOAD
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
CL
RL
V∆
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
VM
Input
VM
th
VM
Data Input
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
0V
tPHL
VOH
VM
Output
VM
VOL
tPHL
tPLH
VOH
Output
VM
VM
VOL
VI
Output
Control
VM
tPLH
VI
Output
Waveform 1
S1 at VLOAD
(see Note B)
Output
Waveform 2
S1 at VLOAD
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VM
VM
0V
tPLZ
tPZL
VLOAD/2
VM
VOL + V∆
VOL
tPHZ
tPZH
VM
VLOAD/2
VLOAD/2 − V∆
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. Since this device has open-drain outputs, tPLZ and tPZL are the same as tpd.
F. tPZL is measured at VM.
G. tPLZ is measured at VOL + V∆.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
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• DALLAS, TEXAS 75265
5
MECHANICAL DATA
MPDS114 – FEBRUARY 2002
DCK (R-PDSO-G6)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
0,65
6
0,10 M
4
1,40
1,10
1
0,13 NOM
2,40
1,80
3
Gage Plane
2,15
1,85
0,15
0°–8°
0,46
0,26
Seating Plane
1,10
0,80
0,10
0,00
0,10
4093553-3/D 01/02
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Falls within JEDEC MO-203
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