SCES470A − AUGUST 2003 − REVISED AUGUST 2003 D Available in the Texas Instruments D D D D D D D D D D DCT OR DCU PACKAGE (TOP VIEW) NanoStar and NanoFree Packages Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 5.4 ns at 3.3 V Low Power Consumption, 10-µA Max ICC ±24-mA Output Drive at 3.3 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) 1A 3Y 2A GND 1 8 2 7 3 6 4 5 VCC 1Y 3A 2Y YEP OR YZP PACKAGE (BOTTOM VIEW) GND 2A 3Y 1A 4 5 3 6 2 7 1 8 2Y 3A 1Y VCC description/ordering information This triple Schmitt-trigger buffer is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC3G17 contains three buffers, and performs the Boolean function Y = A. The device functions as three independent buffers, but because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT−) signals. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package. ORDERING INFORMATION ORDERABLE PART NUMBER PACKAGE† TA NanoStar − WCSP (DSBGA) 0.23-mm Large Bump − YEP −40°C to 85°C NanoFree − WCSP (DSBGA) 0.23-mm Large Bump − YZP (Pb-free) TOP-SIDE MARKING‡ SN74LVC3G17YEPR Tape and reel _ _ _C7_ SN74LVC3G17YZPR SSOP − DCT Tape and reel SN74LVC3G17DCTR C17_ _ _ VSSOP − DCU Tape and reel SN74LVC3G17DCUR C17_ † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ‡ DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site. DCU: The actual top-side marking has one additional character that designates the assembly/test site. YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar and NanoFree are trademarks of Texas Instruments. Copyright 2003, Texas Instruments Incorporated ! " #$%! " &$'(#! )!%* )$#!" # ! "&%##!" &% !+% !%" %," "!$%!" "!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)% !%"!/ (( &%!%"* POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCES470A − AUGUST 2003 − REVISED AUGUST 2003 FUNCTION TABLE (each inverter) INPUT A OUTPUT Y H H L L logic diagram (positive logic) 1A 2A 3A 1 7 3 5 6 2 1Y 2Y 3Y absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 3): DCT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C/W DCU package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227°C/W YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 102°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCES470A − AUGUST 2003 − REVISED AUGUST 2003 recommended operating conditions (see Note 4) Operating MIN MAX UNIT VCC VI Supply voltage 1.65 5.5 V Input voltage 0 5.5 V VO Output voltage 0 VCC −4 V VCC = 1.65 V VCC = 2.3 V IOH High-level output current VCC = 3 V VCC = 4.5 V VCC = 1.65 V VCC = 2.3 V IOL −8 −16 −32 4 8 16 Low-level output current mA −24 VCC = 3 V 24 VCC = 4.5 V 32 mA TA Operating free-air temperature −40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SCES470A − AUGUST 2003 − REVISED AUGUST 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VT+ Positive-going input threshold voltage VT− Negative-going input threshold voltage ∆VT Hysteresis (VT+ − VT−) MIN 1.65 V 0.79 1.16 2.3 V 1.11 1.56 3V 1.5 1.87 2.16 2.74 5.5 V 2.61 3.33 1.65 V 0.39 0.62 2.3 V 0.58 0.87 3V 0.84 1.14 4.5 V 1.41 1.79 5.5 V 1.87 2.29 1.65 V 0.37 0.62 2.3 V 0.48 0.77 3V 0.56 0.87 4.5 V 0.71 1.04 0.71 1.11 IOH = −100 µA IOH = −4 mA 1.65 V to 5.5 V 1.65 V VCC−0.1 1.2 IOH = −8 mA IOH = −16 mA 2.3 V 1.9 1.65 V to 5.5 V 0.1 1.65 V 0.45 IOL = 8 mA IOL = 16 mA 2.3 V 0.3 0.4 3V ICC ∆ICC VI = 5.5 V or GND, One input at VCC − 0.6 V, 0 1.65 V to 5.5 V 3 V to 5.5 V Ci VI = VCC or GND † All typical values are at VCC = 3.3 V, TA = 25°C. V 0.55 0 to 5.5 V IO = 0 Other inputs at VCC or GND V 0.55 4.5 V VI = 5.5 V or GND VI or VO = 5.5 V V 3.8 IOL = 100 µA IOL = 4 mA II Ioff V 2.3 4.5 V IOL = 24 mA IOL = 32 mA UNIT V 2.4 3V IOH = −24 mA IOH = −32 mA VOL MAX 4.5 V 5.5 V VOH TYP† VCC 3.3 V ±1 µA ±5 µA 10 µA 500 µA 4 pF switching characteristics over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX tpd A Y ‡ This information was not available at the time of publication. ‡ ‡ ‡ ‡ ‡ ‡ ‡ ‡ 4 • DALLAS, TEXAS 75265 POST OFFICE BOX 655303 ns SCES470A − AUGUST 2003 − REVISED AUGUST 2003 switching characteristics over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 2) PARAMETER tpd FROM (INPUT) TO (OUTPUT) A Y VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V MIN MAX MIN MAX MIN MAX MIN MAX 4.3 9.2 2 6.2 1.2 5.4 1 4.1 UNIT ns operating characteristics, TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS f = 10 MHz POST OFFICE BOX 655303 VCC = 1.8 V TYP VCC = 2.5 V TYP 18 • DALLAS, TEXAS 75265 19 VCC = 3.3 V TYP 19 VCC = 5 V TYP 22 UNIT pF 5 SCES470A − AUGUST 2003 − REVISED AUGUST 2003 PARAMETER MEASUREMENT INFORMATION RL From Output Under Test CL (see Note A) VLOAD Open S1 GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 15 pF 15 pF 15 pF 15 pF 1 MΩ 1 MΩ 1 MΩ 1 MΩ 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH tPHL VOH VM Output VM VOL tPHL Output Waveform 1 S1 at VLOAD (see Note B) tPLH VM VM VM 0V tPZL tPLZ VLOAD/2 VM tPZH VOH Output VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ VM VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCES470A − AUGUST 2003 − REVISED AUGUST 2003 PARAMETER MEASUREMENT INFORMATION RL From Output Under Test CL (see Note A) VLOAD Open S1 GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH tPHL VOH VM Output VM VOL tPHL Output Waveform 1 S1 at VLOAD (see Note B) tPLH VM VM VM 0V tPZL tPLZ VLOAD/2 VM tPZH VOH Output VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ VM VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 2. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 MECHANICAL DATA MPDS049B – MAY 1999 – REVISED OCTOBER 2002 DCT (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,15 0,65 8 0,13 M 5 0,15 NOM ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ 2,90 2,70 4,25 3,75 Gage Plane PIN 1 INDEX AREA 1 0,25 4 0° – 8° 3,15 2,75 0,60 0,20 1,30 MAX Seating Plane 0,10 0,10 0,00 NOTES: A. B. C. D. 4188781/C 09/02 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion Falls within JEDEC MO-187 variation DA. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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