TI SN74LVC4245A-EP

SCAS742 − DECEMBER 2003
D Controlled Baseline
D
D
D
D
D
D
D ESD Protection Exceeds JESD 22
− One Assembly/Test Site, One Fabrication
Site
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree†
Bidirectional Voltage Translator
5.5 V on A Port and 2.7 V to 3.6 V on B Port
Latch-Up Performance Exceeds 250 mA Per
JESD 17
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
PW PACKAGE
(TOP VIEW)
(5 V) VCCA
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
GND
† Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VCCB (3.3 V)
VCCB (3.3 V)
OE
B1
B2
B3
B4
B5
B6
B7
B8
GND
description/ordering information
This 8-bit (octal) noninverting bus transceiver contains two separate supply rails; B port has VCCB, which is set
at 3.3 V, and A port has VCCA, which is set at 5 V. This allows for translation from a 3.3-V to a 5-V environment,
and vice versa.
The SN74LVC4245A is designed for asynchronous communication between data buses. The device transmits
data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are
effectively isolated.
The SN74LVC4245A pinout allows the designer to switch to a normal all-3.3-V or all-5-V 20-pin ’245 device
without board re-layout. The designer uses the data paths for pins 2−11 and 14−23 of the SN74LVC4245A to
align with the conventional ’245 pinout.
ORDERING INFORMATION
TA
ORDERABLE
PART NUMBER
PACKAGE‡
TOP-SIDE
MARKING
−40°C to 85°C TSSOP − PW Reel of 2000
SN74LVC4245AIPWREP
C4245AEP
‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
OE
DIR
OPERATION
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2003, Texas Instruments Incorporated
!" # $%&" !# '%()$!" *!"&
*%$"# $ " #'&$$!"# '& "+& "&# &,!# #"%&"#
#"!*!* -!!". *%$" '$&##/ *&# " &$&##!). $)%*&
"&#"/ !)) '!!&"&#
POST OFFICE BOX 655303
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1
SCAS742 − DECEMBER 2003
logic diagram (positive logic)
2
DIR
22
OE
A1
3
21
B1
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range for VCCA = 4.5 V to 5.5 V
(unless otherwise noted)†
Supply voltage range, VCCA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Input voltage range, VI: A port (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCCA + 0.5 V
Control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6 V
Output voltage range, VO: A port (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCCA + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCCA or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. This value is limited to 6 V maximum.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
absolute maximum ratings over operating free-air temperature range for VCCB = 2.7 V to 3.6 V
(unless otherwise noted)†
Supply voltage range, VCCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Input voltage range, VI: B port (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCCB + 0.5 V
Output voltage range, VO: B port (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCCB + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCCB or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. This value is limited to 4.6 V maximum.
2
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SCAS742 − DECEMBER 2003
recommended operating conditions for VCCA = 4.5 V to 5.5 V (see Note 4)
MIN
MAX
4.5
5.5
UNIT
VCCA
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
0
VO
IOH
Output voltage
0
High-level output current
−24
mA
IOL
TA
Low-level output current
24
mA
85
°C
High-level input voltage
2
Operating free-air temperature
−40
V
V
0.8
V
VCCA
VCCA
V
V
NOTE 4: All unused inputs of the device must be held at the associated VCC or GND to ensure proper device operation. Refer to the TI application
report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
recommended operating conditions for VCCB = 2.7 V to 3.6 V (see Note 4)
MIN
MAX
2.7
3.6
VCCB
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
0
VO
Output voltage
0
IOH
High-level output current
IOL
Low-level output current
High-level input voltage
VCCB = 2.7 V to 3.6 V
VCCB = 2.7 V to 3.6 V
VCCB = 2.7 V
VCCB = 3 V
VCCB = 2.7 V
VCCB = 3 V
2
UNIT
V
V
0.8
V
VCCB
VCCB
V
V
−12
−24
mA
12
24
mA
TA
Operating free-air temperature
−40
85
°C
NOTE 4: All unused inputs of the device must be held at the associated VCC or GND to ensure proper device operation. Refer to the TI application
report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SCAS742 − DECEMBER 2003
electrical characteristics over recommended operating free-air temperature range for
VCCA = 4.5 V to 5.5 V (unless otherwise noted) (see Note 5)
PARAMETER
TEST CONDITIONS
IOH = −100 µA
A
VOH
IOH = −24 mA
VOL
IOL = 24 mA
Control inputs
A port
ICCA
∆ICCA§
VI = VCCA or GND
VO = VCCA or GND
VI = VCCA or GND,
One input at 3.4 V,
Ci
Control inputs
Cio
A port
MIN
5.5 V
5.3
4.5 V
3.7
5.5 V
4.7
TYP†
IO = 0
Other inputs at VCCA or GND
VI = VCCA or GND
VO = VCCA or GND
MAX
UNIT
4.3
V
4.5 V
IOL = 100 µA
A
II
IOZ‡
VCCA
4.5 V
0.2
5.5 V
0.2
4.5 V
0.55
5.5 V
0.55
5.5 V
±1
µA
5.5 V
±5
µA
5.5 V
80
µA
5.5 V
1.5
mA
Open
5
5V
11
V
pF
pF
† All typical values are measured at VCC = 5 V, TA = 25°C.
‡ For I/O ports, the parameter IOZ includes the input leakage current.
§ This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or the associated VCC.
NOTE 5: VCCB = 2.7 V to 3.6 V
electrical characteristics over recommended operating free-air temperature range for
VCCB = 2.7 V to 3.6 V (unless otherwise noted) (see Note 6)
PARAMETER
TEST CONDITIONS
VCCB
2.7 V to 3.6 V
IOH = −100 µA
2.7 V
VOH
IOH = −12 mA
IOH = −24 mA
IOL = 100 µA
VOL
IOZ‡
ICCB
∆ICCB§
B port
MIN
TYP¶
MAX
UNIT
VCC−0.2
2.2
3V
2.4
3V
2
V
2.7 V to 3.6 V
0.2
IOL = 12 mA
IOL = 24 mA
2.7 V
0.4
3V
0.55
VO = VCCB or GND
VI = VCCB or GND,
3.6 V
±5
µA
IO = 0
3.6 V
50
µA
One input at VCCB − 0.6 V,
Other inputs at VCCB or GND
2.7 V to 3.6 V
0.5
mA
V
Cio
B port
VO = VCCB or GND
3.3 V
11
pF
‡ For I/O ports, the parameter IOZ includes the input leakage current.
§ This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or the associated VCC.
¶ All typical values are measured at VCC = 3.3 V, TA = 25°C.
NOTE 6: VCCA = 5 V ± 0.5 V
4
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SCAS742 − DECEMBER 2003
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figures 1 and 2)
FROM
(INPUT)
TO
(OUTPUT)
tPHL
tPLH
A
B
tPHL
tPLH
B
A
tPZL
tPZH
OE
A
tPZL
tPZH
OE
B
tPLZ
tPHZ
OE
A
tPLZ
tPHZ
OE
B
PARAMETER
VCCA = 5 V ± 0.5 V,
VCCB = 2.7 V TO 3.6 V
MIN
MAX
1
6.3
1
6.7
1
6.1
1
5
1
9
1
8.1
1
8.8
1
9.8
1
7
1
5.8
1
7.7
1
7.8
UNIT
ns
ns
ns
ns
ns
ns
operating characteristics, VCCA = 4.5 V to 5.5 V, VCCB = 2.7 V to 3.6 V, TA = 25°C
PARAMETER
TEST CONDITIONS
Outputs enabled
Cpd
Power dissipation capacitance per transceiver
Outputs disabled
TYP
UNIT
39.5
CL = 0,
f = 10 MHz
5
pF
power-up considerations†
TI level-translation devices offer an opportunity for successful mixed-voltage signal design. A proper power-up
sequence always should be followed to avoid excessive supply current, bus contention, oscillations, or other
anomalies caused by improperly biased device pins. Take these precautions to guard against such power-up
problems.
1. Connect ground before any supply voltage is applied.
2. Power up the control side of the device (VCCA for all four of these devices).
3. Tie OE to VCCA with a pullup resistor so that it ramps with VCCA.
4. Depending on the direction of the data path, DIR can be high or low. If DIR high is needed (A data to B bus),
ramp it with VCCA. Otherwise, keep DIR low.
† Refer to the TI application report, Texas Instruments Voltage-Level-Translation Devices, literature number SCEA021.
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5
SCAS742 − DECEMBER 2003
PARAMETER MEASUREMENT INFORMATION
A PORT
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Input
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V
1.5 V
0V
tPLH
tPHL
VOH
Output
50% VCC
1.5 V
50% VCC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NONINVERTING OUTPUTS
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V
0V
tPZL
VCC
Input
3V
Output
Control
tPLZ
VCC
50% VCC
tPZH
50% VCC
VOL + 0.3 V
VOL
tPHZ
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
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SCAS742 − DECEMBER 2003
PARAMETER MEASUREMENT INFORMATION
B PORT
7V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7V
GND
LOAD CIRCUIT
tw
3V
Input
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V
1.5 V
0V
tPLH
tPHL
VOH
Output
1.5 V
1.5 V
1.5 V
VOL
Output
Waveform 1
S1 at 7 V
(see Note B)
tPLZ
3.5 V
1.5 V
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
tPZH
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NONINVERTING OUTPUTS
1.5 V
0V
tPZL
3V
Input
3V
Output
Control
1.5 V
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
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7
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jun-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74LVC4245AIPWREP
ACTIVE
TSSOP
PW
24
2000
TBD
Call TI
Level-1-250C-UNLIM
V62/04664-01XE
ACTIVE
TSSOP
PW
24
2000
TBD
Call TI
Level-1-250C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
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PACKAGE OPTION ADDENDUM
www.ti.com
23-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74LVC4245AIPWREP
ACTIVE
TSSOP
PW
24
2000
TBD
CU NIPDAU
Level-1-250C-UNLIM
V62/04664-01XE
ACTIVE
TSSOP
PW
24
2000
TBD
CU NIPDAU
Level-1-250C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74LVC4245AIPWREP
ACTIVE
TSSOP
PW
24
2000
TBD
Call TI
Level-1-250C-UNLIM
V62/04664-01XE
ACTIVE
TSSOP
PW
24
2000
TBD
Call TI
Level-1-250C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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