SN74LVCH16374A 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCAS757A – DECEMBER 2003 – REVISED OCTOBER 2005 FEATURES • • • • • • • • • • • DGG, DGV, OR DL PACKAGE (TOP VIEW) Member of the Texas Instruments Widebus™ Family Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 4.5 ns at 3.3 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C Ioff Supports Partial-Power-Down Mode Operation Supports Mixed-Mode Signal Operation on All Ports (5-V Input and Output Voltages With 3.3-V VCC) Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 1000-V Charged-Device Model (C101) 1OE 1Q1 1Q2 GND 1Q3 1Q4 VCC 1Q5 1Q6 GND 1Q7 1Q8 2Q1 2Q2 GND 2Q3 2Q4 VCC 2Q5 2Q6 GND 2Q7 2Q8 2OE DESCRIPTION/ORDERING INFORMATION This 16-bit edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation. 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1CLK 1D1 1D2 GND 1D3 1D4 VCC 1D5 1D6 GND 1D7 1D8 2D1 2D2 GND 2D3 2D4 VCC 2D5 2D6 GND 2D7 2D8 2CLK ORDERING INFORMATION PACKAGE (1) TA FBGA – GRD FBGA – ZRD (Pb-free) Tape and reel Tube SSOP – DL Tape and reel –40°C to 85°C TSSOP – DGG Tape and reel TVSOP – DGV Tape and reel VFBGA – GQL VFBGA – ZQL (Pb-free) (1) Tape and reel ORDERABLE PART NUMBER SN74LVCH16374AGRDR SN74LVCH16374AZRDR TOP-SIDE MARKING LDH374A SN74LVCH16374ADL 74LVCH16374ADLG4 SN74LVCH16374ADL LVCH16374A 74LVCH16374ADLRG4 SN74LVCH16374ADGGR 74LVCH16374ADGGRG4 SN74LVCH16374ADGVR 74LVCH16374ADGVRE4 SN74LVCH16374AGQLR SN74LVCH16374AZQLR LVCH16374A LDH374A LDH374A Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2005, Texas Instruments Incorporated SN74LVCH16374A 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCAS757A – DECEMBER 2003 – REVISED OCTOBER 2005 DESCRIPTION/ORDERING INFORMATION (CONTINUED) A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. The SN74LVCH16374A is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. GQL OR ZQL PACKAGE (TOP VIEW) TERMINAL ASSIGNMENTS (1) (56-Ball GQL/ZQL Package) 1 2 3 4 5 6 1 A B C D E F G H J K xxx 3 4 5 5 6 1OE NC NC NC NC 1CLK 1Q2 1Q1 GND GND 1D1 1D2 C 1Q4 1Q3 VCC VCC 1D3 1D4 D 1Q6 1Q5 GND GND 1D5 1D6 E 1Q8 1Q7 1D7 1D8 F 2Q1 2Q2 2D2 2D1 G 2Q3 2Q4 GND 2D4 2D3 H 2Q5 2Q6 VCC VCC 2D6 2D5 J 2Q7 2Q8 GND GND 2D8 2D7 K 2OE NC NC NC NC 2CLK GND NC – No internal connection TERMINAL ASSIGNMENTS (1) (54-Ball GRD/ZRD Package) 6 1 2 3 4 5 6 A 1Q1 NC 1OE 1CLK NC 1D1 A B 1Q3 1Q2 NC NC 1D2 1D3 B C 1Q5 1Q4 VCC VCC 1D4 1D5 C D 1Q7 1Q6 GND GND 1D6 1D7 D E 2Q1 1Q8 GND GND 1D8 2D1 E F 2Q3 2Q2 GND GND 2D2 2D3 F G 2Q5 2Q4 VCC VCC 2D4 2D5 G H 2Q7 2Q6 NC NC 2D6 2D7 J 2Q8 NC 2OE 2CLK NC 2D8 H J (1) 2 4 B GRD OR ZRD PACKAGE (TOP VIEW) 2 3 A (1) 1 2 NC – No internal connection SN74LVCH16374A 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCAS757A – DECEMBER 2003 – REVISED OCTOBER 2005 FUNCTION TABLE (EACH FLIP-FLOP) INPUTS OE CLK D OUTPUT Q L ↑ H H L ↑ L L L H or L X Q0 H X X Z LOGIC DIAGRAM (POSITIVE LOGIC) 1OE 1CLK 1D1 1 2OE 48 2CLK C1 47 2 1D 1Q1 24 25 C1 2D1 36 To Seven Other Channels 13 1D 2Q1 To Seven Other Channels Pin numbers shown are for the DGG, DGV, and DL packages. Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V –0.5 6.5 V –0.5 VCC + 0.5 state (2) UNIT VO Voltage range applied to any output in the high-impedance or power-off VO Voltage range applied to any output in the high or low state (2) (3) IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA Continuous current through each VCC or GND θJA Package thermal impedance (4) DGG package 70 DGV package 58 DL package 63 GQL/ZQL package 42 GRD/ZRD package Tstg (1) (2) (3) (4) Storage temperature range V °C/W 36 –65 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7. 3 SN74LVCH16374A 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCAS757A – DECEMBER 2003 – REVISED OCTOBER 2005 Recommended Operating Conditions (1) VCC Supply voltage Operating Data retention only VCC = 1.65 V to 1.95 V VIH High-level input voltage MIN MAX 1.65 3.6 1.5 Low-level input voltage VI VCC = 2.3 V to 2.7 V 1.7 VCC = 2.7 V to 3.6 V 2 VO Output voltage IOH High-level output current 0.35 × VCC 0.7 VCC = 2.7 V to 3.6 V 0.8 0 5.5 High or low state 0 VCC High-impedance state 0 5.5 VCC = 1.65 V –4 VCC = 2.3 V –8 VCC = 2.7 V –12 VCC = 3 V –24 VCC = 1.65 V IOL Low-level output current ∆t/∆v Input transition rise or fall rate TA Operating free-air temperature (1) 4 V VCC = 2.3 V to 2.7 V Input voltage V 0.65 × VCC VCC = 1.65 V to 1.95 V VIL UNIT V V V mA 4 VCC = 2.3 V 8 VCC = 2.7 V 12 VCC = 3 V 24 –40 mA 10 ns/V 85 °C All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. SN74LVCH16374A 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCAS757A – DECEMBER 2003 – REVISED OCTOBER 2005 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = –100 µA VOH 1.65 V to 3.6 V 1.2 IOH = –8 mA 2.3 V 1.7 2.7 V 2.2 3V 2.4 IOH = –24 mA 3V 2.2 IOL = 100 µA 1.65 V to 3.6 V 0.2 IOL = 4 mA 1.65 V 0.45 IOL = 8 mA 2.3 V 0.7 IOL = 12 mA 2.7 V 0.4 3V 0.55 VI = 0 to 5.5 V ±5 V µA (2) 1.65 V VI = 1.07 V VI = 0.7 V (2) 45 2.3 V VI = 1.7 V VI = 0.8 V µA –45 75 3V VI = 2 V –75 3.6 V ±500 Ioff VI or VO = 5.5 V 0 ±10 µA IOZ VO = 0 to 5.5 V 3.6 V ±10 µA VI = 0 to 3.6 ICC ∆ICC (1) (2) (3) (4) UNIT V 3.6 V VI = 0.58 V II(hold) MAX VCC – 0.2 1.65 V IOL = 24 mA II TYP (1) IOH = –4 mA IOH = –12 mA VOL MIN V (3) VI = VCC or GND 3.6 V ≤ VI ≤ 5.5 V (4) One input at VCC – 0.6 V, IO = 0 20 3.6 V Other inputs at VCC or GND 20 2.7 V to 3.6 V 500 µA µA Ci VI = VCC or GND 3.3 V 5 pF Co VO = VCC or GND 3.3 V 6.5 pF All typical values are at VCC = 3.3 V, TA = 25°C. This information was not available at the time of publication. This is the bus-hold maximum dynamic current required to switch the input from one state to another. This applies in the disabled state only. Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 1.8 V ± 0.15 V MIN fclock MAX VCC = 2.5 V ± 0.2 V MIN (1) Clock frequency MAX VCC = 2.7 V MIN (1) MIN 150 UNIT MAX 150 MHz tw Pulse duration, CLK high or low (1) 3.3 3.3 ns tsu Setup time, data before CLK↑ (1) (1) 1.9 1.9 ns th Hold time, data after CLK↑ (1) (1) 1.1 1.1 ns (1) (1) MAX VCC = 3.3 V ± 0.3 V This information was not available at the time of publication. 5 SN74LVCH16374A 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCAS757A – DECEMBER 2003 – REVISED OCTOBER 2005 Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 1.8 V ± 0.15 V MIN VCC = 2.5 V ± 0.2 V MAX MIN MAX MIN MAX VCC = 3.3 V ± 0.3 V MIN (1) tpd CLK Q (1) (1) (1) (1) 4.9 1.5 4.5 ns ten OE Q (1) (1) (1) (1) 5.3 1.5 4.6 ns Q (1) (1) (1) (1) 6.1 1.5 5.5 ns 1 ns OE 150 150 MHz tsk(o) (1) UNIT MAX fmax tdis (1) VCC = 2.7 V This information was not available at the time of publication. Operating Characteristics TA = 25°C TEST CONDITIONS PARAMETER Cpd (1) 6 Power dissipation capacitance per flip-flop Outputs enabled Outputs disabled This information was not available at the time of publication. f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V TYP TYP TYP (1) (1) 58 (1) (1) 24 UNIT pF SN74LVCH16374A 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCAS757A – DECEMBER 2003 – REVISED OCTOBER 2005 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V 1.5 V 2 × VCC 2 × VCC 6V 6V 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VM VM VOL tPHL VM VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPLZ VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VOH Output VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ VM VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 7 PACKAGE OPTION ADDENDUM www.ti.com 24-May-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 74LVCH16374ADGGRG4 ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74LVCH16374ADGVRE4 ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74LVCH16374ADGVRG4 ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74LVCH16374ADLG4 ACTIVE SSOP DL 48 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74LVCH16374ADLRG4 ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVCH16374ADGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVCH16374ADGVR ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVCH16374ADL ACTIVE SSOP DL 48 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVCH16374ADLR ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVCH16374AGQLR NRND BGA MI CROSTA R JUNI OR GQL 56 1000 SNPB Level-1-240C-UNLIM SN74LVCH16374AZQLR ACTIVE BGA MI CROSTA R JUNI OR ZQL 56 1000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM 25 25 TBD Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 24-May-2007 incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 19-May-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com Device 19-May-2007 Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74LVCH16374ADGGR DGG 48 MLA 330 24 8.6 15.8 1.8 12 24 Q1 SN74LVCH16374ADGVR DGV 48 MLA 330 24 6.8 10.1 1.6 12 24 Q1 SN74LVCH16374ADLR DL 48 MLA 330 32 11.35 16.2 3.1 16 32 Q1 SN74LVCH16374AGQLR GQL 56 HIJ 330 16 4.8 7.3 1.45 8 16 Q1 SN74LVCH16374AZQLR ZQL 56 HIJ 330 16 4.8 7.3 1.45 8 16 Q1 TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) SN74LVCH16374ADGGR DGG 48 MLA 333.2 333.2 31.75 SN74LVCH16374ADGVR DGV 48 MLA 333.2 333.2 31.75 SN74LVCH16374ADLR DL 48 MLA 336.6 342.9 41.3 SN74LVCH16374AGQLR GQL 56 HIJ 346.0 346.0 33.0 SN74LVCH16374AZQLR ZQL 56 HIJ 346.0 346.0 33.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 19-May-2007 Pack Materials-Page 3 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°–8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.620 (15,75) 0.720 (18,29) DIM 4040048 / E 12/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MO-118 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. 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