TI SN74LVT543

SN54LVT543, SN74LVT543
3.3-V ABT OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS137D – MAY 1992 – REVISED JULY 1995
D
D
D
D
D
D
description
These octal transceivers are designed specifically
for low-voltage (3.3-V) VCC operation, but with the
capability to provide a TTL interface to a 5-V
system environment.
The ’LVT543 contain two sets of D-type latches for
temporary storage of data flowing in either
direction. Separate latch-enable (LEAB or LEBA)
and output-enable (OEAB or OEBA) inputs are
provided for each register to permit independent
control in either direction of data flow.
LEBA
OEBA
A1
A2
A3
A4
A5
A6
A7
A8
CEAB
GND
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VCC
CEBA
B1
B2
B3
B4
B5
B6
B7
B8
LEAB
OEAB
SN54LVT543 . . . FK PACKAGE
(TOP VIEW)
5
3 2 1 28 27 26
25
6
24
7
23
8
22
9
21
10
20
4
A2
A3
A4
NC
A5
A6
A7
CEBA
B1
D
SN54LVT543 . . . JT PACKAGE
SN74LVT543 . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
A1
OEBA
LEBA
NC
VCC
D
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static Power
Dissipation
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V VCC )
Support Unregulated Battery Operation
Down to 2.7 V
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
Bus-Hold Data Inputs Eliminate the Need
for External Pullup Resistors
Support Live Insertion
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK), and
Ceramic (JT) DIPs
19
11
12 13 14 15 16 17 18
B2
B3
B4
NC
B5
B6
B7
A8
CEAB
GND
NC
OEAB
LEAB
B8
D
NC – No internal connection
The A-to-B enable (CEAB) input must be low in order to enter data from A or to output data from B. If CEAB
is low and LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts
the A latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect
the data present at the output of the A latches. Data flow from B to A is similar but requires using the CEBA,
LEBA, and OEBA inputs.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1995, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54LVT543, SN74LVT543
3.3-V ABT OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS137D – MAY 1992 – REVISED JULY 1995
description (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74LVT543 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54LVT543 is characterized for operation over the full military temperature range of – 55°C to 125°C. The
SN74LVT543 is characterized for operation from – 40°C to 85°C.
FUNCTION TABLE†
INPUTS
CEAB
LEAB
OEAB
A
OUTPUT
B
H
X
X
X
Z
X
X
H
X
Z
L
H
L
X
L
L
L
L
B0‡
L
L
L
L
H
H
† A-to-B data flow is shown; B-to-A flow control is the
same except that it uses CEBA, LEBA, and OEBA.
‡ Output level before the indicated steady-state input
conditions were established
logic symbol§
2
1EN3
OEBA
23
CEBA
1
1C5
LEBA
13
OEAB
11
CEAB
14
LEAB
A1
A2
A3
A4
A5
A6
A7
A8
G1
2EN4
G2
2C6
3
4
3
1
5D
6D
1
4
21
5
20
6
19
7
18
8
17
9
16
10
15
§ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DB, DW, JT, and PW packages.
2
22
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
B1
B2
B3
B4
B5
B6
B7
B8
SN54LVT543, SN74LVT543
3.3-V ABT OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS137D – MAY 1992 – REVISED JULY 1995
logic diagram (positive logic)
OEBA
CEBA
LEBA
OEAB
CEAB
LEAB
A1
2
23
1
13
11
14
C1
3
1D
22
B1
C1
1D
To Seven Other Channels
Pin numbers shown are for the DB, DW, JT, and PW packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Voltage range applied to any output in the high state or power-off state, VO (see Note 1) . . . . – 0.5 V to 7 V
Current into any output in the low state, IO: SN54LVT543 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74LVT543 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Current into any output in the high state, IO (see Note 2): SN54LVT543 . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA
SN74LVT543 . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 3): DB package . . . . . . . . . . . . . . . . . . . 0.65 W
DW package . . . . . . . . . . . . . . . . . . . 1.7 W
PW package . . . . . . . . . . . . . . . . . . . 0.7 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology
Data Book, literature number SCBD002B.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54LVT543, SN74LVT543
3.3-V ABT OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS137D – MAY 1992 – REVISED JULY 1995
recommended operating conditions (see Note 4)
SN54LVT543
SN74LVT543
MIN
MAX
MIN
MAX
2.7
3.6
2.7
3.6
UNIT
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
0.8
0.8
Input voltage
5.5
5.5
V
IOH
IOL
High-level output current
– 24
– 32
mA
48
64
mA
∆t /∆v
Input transition rise or fall rate
10
10
ns / V
85
°C
High-level input voltage
2
Low-level output current
Outputs enabled
TA
Operating free-air temperature
NOTE 4: Unused control inputs must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
– 55
2
125
– 40
V
V
V
SN54LVT543, SN74LVT543
3.3-V ABT OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS137D – MAY 1992 – REVISED JULY 1995
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
VCC = 2.7 V,
VCC = MIN to MAX‡,
II = –18 mA
IOH = –100 µA
VCC = 2.7 V,
IOH = – 8 mA
IOH = – 24 mA
VCC = 3 V
VCC = 2
2.7
7V
VOL
VCC = 3 V
VCC = 3.6 V,
VCC = 0 or MAX‡,
II
VCC = 3.6 V
Ioff
VCC = 0,
II(hold)
I(h ld)
VCC = 3 V
IOZH
IOZL
VCC = 3.6 V,
VCC = 3.6 V,
ICC
SN54LVT543
TYP†
MAX
TEST CONDITIONS
VCC = 3.6 V,
VI = VCC or GND
MIN
–1.2
VCC – 0.2
2.4
–1.2
VCC – 0.2
2.4
IOH = – 32 mA
IOL = 100 µA
0.2
IOL = 24 mA
IOL = 16 mA
0.5
0.5
0.4
0.4
IOL = 32 mA
IOL = 48 mA
0.5
0.5
VI = 5.5 V
VI = 5.5 V
VI = VCC
VI = 0
VI or VO = 0 to 4.5 V
VI = 0.8 V
VI = 2 V
VO = 3 V
V
0.55
0.55
Control
inputs
A or B ports§
±1
±1
10
10
20
20
5
5
–10
–10
± 100
A or B ports
75
75
–75
–75
–1
µA
–1
µA
0.13
0.19
0.13
0.19
Outputs low
8.8
12
8.8
12
0.13
0.19
0.13
0.19
VCC = 3 V to 3.6 V,
One input at VCC – 0.6 V,
Other inputs at VCC or GND
Ci
VI = 3 V or 0
VO = 3 V or 0
µA
1
Outputs high
Outputs
disabled
µA
µA
1
VO = 0.5 V
IO = 0,
V
2
0.2
IOL = 64 mA
VI = VCC or GND
UNIT
V
2
∆ICC¶
Cio
SN74LVT543
TYP†
MAX
MIN
0.2
0.2
mA
mA
4.5
4.5
pF
11
11
pF
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
§ Unused terminals at VCC or GND
¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SN54LVT543, SN74LVT543
3.3-V ABT OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS137D – MAY 1992 – REVISED JULY 1995
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
SN54LVT543
VCC = 3.3 V
± 0.3 V
MIN
tw
tsu
th
Pulse duration,
LEAB or LEBA low
A or B before LEAB or
LEBA↑
Data high
A or B before CEAB or
CEBA↑
Data high
Setup time
Hold time
MAX
3.3
Data low
Data low
SN74LVT543
VCC = 2.7 V
MIN
MAX
3.3
VCC = 3.3 V
± 0.3 V
MIN
VCC = 2.7 V
MAX
MIN
3.3
MAX
3.3
0
0
0
0
0.8
1.1
0.8
1.1
0
0
0
0
0.9
1.2
0.9
1.2
A or B after LEAB or LEBA↑
1.7
1.7
1.7
1.7
A or B after CEAB or CEBA↑
1.8
1.8
1.8
1.8
UNIT
ns
ns
ns
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
SN54LVT543
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A or B
B or A
tPLH
tPHL
LE
A or B
tPZH
tPZL
OE
A or B
tPHZ
tPLZ
OE
A or B
tPZH
tPZL
CE
A or B
tPHZ
tPLZ
CE
A or B
VCC = 3.3 V
± 0.3 V
SN74LVT543
VCC = 2.7 V
MIN
MAX
VCC = 2.7 V
MIN
MAX
1
4.9
5.7
1
2.9
4.7
5.5
1
4.8
6
1
3.3
4.6
5.8
1
6.1
7.5
1
4
5.9
7.3
1
5.9
7.5
1
4.1
5.7
7.3
1
6
7.8
1
4.1
5.8
7.6
1.1
6.6
8.4
1.1
4.5
6.4
8.2
2.4
6.7
7.3
2.4
4.8
6.5
7.1
2
6
6.1
2
4
5.8
5.9
MIN
1
6.2
7.8
1
4.2
6
7.6
6.9
8.5
1.4
4.7
6.7
8.3
2.3
6.6
7.3
2.3
4.7
6.4
7.1
2
5.6
5.8
2
3.8
5.4
5.6
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
MAX
1.4
† All typical values are at VCC = 3.3 V, TA = 25°C.
6
VCC = 3.3 V
± 0.3 V
MIN TYP†
MAX
ns
ns
ns
ns
ns
ns
SN54LVT543, SN74LVT543
3.3-V ABT OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS137D – MAY 1992 – REVISED JULY 1995
PARAMETER MEASUREMENT INFORMATION
6V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
2.7 V
LOAD CIRCUIT FOR OUTPUTS
1.5 V
Timing Input
0V
tw
tsu
2.7 V
Input
1.5 V
th
2.7 V
1.5 V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
Input
1.5 V
0V
1.5 V
1.5 V
VOL
tPLH
tPHL
VOH
Output
1.5 V
1.5 V
VOL
1.5 V
0V
tPLZ
Output
Waveform 1
S1 at 6 V
(see Note B)
VOH
Output
1.5 V
tPZL
tPHL
tPLH
2.7 V
Output
Control
1.5 V
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
tPZH
3V
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH – 0.3 V
VOH
[0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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7
PACKAGE OPTION ADDENDUM
www.ti.com
21-Aug-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
SN74LVT543DBLE
OBSOLETE
SSOP
DB
24
SN74LVT543DW
NRND
SOIC
DW
24
SN74LVT543DWR
NRND
SOIC
DW
24
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
TBD
Call TI
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
25
Call TI
SN74LVT543NSR
OBSOLETE
SO
NS
24
TBD
Call TI
Call TI
SN74LVT543PWLE
OBSOLETE
TSSOP
PW
24
TBD
Call TI
Call TI
SN74LVT543PWR
NRND
TSSOP
PW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jul-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
Device
16-Jul-2007
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74LVT543DWR
DW
24
TAI
330
24
10.75
15.7
2.7
12
24
Q1
SN74LVT543PWR
PW
24
MLA
330
16
6.95
8.3
1.6
8
16
Q1
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
SN74LVT543DWR
DW
SN74LVT543PWR
PW
24
TAI
346.0
346.0
41.0
24
MLA
346.0
346.0
33.0
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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