TI SN74LVTH32245GKER

SCBS750A − OCTOBER 2000 − REVISED SEPTEMBER 2003
D Member of the Texas Instruments
D
D
D
D
D Supports Mixed-Mode Signal Operation
Widebus+  Family
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
Ioff and Power-Up 3-State Support Hot
Insertion
Supports Unregulated Battery Operation
Down to 2.7 V
GKE OR ZKE PACKAGE
(TOP VIEW)
1
2
3
4
5
(5-V Input and Output Voltages With
3.3-V VCC)
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
D
D
D
terminal assignments
6
1
2
3
4
5
6
A
A
1B2
1B1
1DIR
1OE
1A1
1A2
B
B
1B4
1B3
GND
GND
1A3
1A4
C
C
1B6
1B5
1B7
1VCC
GND
1A6
1B8
1VCC
GND
1A5
D
1A7
1A8
E
2B2
2B1
GND
GND
2A1
2A2
D
E
F
G
H
J
F
2B4
2B3
2B5
1VCC
GND
2A4
2B6
1VCC
GND
2A3
G
2A5
2A6
H
2B7
2B8
2DIR
2OE
2A8
2A7
J
3B2
3B1
3DIR
3OE
3A1
3A2
K
3B4
3B3
GND
GND
3A3
3A4
K
L
3B6
3B5
3B8
3B7
2VCC
GND
3A6
M
2VCC
GND
3A5
L
3A7
3A8
M
N
4B2
4B1
GND
GND
4A1
4A2
N
P
4B4
4B3
P
4B5
2VCC
GND
4A4
4B6
2VCC
GND
4A3
R
4A5
4A6
R
T
4B7
4B8
4DIR
4OE
4A8
4A7
T
description/ordering information
ORDERING INFORMATION
ORDERABLE
PART NUMBER
PACKAGE†
TA
LFBGA − GKE
−40°C to 85°C
LFBGA − ZKE (Pb-free)
TOP-SIDE
MARKING
SN74LVTH32245GKER
Tape and reel
SN74LVTH32245ZKER
HV245
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ is a trademark of Texas Instruments.
Copyright  2003, Texas Instruments Incorporated
! " #$%! " &$'(#! )!%
)$#!" # ! "&%##!" &% !*% !%" %+" "!$%!"
"!)) ,!- )$#! &#%"". )%" ! %#%""(- #($)%
!%"!. (( &%!%"
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SCBS750A − OCTOBER 2000 − REVISED SEPTEMBER 2003
description/ordering information (continued)
The SN74LVTH32245 is a 32-bit noninverting 3-state transceiver designed for low-voltage (3.3-V) VCC
operation, but with the capability to provide a TTL interface to a 5-V system environment.
This device can be used as four 8-bit transceivers, two 16-bit transceivers, or one 32-bit transceiver. The device
allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level
at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the devices so that the
buses are effectively isolated.
When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
FUNCTION TABLE
(each 8-bit transceiver)
INPUTS
2
OPERATION
OE
DIR
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCBS750A − OCTOBER 2000 − REVISED SEPTEMBER 2003
logic diagram (positive logic)
1DIR
A3
2DIR
A4
1A1
H4
1OE
A5
2A1
A2
H3
E5
E2
1B1
To Seven Other Channels
3DIR
2B1
To Seven Other Channels
J3
4DIR
J4
3A1
2OE
T4
3OE
J5
4A1
J2
T3
4OE
N5
N2
3B1
To Seven Other Channels
4B1
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high-impedance
or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Current into any output in the high state, IO (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Package thermal impedance, θJA (see Note 3): GKE/ZKE package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
POST OFFICE BOX 655303
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3
SCBS750A − OCTOBER 2000 − REVISED SEPTEMBER 2003
recommended operating conditions (see Note 4)
MIN
MAX
2.7
3.6
UNIT
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
5.5
V
IOH
IOL
High-level output current
−32
mA
∆t/∆v
Input transition rise or fall rate
∆t/∆VCC
TA
Power-up ramp rate
200
Operating free-air temperature
−40
High-level input voltage
2
V
0.8
Low-level output current
Outputs enabled
V
V
64
mA
10
ns/V
µs/V
85
°C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCBS750A − OCTOBER 2000 − REVISED SEPTEMBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
UNIT
−1.2
V
VIK
VCC = 2.7 V,
VCC = 2.7 V to 3.6 V,
II = −18 mA
IOH = −100 µA
VOH
VCC = 2.7 V,
VCC = 3 V,
IOH = −8 mA
IOH = −32 mA
IOL = 100 µA
IOL = 24 mA
0.2
VCC = 2.7 V
IOL = 16 mA
IOL = 32 mA
0.4
VOL
VCC = 3 V
Control inputs
Ioff
II(hold)
A or B ports
V
2
0.5
VCC = 3.6 V,
VCC = 0 or 3.6 V,
0.55
±1
VI = 5.5 V
VI = 5.5 V
10
VCC = 3.6 V
VI = VCC
VI = 0
1
VCC = 0,
VI or VO = 0 to 4.5 V
VI = 0.8 V
VCC = 3 V
20
µA
−5
±100
µA
75
VI = 2 V
VI = 0 to 3.6 V
VCC = 3.6 V,§
V
0.5
IOL = 64 mA
VI = VCC or GND
II
A or B ports‡
VCC−0.2
2.4
µA
−75
±500
IOZPU
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE = don’t care
± 100
µA
IOZPD
VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE = don’t care
±100
µA
ICC
VCC = 3.6 V, IO = 0,
VI = VCC or GND
Outputs high
10
Outputs disabled
∆ICC¶
VCC = 3 V to 3.6 V, One input at VCC − 0.6 V,
Other inputs at VCC or GND
Ci
VI = 3 V or 0
VO = 3 V or 0
Cio
0.38
Outputs low
mA
0.38
0.2
4
mA
pF
10
pF
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ Unused pins at VCC or GND
§ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
¶ This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A or B
B or A
tPZH
tPZL
OE
A or B
tPHZ
tPLZ
OE
A or B
PARAMETER
tsk(o)
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
MIN
TYP†
MAX
1.5
2.3
3.3
3.7
1.3
2.1
3.3
3.5
1.5
2.8
4.5
5.3
1.6
2.9
4.6
5.2
2.3
3.7
5.1
5.5
2.2
3.5
5.1
5.4
0.5
MIN
UNIT
MAX
ns
ns
ns
ns
† All typical values are at VCC = 3.3 V, TA = 25°C.
POST OFFICE BOX 655303
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5
SCBS750A − OCTOBER 2000 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
6V
500 Ω
From Output
Under Test
S1
GND
CL = 50 pF
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
Open
500 Ω
2.7 V
LOAD CIRCUIT
1.5 V
Timing Input
0V
tw
tsu
2.7 V
1.5 V
Input
1.5 V
th
2.7 V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
Input
1.5 V
1.5 V
0V
tPHL
tPLH
VOH
1.5 V
Output
1.5 V
VOL
VOH
Output
1.5 V
Output
Waveform 1
S1 at 6 V
(see Note B)
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
0V
tPLZ
tPZL
3V
1.5 V
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
tPZH
tPLH
tPHL
2.7 V
Output
Control
1.5 V
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74LVTH32245GKER
ACTIVE
LFBGA
GKE
96
1000
SN74LVTH32245ZKER
ACTIVE
LFBGA
ZKE
96
1000 Green (RoHS &
no Sb/Br)
TBD
Lead/Ball Finish
MSL Peak Temp (3)
SNPB
Level-3-220C-168 HR
SNAGCU
Level-3-250C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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to Customer on an annual basis.
Addendum-Page 1
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