SCBS747C − SEPTEMBER 2000 − REVISED SEPTEMBER 2003
D Member of Texas Instruments Widebus+
D
D
D
D Supports Unregulated Battery Operation
Family
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
Ioff and Power-Up 3-State Support Hot
Insertion
Supports Mixed-Mode Signal Operation
(5-V Input/Output Voltage With 3.3-V VCC)
GKE OR ZKE PACKAGE
(TOP VIEW)
1
2
3
4
5
Down to 2.7 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
D
D
terminal assignments
6
1
2
3
4
5
6
A
A
1Y2
1Y1
1OE
2OE
1A1
1A2
B
B
1Y4
1Y3
GND
GND
1A3
1A4
C
C
2Y2
2Y1
2A2
D
2Y2
2Y3
1VCC
GND
2A1
D
1VCC
GND
2A3
2A4
E
3Y2
3Y1
GND
GND
3A1
3A2
F
3Y4
3Y3
3A4
4Y2
4Y1
1VCC
GND
3A3
G
1VCC
GND
4A1
4A2
H
4Y3
4Y4
4OE
3OE
4A4
4A3
J
5Y2
5Y1
5OE
6OE
5A1
5A2
E
F
G
H
J
K
5Y4
5Y3
GND
GND
5A3
5A4
K
L
6Y2
6Y1
6A2
M
6Y4
6Y3
2VCC
GND
6A1
L
2VCC
GND
6A3
6A4
M
N
7Y2
7Y1
GND
GND
7A1
7A2
N
P
7Y4
7Y3
7A4
R
8Y2
8Y1
2VCC
GND
7A3
P
2VCC
GND
8A1
8A2
R
T
8Y3
8Y4
8OE
7OE
8A4
8A3
T
description/ordering information
The SN74LVT32240 is a 32-bit buffer and line driver designed for low-voltage (3.3-V) VCC operation, but with
the capability to provide a TTL interface to a 5-V system environment. This device can be used as eight 4-bit
buffers, four 8-bit buffers, two 16-bit buffers, or one 32-bit buffer. The device provides inverted outputs and
symmetrical active-low output-enable (OE) inputs. It is designed specifically to improve both the performance
and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
PACKAGE†
TA
LFBGA − GKE
−40°C to 85°C
LFBGA − ZKE (Pb-free)
TOP-SIDE
MARKING
SN74LVT32240GKER
Tape and reel
SN74LVT32240ZKER
VJ240
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ is a trademark of Texas Instruments.
Copyright 2003, Texas Instruments Incorporated
!"# $ %&'# "$ (&)*%"# +"#'
+&%#$ %! # $('%%"#$ (' #,' #'!$ '-"$ $#&!'#$
$#"+"+ .""#/ +&%# (%'$$0 +'$ # '%'$$"*/ %*&+'
#'$#0 "** (""!'#'$
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1
SCBS747C − SEPTEMBER 2000 − REVISED SEPTEMBER 2003
description/ordering information (continued)
When VCC is between 0 and 1.5-V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5-V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
FUNCTION TABLE
(each 4-bit buffer/driver)
INPUTS
2
OE
A
OUTPUT
Y
L
H
L
L
L
H
H
X
Z
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCBS747C − SEPTEMBER 2000 − REVISED SEPTEMBER 2003
logic diagram (positive logic)
1OE
1A1
1A2
1A3
1A4
2OE
2A1
2A2
2A3
2A4
5OE
5A1
5A2
5A3
5A4
6OE
6A1
6A2
6A3
6A4
A3
3OE
A5
A2
A6
A1
B5
B2
B6
B1
1Y1
3A1
1Y2
3A2
1Y3
3A3
1Y4
3A4
A4
4OE
C5
C2
C6
C1
D5
D2
D6
D1
2Y1
4A1
2Y2
4A2
2Y3
4A3
2Y4
4A4
J3
7OE
J5
J2
J6
J1
K5
K2
K6
K1
5Y1
7A1
5Y2
7A2
5Y3
7A3
5Y4
7A4
J4
8OE
L5
L2
L6
L1
M5
M2
M6
M1
6Y1
8A1
6Y2
8A2
6Y3
8A3
6Y4
8A4
POST OFFICE BOX 655303
H4
E5
E2
E6
E1
F5
F2
F6
F1
3Y1
3Y2
3Y3
3Y4
H3
G5
G2
G6
G1
H6
H1
H5
H2
4Y1
4Y2
4Y3
4Y4
T4
N5
N2
N6
N1
P5
P2
P6
P1
7Y1
7Y2
7Y3
7Y4
T3
R5
R2
R6
R1
T6
T1
T5
T2
• DALLAS, TEXAS 75265
8Y1
8Y2
8Y3
8Y4
3
SCBS747C − SEPTEMBER 2000 − REVISED SEPTEMBER 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high-impedance
or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Current into any output in the high state, IO (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Package thermal impedance, θJA (see Note 3): GKE/ZKE package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
MIN
MAX
2.7
3.6
UNIT
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
0.8
V
Input voltage
5.5
V
IOH
IOL
High-level output current
−32
mA
Low-level output current
64
mA
∆t/∆v
Input transition rise or fall rate
10
ns/V
∆t/∆VCC
TA
Power-up ramp rate
200
Operating free-air temperature
−40
High-level input voltage
2
Outputs enabled
V
V
µs/V
85
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
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SCBS747C − SEPTEMBER 2000 − REVISED SEPTEMBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TYP†
MIN
MAX
UNIT
−1.2
V
VIK
VCC = 2.7 V,
VCC = 2.7 V to 3.6 V,
II = −18 mA
IOH = −100 µA
VOH
VCC = 2.7 V,
VCC = 3 V,
IOH = −8 mA
IOH = −32 mA
IOL = 100 µA
IOL = 24 mA
0.2
VCC = 2.7 V
IOL = 16 mA
IOL = 32 mA
0.4
IOL = 64 mA
VI = 5.5 V
0.55
VOL
VCC = 3 V
Control inputs
VCC = 0 or 3.6 V,
VCC = 3.6 V,
Data inputs
VCC = 3.6 V
II
VCC−0.2
2.4
V
2
0.5
V
0.5
10
±1
VI = VCC or GND
VI = VCC
1
VI = 0
VI or VO = 0 to 4.5 V
µA
A
−5
±100
µA
5
µA
−5
µA
± 100
µA
Ioff
IOZH
VCC = 0,
VCC = 3.6 V,
IOZL
VCC = 3.6 V,
IOZPU
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE = don’t care
IOZPD
VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE = don’t care
±100
µA
ICC
VCC = 3.6 V, IO = 0,
VI = VCC or GND
VO = 3 V
VO = 0.5 V
Outputs high
10
Outputs disabled
∆ICC‡
VCC = 3 V to 3.6 V, One input at VCC − 0.6 V,
Other inputs at VCC or GND
Ci
VI = 3 V or 0
VO = 3 V or 0
Co
0.38
Outputs low
mA
0.38
0.2
mA
4
pF
9
pF
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A
Y
tPZH
tPZL
OE
Y
tPHZ
tPLZ
OE
Y
PARAMETER
tsk(o)
† All typical values are at VCC = 3.3 V, TA = 25°C.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
MIN
TYP†
MAX
1
2.2
3.5
4
1
2.7
3.5
4
MIN
UNIT
MAX
1
2.6
4
4.9
1.2
2.6
4.4
4.6
2
3.4
4.5
5
2
3.2
4.2
4.2
0.5
0.5
ns
ns
ns
ns
5
SCBS747C − SEPTEMBER 2000 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
6V
500 Ω
From Output
Under Test
S1
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
2.7 V
LOAD CIRCUIT
1.5 V
Timing Input
0V
tw
tsu
2.7 V
1.5 V
Input
th
2.7 V
1.5 V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
2.7 V
Input
1.5 V
1.5 V
0V
tPHL
tPLH
VOH
Output
1.5 V
1.5 V
VOL
1.5 V
Output
Waveform 1
S1 at 6 V
(see Note B)
tPZL
tPLZ
3V
1.5 V
tPZH
VOH
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
0V
tPLH
tPHL
Output
2.7 V
Output
Control
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
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