SCLS141D – DECEMBER 1982 – REVISED DECEMBER 2002 D Wide Operating Voltage Range of 2 V to 6 V D High-Current 3-State True Outputs Can D D D D Drive Up To 15 LSTTL Loads D Eight D-Type Flip-Flops in a Single Package D Full Parallel Access for Loading Low Power Consumption, 80-µA Max ICC Typical tpd = 14 ns ±6-mA Output Drive at 5 V Low Input Current of 1 µA Max SN54HC374 . . . FK PACKAGE (TOP VIEW) 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q CLK 2D 2Q 3Q 3D 4D 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 8D 7D 7Q 6Q 6D 4Q GND CLK 5Q 5D OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND 1D 1Q OE VCC 8Q SN54HC374 . . . J OR W PACKAGE SN74HC374 . . . DB, DW, N, NS, OR PW PACKAGE (TOP VIEW) description/ordering information These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight flip-flops of the ’HC374 devices are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels that were set up at the data (D) inputs. An output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. ORDERING INFORMATION PDIP – N –55°C 55 C to 125 125°C C TOP-SIDE MARKING Tube SN74HC374N Tube SN74HC374DW Tape and reel SN74HC374DWR SOP – NS Tape and reel SN74HC374NSR HC374 SSOP – DB Tape and reel SN74HC374DBR HC374 TSSOP – PW Tape and reel SN74HC374PWR HC374 CDIP – J Tube SNJ54HC374J SNJ54HC374J CFP – W Tube SNJ54HC374W SNJ54HC374W LCCC – FK Tube SNJ54HC374FK SOIC – DW –40°C 40°C to 85°C ORDERABLE PART NUMBER PACKAGE† TA SN74HC374N HC374 SNJ54HC374FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2002, Texas Instruments Incorporated ! " #$%! " &$'(# ! ) !%* )$#!" # ! "&%## !" &% !+% !%" %, " "!$%!" "! ) ) - !.* )$#! &#%""/ )%" ! %#%"" (. #($)% !%"!/ (( & %!%"* &)$#!" #&( ! ! 01 (( & %!%" % !%"!%) $(%"" !+%-"% !%)* (( !+% &)$#!" &)$#! &#%""/ )%" ! %#%"" (. #($)% !%"!/ (( & %!%"* POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCLS141D – DECEMBER 1982 – REVISED DECEMBER 2002 description/ordering information (continued) OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. FUNCTION TABLE (each flip-flop) INPUTS OE CLK D OUTPUT Q L ↑ H H L ↑ L L L H or L X Q0 H X X Z logic diagram (positive logic) OE CLK 1 11 C1 1D 3 1D 2 1Q To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCLS141D – DECEMBER 1982 – REVISED DECEMBER 2002 recommended operating conditions (see Note 3) SN54HC374 VCC VIH Supply voltage VCC = 2 V VCC = 4.5 V High-level High level in input ut voltage VCC = 6 V VCC = 2 V VIL VI VO ∆t/∆v MIN NOM MAX 2 5 6 Input voltage MAX 2 5 6 3.15 3.15 4.2 4.2 0 VCC = 6 V UNIT V V 0.5 0.5 1.35 1.35 1.8 1.8 VCC VCC VCC = 2 V VCC = 4.5 V Input In ut transition rise/fall time NOM 1.5 0 Output voltage MIN 1.5 VCC = 4.5 V VCC = 6 V Low-level Low level in input ut voltage SN74HC374 0 VCC VCC 0 1000 1000 500 500 400 400 V V V ns TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL TEST CONDITIONS VI = VCC or 0, MIN MAX SN74HC374 MIN MAX UNIT 1.9 1.998 1.9 1.9 IOH = –20 20 µA 4.4 4.499 4.4 4.4 6V 5.9 5.999 5.9 5.9 IOH = –6 mA IOH = –7.8 mA 4.5 V 3.98 4.3 3.7 3.84 6V 5.48 5.8 5.2 5.34 2V 0.002 0.1 0.1 0.1 IOL = 20 µA 4.5 V 0.001 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 4.5 V 0.17 0.26 0.4 0.33 6V 0.15 0.26 0.4 0.33 6V ±0.1 ±100 ±1000 ±1000 nA 6V ±0.01 ±0.5 ±10 ±5 µA 8 160 80 µA 10 10 10 pF IOL = 6 mA IOL = 7.8 mA ICC Ci SN54HC374 2V VI = VIH or VIL VI = VCC or 0 VO = VCC or 0 TA = 25°C MIN TYP MAX 4.5 V VI = VIH or VIL II IOZ VCC IO = 0 6V 2 V to 6 V POST OFFICE BOX 655303 3 • DALLAS, TEXAS 75265 V V 3 SCLS141D – DECEMBER 1982 – REVISED DECEMBER 2002 timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC fclock Clock frequency tw Pulse duration, CLK high or low tsu Setup time, data before CLK↑ Setu th Hold time,, data after CLK↑ TA = 25°C MIN MAX SN54HC374 MIN MAX SN74HC374 MIN MAX 2V 6 4 5 4.5 V 30 20 24 6V 35 24 28 2V 80 120 100 4.5 V 16 24 20 6V 14 20 17 2V 100 150 125 4.5 V 20 30 25 6V 17 25 21 2V 10 13 12 4.5 V 5 5 5 6V 5 5 5 UNIT MHz ns ns ns switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tpd d ten tdis tt 4 CLK OE OE Any Q Any Q Any Q Any yQ VCC TA = 25°C MIN TYP MAX SN54HC374 MIN MAX SN74HC374 MIN 2V 6 12 4 5 4.5 V 30 60 20 24 6V 35 70 24 28 MAX MHz 2V 63 180 270 225 4.5 V 17 36 54 45 6V 15 31 46 38 2V 60 150 225 190 4.5 V 16 30 45 38 6V 14 26 38 32 2V 36 150 225 190 4.5 V 17 30 45 38 6V 16 26 38 32 2V 28 60 90 75 4.5 V 8 12 18 15 6V 6 10 15 13 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT ns ns ns ns SCLS141D – DECEMBER 1982 – REVISED DECEMBER 2002 switching characteristics over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tpd d ten tt CLK OE Any Q Any Q Any yQ VCC MIN TA = 25°C TYP MAX SN54HC374 MIN MAX SN74HC374 MIN 2V 6 12 5 4.5 V 30 60 24 6V 35 70 28 MAX UNIT MHz 2V 80 230 345 290 4.5 V 22 46 69 58 6V 19 39 58 49 2V 70 200 300 250 4.5 V 25 40 60 50 6V 22 34 51 43 2V 45 210 315 265 4.5 V 17 42 63 53 6V 13 36 53 45 ns ns ns operating characteristics, TA = 25°C PARAMETER Cpd Power dissipation capacitance per flip-flop POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TEST CONDITIONS TYP UNIT No load 100 pF 5 SCLS141D – DECEMBER 1982 – REVISED DECEMBER 2002 PARAMETER MEASUREMENT INFORMATION VCC From Output Under Test CL (see Note A) PARAMETER tPZH S1 Test Point RL ten RL tdis S2 tPZL tPHZ tPLZ 1 kΩ 1 kΩ Reference Input VCC 50% Data Input VCC 50% 10% 50% VCC 0V In-Phase Output 50% 10% tPHL 90% 90% tr tPHL Out-ofPhase Output 90% tf Open Closed Closed Open Open Open VCC th 90% 90% VCC 50% 10% 0 V tf 50% 10% Output Control (Low-Level Enabling) VCC 50% 50% 0V tPZL VOH 50% 10% V OL tf Output Waveform 1 (See Note B) tPLZ 90% VOH VOL Output Waveform 2 (See Note B) ≈VCC ≈VCC 50% 10% tPZH tPLH 50% 10% Open VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES 50% tPLH Closed tr VOLTAGE WAVEFORMS PULSE DURATIONS 50% Closed 0V 0V Input Open tsu 0V 50% 50 pF or 150 pF 50% 50% tw Low-Level Pulse S2 50 pF or 150 pF LOAD CIRCUIT High-Level Pulse S1 50 pF –– tpd or tt CL VOL tPHZ 50% 90% VOH ≈0 V tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. For clock inputs, fmax is measured when the input duty cycle is 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tPLZ and tPHZ are the same as tdis. G. tPZL and tPZH are the same as ten. H. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MCER002C – JANUARY 1995 – REVISED JUNE 1999 J (R-GDIP-T**) CERAMIC DUAL-IN-LINE 14 LEADS SHOWN PINS ** 14 16 20 A MAX 0.310 (7,87) 0.310 (7,87) 0.310 (7,87) A MIN 0.290 (7,37) 0.290 (7,37) 0.290 (7,37) B MAX 0.785 (19,94) 0.785 (19,94) 0.975 (24,77) B MIN 0.755 (19,18) 0.755 (19,18) 0.930 (23,62) C MAX 0.300 (7,62) 0.300 (7,62) 0.300 (7,62) C MIN 0.245 (6,22) 0.245 (6,22) 0.245 (6,22) DIM B 14 8 C 1 7 0.065 (1,65) 0.045 (1,14) 0.100 (2,54) 0.070 (1,78) 0.020 (0,51) MIN A 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0°–15° 0.014 (0,36) 0.008 (0,20) 0.100 (2,54) 4040083/E 03/99 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package is hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification. Falls within MIL STD 1835 GDIP1-T14, GDIP1-T16, and GDIP1-T20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 MECHANICAL DATA MCFP006A– JANUARY 1995 – REVISED FEBRUARY 2002 W (R-GDFP-F20) CERAMIC DUAL FLATPACK Base and Seating Plane 0.300 (7,62) 0.245 (6,22) 0.045 (1,14) 0.026 (0,66) 0.006 (0,15) 0.004 (0,10) 0.100 (2,54) 0.045 (1,14) 0.320 (8,13) MAX 1 0.019 (0,48) 0.015 (0,38) 20 0.050 (1,27) 0.540 (13,72) 0.490 (12,45) 0.005 (0,13) MIN 4 Places 10 11 0.260 (6,60) 0.200 (5,08) 0.260 (6,60) 0.200 (5,08) 4040180-4 / C 02/02 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification only. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 MECHANICAL DATA MLCC006B – OCTOBER 1996 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 MECHANICAL MPDI002C – JANUARY 1995 – REVISED DECEMBER 20002 N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE 16 PINS SHOWN PINS ** 14 16 18 20 A MAX 0.775 (19,69) 0.775 (19,69) 0.920 (23,37) 1.060 (26,92) A MIN 0.745 (18,92) 0.745 (18,92) 0.850 (21,59) 0.940 (23,88) MS-100 VARIATION AA BB AC DIM A 16 9 0.260 (6,60) 0.240 (6,10) 1 C AD 8 0.070 (1,78) 0.045 (1,14) 0.045 (1,14) 0.030 (0,76) D D 0.325 (8,26) 0.300 (7,62) 0.020 (0,51) MIN 0.015 (0,38) Gauge Plane 0.200 (5,08) MAX Seating Plane 0.010 (0,25) NOM 0.125 (3,18) MIN 0.100 (2,54) 0.430 (10,92) MAX 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M 14/18 PIN ONLY 20 pin vendor option D 4040049/E 12/2002 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001, except 18 and 20 pin minimum body lrngth (Dim A). D. The 20 pin end lead shoulder width is a vendor option, either half or full width. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 MECHANICAL DATA MSOI003E – JANUARY 1995 – REVISED SEPTEMBER 2001 DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 16 PINS SHOWN 0.020 (0,51) 0.014 (0,35) 9 0.050 (1,27) 16 0.010 (0,25) 0.419 (10,65) 0.400 (10,15) 0.010 (0,25) NOM 0.299 (7,59) 0.291 (7,39) Gage Plane 0.010 (0,25) 1 8 0°– 8° 0.050 (1,27) 0.016 (0,40) A Seating Plane 0.104 (2,65) MAX 0.012 (0,30) 0.004 (0,10) PINS ** 0.004 (0,10) 16 18 20 24 28 A MAX 0.410 (10,41) 0.462 (11,73) 0.510 (12,95) 0.610 (15,49) 0.710 (18,03) A MIN 0.400 (10,16) 0.453 (11,51) 0.500 (12,70) 0.600 (15,24) 0.700 (17,78) DIM 4040000/E 08/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MS-013 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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