SIPEX SP3243EBCR

®
SP3223EB/3243EB
Intelligent +3.0V to +5.5V RS-232 Transceivers
■ Meets true EIA/TIA-232-F Standards
from a +3.0V to +5.5V power supply
■ Interoperable with EIA/TIA-232 and
adheres to EIA/TIA-562 down to a +2.7V
power source
■ AUTO ON-LINE® circuitry automatically
wakes up from a 1µA shutdown
■ Minimum 250kbps data rate under load
■ Regulated Charge Pump Yields Stable
RS-232 Outputs Regardless of VCC
Variations
■ Enhanced ESD Specifications:
+15kV Human Body Model
+15kV IEC1000-4-2 Air Discharge
+8kV IEC1000-4-2 Contact Discharge
EN
20 SHUTDOWN
1
C1+ 2
19 VCC
V+
3
18 GND
C1-
4
17
C2+
5
SP3223EB 16
C2-
6
15 R1OUT
V-
7
14
T1OUT
R1IN
ONLINE
T2OUT
8
13 T1IN
R2IN
9
12 T2IN
R2OUT 10
11
STATUS
Now Available in Lead Free Packaging
DESCRIPTION
The SP3223EB and SP3243EB products are RS-232 transceiver solutions intended for
portable or hand-held applications such as notebook and palmtop computers. The SP3223EB
and SP3243EB use an internal high-efficiency, charge-pump power supply that requires only
0.1µF capacitors in 3.3V operation. This charge pump and Sipex's driver architecture allow
the SP3223EB/3243EB series to deliver compliant RS-232 performance from a single power
supply ranging from +3.0V to +5.5V. The SP3223EB is a 2-driver/2-receiver device, and the
SP3243EB is a 3-driver/5-receiver device ideal for laptop/notebook computer and PDA
applications. The SP3243EB includes one complementary receiver that remains alert to
monitor an external device's Ring Indicate signal while the device is shutdown.
The AUTO ON-LINE® feature allows the device to automatically "wake-up" during a shutdown
state when an RS-232 cable is connected and a connected peripheral is turned on. Otherwise,
the device automatically shuts itself down drawing less than 1µA.
SELECTION TABLE
Device
Power Supplies
RS-232
Drivers
RS-232
Receivers
External
Components
AUTO ON-LINE®
Circuitry
TTL 3-State
No. of
Pins
SP3223EB
+3.0V to +5.5V
2
2
4 capacitors
YES
YES
20
SP3243EB
+3.0V to +5.5V
3
5
4 capacitors
YES
YES
28
Applicable U.S. Patents - 5,306,954; and other patents pending.
Date: 6/2/04
SP3223EB/3243EB +3.0V to +5.5V RS-232 Transceivers
1
© Copyright 2004 Sipex Corporation
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation
of the device at these ratings or any other above those
indicated in the operation sections of the specifications
below is not implied. Exposure to absolute maximum
rating conditions for extended periods of time may
affect reliability and cause permanent damage to the
device.
VCC ...................................................... -0.3V to +6.0V
V+ (NOTE 1) ...................................... -0.3V to +7.0V
V- (NOTE 1) ....................................... +0.3V to -7.0V
V+ + |V-| (NOTE 1) ........................................... +13V
ICC (DC VCC or GND current) ......................... +100mA
Input Voltages
TxIN, ONLINE,
SHUTDOWN, EN (SP3223E) ............ -0.3V to +6.0V
RxIN .................................................................. +25V
Output Voltages
TxOUT ........................................................... +13.2V
RxOUT, STATUS ..................... -0.3V to (VCC + 0.3V)
Short-Circuit Duration
TxOUT .................................................... Continuous
Storage Temperature ...................... -65°C to +150°C
Power Dissipation per package
28-pin PDIP
(derate 16.0mW/°C above+70°C) ...................... 1300mW
20-pin SSOP
(derate 9.25mW/°C above +70°C) ...................... 750mW
20-pin TSSOP
(derate 11.1mW/°C above +70°C) ....................... 900mW
28-pin SOIC
(derate 12.7mW/°C above +70°C) .................... 1000mW
28-pin SSOP
(derate 11.2mW/°C above +70°C) ...................... 900mW
28-pin TSSOP
(derate 11.1mW/°C above +70°C) ....................... 900mW
32-pin QFN
NOTE 1: V+ and V- can have maximum magnitudes of 7V, but their absolute difference cannot exceed 13V.
ELECTRICAL CHARACTERISTICS
Unless otherwise noted, the following specifications apply for VCC = +3.0V to +5.5V with TAMB = TMIN to TMAX,
C1 - 4 = 0.1µF. Typical values apply at VCC = +3.3V or +5.0V and TAMB = 25°C.
PARAMETER
MIN.
TYP.
MAX. UNITS CONDITIONS
DC CHARACTERISTICS
Supply Current,
AUTO ON-LINE®
1.0
10
µA
All RxIN open, ONLINE = GND,
SHUTDOWN = VCC, TxIN = VCC or
GND,VCC = +3.3V, TAMB = +25°C
Supply Current, Shutdown
1.0
10
µA
SHUTDOWN = GND,
VCC = +3.3V, TAMB = +25°C,
TxIN = VCC or GND
Supply Current,
AUTO ON-LINE® Disabled
0.3
1.0
mA
ONLINE = SHUTDOWN = VCC,
TxIN = VCC or GND,
no load, VCC = +3.3V, TAMB = +25°C
0.8
VCC
V
V
VCC = +3.3V or +5.0V, TxIN,
EN (SP3223EB), ONLINE,
SHUTDOWN
LOGIC INPUTS AND RECEIVER OUTPUTS
Input Logic Threshold
LOW
HIGH
GND
2.4
Input Leakage Current
SHUTDOWN,
±0.01
±1.0
µA
TxIN, EN (SP3223EB), ONLINE,
Output Leakage Current
±0.05
±10
µA
Receivers disabled, VOUT = 0V to
VCC
0.4
TAMB = +25°C, VIN = 0V to VCC
Output Voltage LOW
V
IOUT = 1.6mA
VCC - 0.6
VCC - 0.1
V
IOUT = -1.0mA
Output Voltage Swing
±5.0
±5.4
V
All driver outputs loaded with 3KΩ
to GND, TAMB = +25°C
Output Resistance
300
Ω
VCC = V+ = V- = 0V, VOUT = ±2V
Output Voltage HIGH
DRIVER OUTPUTS
Output Short-Circuit Current
±35
Output Leakage Current
Date: 6/2/04
±60
mA
VOUT = 0V
±25
µA
VCC = 0V or 3.0V to 5.5V,
VOUT = ±12V, Drivers disabled
SP3223EB/3243EB +3.0V to +5.5V RS-232 Transceivers
2
© Copyright 2004 Sipex Corporation
ELECTRICAL CHARACTERISTICS
Unless otherwise noted, the following specifications apply for VCC = +3.0V to +5.5V with TAMB = TMIN to TMAX,
C1 - 4 = 0.1µF. Typical values apply at VCC = +3.3V or +5.0V and TAMB = 25°C.
PARAMETER
MIN.
TYP.
MAX. UNITS CONDITIONS
RECEIVER INPUTS
Input Voltage Range
-25
Input Threshold LOW
0.6
1.2
25
V
V
Input Threshold LOW
0.8
1.5
V
VCC = 5.0V
VCC = 3.3V
Input Threshold HIGH
1.5
2.4
V
VCC = 3.3V
Input Threshold HIGH
1.8
2.4
V
VCC = 5.0V
7
kΩ
Input Hysteresis
Input Resistance
0.3
3
V
5
AUTO ON-LINE® CIRCUITRY CHARACTERISTICS (ONLINE = GND, SHUTDOWN = VCC)
STATUS Output Voltage LOW
STATUS Output Voltage HIGH
0.4
VCC - 0.6
Receiver Threshold to Drivers
Enabled (tONLINE)
V
IOUT = 1.6mA
V
IOUT = -1.0mA
200
µs
Figure 20
Receiver Positive or Negative
Threshold to STATUS HIGH
(tSTSH)
0.5
µs
Figure 20
Receiver Positive or Negative
Threshold to STATUS LOW
(tSTSL)
20
µs
Figure 20
TIMING CHARACTERISTICS
Maximum Data Rate
250
kbps
RL = 3KΩ, CL = 1000pF,
one driver active
Receiver Propagation Delay
tPHL
tPLH
0.15
0.15
µs
Receiver input to Receiver output,
CL = 150pF
Receiver Output Enable Time
200
ns
Normal operation
Receiver Output Disable Time
200
ns
Normal operation
Driver Skew
100
ns
| tPHL - tPLH |, TAMB = 25°C
Receiver Skew
50
ns
| tPHL - tPLH |
Transition-Region Slew Rate
Date: 6/2/04
30
V/µs
VCC= 3.3V, RL = 3KΩ, TAMB = 25°C,
measurements taken from -3.0V to
+3.0V or +3.0V to -3.0V
SP3223EB/3243EB +3.0V to +5.5V RS-232 Transceivers
3
© Copyright 2004 Sipex Corporation
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted, the following performance characteristics apply for VCC = +3.3V, 250kbps data rate, all drivers
loaded with 3KΩ, 0.1µF charge pump capacitors, and TAMB = +25°C.
30
4
25
TxOUT +
Slew rate (V/µs)
Transmitter Output
Voltage (VDC)
6
2
0
-2
TxOUT -
-4
-6
15
10
1000
1 Transmitter at 250Kbps
1 Transmitter at 15.6Kbps
All drivers loaded 3K + Load Cap
5
0
0
- Slew
+ Slew
20
2000
3000
4000
5000
0
500
1000
Figure 1. Transmitter Output Voltage VS. Load
Capacitance for the SP3223EB
3000
4000
5000
Figure 2. Slew Rate VS. Load Capacitance for the
SP3223EB
35
20
25
Supply Current (mA)
30
I CC (mA)
2000
Load Capacitance (pF)
Load Capacitance (pF)
250Kbps
20
125Kbps
15
20Kbps
10
1 Transmitter at 250Kbps
1 Transmitter at 15.6Kbps
All drivers loaded 3K + Load Cap
5
0
0
1000
2000
3000
4000
15
10
0
5000
1 Transmitter at 250Kbps
2 Transmitters at 15.6Kbps
All drivers loaded with 3K // 1000pF
5
2.7
3
Load Capacitance (pF)
3.5
4
4.5
5
Supply Voltage (VDC)
Figure 4. Supply Current VS. Supply Voltage for
the SP3243EB
Figure 3. Supply Current VS. Load Capacitance when
Transmitting Data for the SP3223EB
6
6
4
4
2
2
Transmitter Output
Voltage (V)
Transmitter Output
Voltage (VDC)
TxOUT +
0
-2
-4
-6
TxOUT -
2.7
3
3.5
4
4.5
5
TxOUT +
0
-2
TxOUT -
-4
-6
0
1000
3000
4000
5000
Figure 6. Transmitter Output Voltage VS. Load
Capacitance for the SP3243EB
Figure 5. Transmitter Output Voltage VS. Supply
Voltage for the SP3243EB
Date: 6/2/04
2000
Load Capacitance (pF)
Supply Voltage (VDC)
SP3223EB/3243EB +3.0V to +5.5V RS-232 Transceivers
4
© Copyright 2004 Sipex Corporation
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted, the following performance characteristics apply for VCC = +3.3V, 250kbps data rate, all drivers
loaded with 3KΩ, 0.1µF charge pump capacitors, and TAMB = +25°C.
40
20
Supply Current (mA)
Slew rate (V/µs)
25
- Slew
+ Slew
15
10
1 Transmitter at 250Kbps
2 Transmitter at 15.6Kbps
All drivers loaded 3K + Load Cap
5
0
35
30
120Kbps
250Kbps
25
20Kbps
20
15
1 Transmitter at full Data Rate
10
2 Transmitters at 15.5 Kbps
5
All Transmitters loades 3K + Load Cap
0
0
500
1000
2000
3000
4000
5000
0
1000
Load Capacitance (pF)
2000
3000
4000
5000
Load Capacitance (pF)
Figure 8. Supply Current VS. Load Capacitance when
Transmitting Data for the SP3243EB
Figure 7. Slew Rate VS. Load Capacitance for the
SP3243EB
25
6
20
4
Transmitter Output
Voltage (V)
Supply Current (mA)
TxOUT +
15
10
1 Transmitter at 250Kbps
2 Transmitters at 15.6Kbps
All drivers loaded with 3K // 1000pF
5
0
2.7
3
3.5
4
4.5
2
0
-2
-4
-6
5
TxOUT -
2.7
Figure 9. Supply Current VS. Supply Voltage for the
SP3243EB
Date: 6/2/04
3
3.5
4
4.5
5
Supply Voltage (VDC)
Supply Voltage (VDC)
Figure 10. Transmitter Output Voltage VS. Supply
Voltage for the SP3243EB
SP3223EB/3243EB +3.0V to +5.5V RS-232 Transceivers
5
© Copyright 2004 Sipex Corporation
NAME
FUNCTION
SP3223EB
PIN NUMBER
SP3243EB
SOIC, SSOP,
SP3243EBCR
TSSOP
QFN
EN
Receiver Enable. Apply logic LOW for normal operation.
Apply logic HIGH to disable the receiver outputs (high-Z state).
1
-
-
C1+
Positive terminal of the voltage doubler charge-pump capacitor.
2
28
28
V+
Regulated +5.5V output generated by the charge pump.
3
27
26
C1-
Negative terminal of the voltage doubler charge-pump capacitor.
4
24
22
C2+
Positive terminal of the inverting charge-pump capacitor.
5
1
29
C2-
Negative terminal of the inverting charge-pump capacitor.
6
2
31
Regulated -5.5V output generated by the charge pump.
7
3
32
R1IN
V-
RS-232 receiver input.
16
4
2
R2IN
RS-232 receiver input.
9
5
3
R3IN
RS-232 receiver input.
-
6
4
R4IN
RS-232 receiver input.
-
7
5
R5IN
RS-232 receiver input.
-
8
6
R1OUT
TTL/CMOS receiver output.
15
19
17
R2OUT
TTL/CMOS receiver output.
10
18
16
R2OUT
Non-inverting receiver-2 output, active in shutdown.
-
20
18
R3OUT
TTL/CMOS receiver output.
-
17
15
R4OUT
TTL/CMOS receiver output.
-
16
14
R5OUT
TTL/CMOS receiver output.
-
15
13
TTL/CMOS Output indicating online and shutdown status.
11
21
19
T1IN
TTL/CMOS driver input.
13
14
12
T2IN
TTL/CMOS driver input.
12
13
11
T3IN
TTL/CMOS driver input.
-
12
10
Apply logic HIGH to override Auto-Online circuitry keeping
drivers active (SHUTDOWN must also be logic HIGH,
refer to Table 2).
14
23
21
T1OUT
RS-232 driver output.
17
9
7
T2OUT
RS-232 driver output.
8
10
8
T3OUT
RS-232 driver output.
-
11
9
Ground.
18
25
23
+3.0V to +5.5V supply voltage.
19
26
25
20
22
20
-
-
1,24,27,30
STATUS
ONLINE
GND
VCC
SHUTDOWN Apply logic LOW to shut down drivers and charge pump.
This overrides all AUTO ON-LINE® circuitry and ONLINE
(refer to Table 2).
NC
No Connection
Table 1. Device Pin Description
Date: 6/2/04
SP3223EB/3243EB +3.0V to +5.5V RS-232 Transceivers
6
© Copyright 2004 Sipex Corporation
EN
1
C1+ 2
28 C1+
C2- 2
27
V+
V- 3
26
VCC
R1IN
4
25
GND
R2IN
5
24
C1-
19 VCC
V+
3
18 GND
C1-
4
17
C2+
5
SP3223EB 16
C2-
6
15 R1OUT
V-
7
14
T2OUT
8
13 T1IN
R2IN
9
12 T2IN
R2OUT 10
C2+ 1
20 SHUTDOWN
T1OUT
R1IN
ONLINE
6
R4IN
7
23 ONLINE
22 SHUTDOWN
21 STATUS
R5IN 8
STATUS
11
R3IN
SP3243EB
T1OUT 9
20
R2OUT
T2OUT 10
19
R1OUT
T3OUT 11
18
R2OUT
T3IN 12
17
R3OUT
T2IN 13
16
R4OUT
T1IN 14
15
R5OUT
Figure 12. SP3243EB Pinout Configuration
25
26
27
28
29
30
1
24
2
23
®
3
22
4
21
5
20
SP3243EB
6
19
16
15
14
13
NC
GND
C1ONLINE
SHUTDOWN
STATUS
R2OUT
R1OUT
T3OUT
T3IN
T2IN
T1IN
R5OUT
R4OUT
R3OUT
R2OUT
12
17
11
18
8
10
7
9
NC
R1IN
R2IN
R3IN
R4IN
R5IN
T1OUT
T2OUT
31
32
VC2NC
C2+
C1+
NC
V+
VCC
Figure 11. SP3223EB Pinout Configuration
Figure 13. SP3243EB QFN (QFN) Pinout Configuration
Date: 6/2/04
SP3223EB/3243EB +3.0V to +5.5V RS-232 Transceivers
7
© Copyright 2004 Sipex Corporation
+3.3V to +5V
+
C5
C1
+
19
0.1µF
VCC
2 C1+
V+
3
0.1µF
C3
+
0.1µF
4 C15 C2+
C2
+
0.1µF
TTL/CMOS
INPUTS
SP3223EB
V-
7
C4
6 C213 T1IN
T1OUT
12 T2IN
T2OUT
R1IN
15 R1OUT
RS-232
OUTPUTS
8
16
RS-232
INPUTS
R2IN
10 R2OUT
0.1µF
17
5kΩ
TTL/CMOS
OUTPUTS
+
9
5kΩ
VCC
1 EN
20
14
To µP Supervisor
Circuit
11
SHUTDOWN
ONLINE
STATUS
GND
18
Figure 14. SP3223EB Typical Operating Circuit
Date: 6/2/04
SP3223EB/3243EB +3.0V to +5.5V RS-232 Transceivers
8
© Copyright 2004 Sipex Corporation
VCC
C5
C1
+
+
26
VCC
0.1µF
28 C1+
V+
27
0.1µF
+
C3
0.1µF
24 C11 C2+
C2
+
0.1µF
TTL/CMOS
INPUTS
SP3243EB
V-
3
C4
2 C214 T1IN
T1OUT
9
13 T2IN
T2OUT
10
12 T3IN
T3OUT
11
+
0.1µF
RS-232
OUTPUTS
20 R2OUT
19 R1OUT
R1IN
4
R2IN
5
R3IN
6
R4IN
7
R5IN
8
5kΩ
18 R2OUT
5kΩ
TTL/CMOS
OUTPUTS
17 R3OUT
5kΩ
16 R4OUT
RS-232
INPUTS
5kΩ
15 R5OUT
VCC
22
23
To µP Supervisor
Circuit
5kΩ
SHUTDOWN
ONLINE
21 STATUS
GND
25
Figure 15. SP3243EB Typical Operating Circuit
Date: 6/2/04
SP3223EB/3243EB +3.0V to +5.5V RS-232 Transceivers
9
© Copyright 2004 Sipex Corporation
DESCRIPTION
The SP3223EB and SP3243EB transceivers meet
the EIA/TIA-232 and ITU-T V.28/V.24 communication protocols and can be implemented
in battery-powered, portable, or hand-held applications such as notebook or palmtop computers. The SP3223EB and SP3243EB devices
feature Sipex's proprietary and patented (U.S.-5,306,954) on-board charge pump circuitry that
generates ±5.5V RS-232 voltage levels from a
single +3.0V to +5.5V power supply. The
SP3223EB and SP3243EB devices can operate
at a data rate of 250kbps fully loaded.
The SP3223EB and SP3243EB series is an ideal
choice for power sensitive designs. The
SP3223EB and SP3243EB devices feature
AUTO ON-LINE® circuitry which reduces the
power supply drain to a 1µA supply current. In
many portable or hand-held applications, an RS232 cable can be disconnected or a connected
peripheral can be turned off. Under these conditions, the internal charge pump and the drivers
will be shut down. Otherwise, the system automatically comes online. This feature allows design engineers to address power saving concerns
without major design changes.
The SP3223EB is a 2-driver/2-receiver device,
and the SP3243EB is a 3-driver/5-receiver device ideal for portable or hand-held applications.
The SP3243EB includes one complementary
always-active receiver that can monitor an
external device (such as a modem) in shutdown.
This aids in protecting the UART or serial
controller IC by preventing forward biasing
of the protection diodes where VCC may be
disconnected.
THEORY OF OPERATION
The SP3223EB and SP3243EB series is made up
of four basic circuit blocks:
1. Drivers,
2. Receivers,
3. the Sipex proprietary charge pump, and
4. AUTO ON-LINE® circuitry.
Drivers
The drivers are inverting level transmitters that
convert TTL or CMOS logic levels to 5.0V EIA/
TIA-232 levels with an inverted sense relative to
the input logic levels. Typically, the RS-232
output voltage swing is +5.4V with no load and
+5V minimum fully loaded. The driver outputs
are protected against infinite short-circuits to
ground without degradation in reliability. These
drivers comply with the EIA-TIA-232F and all
previous RS-232 versions. Unused driver inputs
should be connected to GND or VCC.
VCC
+
C5
+
C1
26
VCC
0.1µF
28 C1+
V+
27
0.1µF
C3
+
0.1µF
24 C11 C2+
C2
+
0.1µF
SP3243EB
V- 3
C4
2 C214 T1IN
T1OUT
RTS
13 T2IN
T2OUT 10
DTR
12 T3IN
T3OUT 11
RxD
19 R1OUT
CTS
18 R2OUT
DSR
17 R3OUT
DCD
16 R4OUT
TxD
+
0.1µF
9
RS-232
OUTPUTS
20 R2OUT
UART
or
Serial C
R1IN 4
5KΩ
R2IN
5
5KΩ
R3IN
6
R4IN
7
R5IN
8
5KΩ
RS-232
INPUTS
The drivers can guarantee a data rate of 250kbps
fully loaded with 3kΩ in parallel with 1000pF,
ensuring compatibility with PC-to-PC communication software.
5KΩ
15 R5OUT
RI
VCC
22
23
5KΩ
SHUTDOWN
ONLINE
21 STATUS
GND
25
RESET
P
Supervisor
IC
VIN
The slew rate of the driver output is internally
limited to a maximum of 30V/µs in order to
meet the EIA standards (EIA RS-232D 2.1.7,
Paragraph 5). The transition of the loaded
output from HIGH to LOW also meets the
monotonicity requirements of the standard.
Figure 16. Interface Circuitry Controlled by Microprocessor Supervisory Circuit
Date: 6/2/04
SP3223EB/3243EB +3.0V to +5.5V RS-232 Transceivers
10
© Copyright 2004 Sipex Corporation
+3V to +5V
DEVICE: SP3223EB
+
C5
SHUTDOWN
EN
TXOUT
RXOUT
C1
0
0
High Z
Active
0
1
High Z
High Z
1
0
Active
Active
1
1
Active
High Z
+
0.1µF
VCC
C1+
V+
0.1µF
C3
C2+
C2
+
0.1µF
SP3223EB
SP3243EB
C4
T1IN
T1OUT
TXIN
TXOUT
DEVICE: SP3243EB
RXOUT
R2OUT
0
High Z
High Z
Active
1
Active
Active
Active
0.1µF
R1IN
5kΩ
RXIN
RXOUT
5kΩ
VCC
1000pF
EN
1000pF
SHUTDOWN
ONLINE
To µP Supervisor
Circuit
STATUS
GND
18
Table 2. SHUTDOWN and EN Truth Tables
Note: In AUTO ON-LINE® Mode where ONLINE =
GND and SHUTDOWN = VCC, the device will shut down
if there is no activity present at the Receiver inputs.
Figure 17. Loopback Test Circuit for RS-232 Driver
Data Transmission Rates
was active at 250kbps and all three drivers loaded
with an RS-232 receiver in parallel with a 1000pF
capacitor. A solid RS-232 data transmission
rate of 250kbps provides compatibility with many
designs in personal computer peripherals and
LAN applications.
The SP3223EB and SP3243EB drivers can maintain high data rates up to 250kbps fully loaded.
Figure 17. shows a loopback test circuit used to
test the SP3243EB RS-232 Drivers. Figure 18
shows the test results of the loopback circuit with
all three drivers active at 120kbps with typical
RS-232 loads in parallel with 1000pF capacitors.
Figure 19 shows the test results where one driver
Receivers
The receivers convert ±5.0V EIA/TIA-232
levels to TTL or CMOS logic output levels. All
receivers have an inverting output that can be
disabled by using the EN pin.
Figure 18. Loopback Test Circuit All Drivers at 120kbps
Date: 6/2/04
+
TTL/CMOS
INPUTS
R1OUT
TXOUT
0.1µF
V-
C2-
TTL/CMOS
OUTPUTS
SHUTDOWN
+
C1-
Figure 19. Loopback Test Circuit One Driver at 250kbps
SP3223EB/3243EB +3.0V to +5.5V RS-232 Transceivers
11
© Copyright 2004 Sipex Corporation
The charge pump operates in a discontinuous
mode using an internal oscillator. If the output
voltages are less than a magnitude of 5.5V, the
charge pump is enabled. If the output voltages
exceed a magnitude of 5.5V, the charge pump is
disabled. This oscillator controls the four phases
of the voltage shifting. A description of each
phase follows.
Receivers are active when the AUTO ON-LINE®
circuitry is enabled or when in shutdown.
During the shutdown, the receivers will continue
to be active. If there is no activity present at the
receivers for a period longer than 100µs or when
SHUTDOWN is enabled, the device goes into a
standby mode where the circuit draws 1µA.
Driving EN to a logic HIGH forces the outputs of
the receivers into high-impedance. The truth
table logic of the SP3223EB and SP3243EB driver
and receiver outputs can be found in Table 2.
Phase 1
— VSS charge storage — During this phase of
the clock cycle, the positive side of capacitors
C1 and C2 are initially charged to VCC. Cl+ is
then switched to GND and the charge in C1– is
transferred to C2–. Since C2+ is connected to
VCC, the voltage potential across capacitor C2 is
now 2 times VCC.
The SP3243EB includes an additional non-inverting receiver with an output R2OUT. R2OUT
is an extra output that remains active and monitors activity while the other receiver outputs are
forced into high impedance. This allows Ring
Indicator (RI) from a peripheral to be monitored
without forward biasing the TTL/CMOS inputs
of the other devices connected to the receiver
outputs.
Phase 2
— VSS transfer — Phase two of the clock
connects the negative terminal of C2 to the VSS
storage capacitor and the positive terminal of C2
to GND. This transfers a negative generated
voltage to C 3. This generated voltage is
regulated to a minimum voltage of -5.5V.
Simultaneous with the transfer of the voltage to
C3, the positive side of capacitor C1 is switched
to VCC and the negative side is connected to
GND.
Since receiver input is usually from a transmission line where long cable lengths and system
interference can degrade the signal, the inputs
have a typical hysteresis margin of 300mV. This
ensures that the receiver is virtually immune to
noisy transmission lines. Should an input be left
unconnected, an internal 5KΩ pulldown resistor
to ground will commit the output of the receiver
to a HIGH state.
Phase 3
— VDD charge storage — The third phase of the
clock is identical to the first phase — the charge
transferred in C1 produces –VCC in the negative
terminal of C1, which is applied to the negative
side of capacitor C2. Since C2+ is at VCC, the
voltage potential across C2 is 2 times VCC.
Charge Pump
The charge pump is a Sipex–patented design
(U.S. 5,306,954) and uses a unique approach
compared to older less–efficient designs. The
charge pump still requires four external
capacitors, but uses a four–phase voltage
shifting technique to attain symmetrical 5.5V
power supplies. The internal power supply
consists of a regulated dual charge pump that
provides output voltages 5.5V regardless of the
input voltage (VCC) over the +3.0V to +5.5V
range. This is important to maintain compliant
RS-232 levels regardless of power supply
fluctuations.
Date: 6/2/04
Phase 4
— VDD transfer — The fourth phase of the clock
connects the negative terminal of C2 to GND,
and transfers this positive generated voltage
across C2 to C4, the VDD storage capacitor. This
voltage is regulated to +5.5V. At this voltage,
the internal oscillator is disabled. Simultaneous
with the transfer of the voltage to C4, the
positive side of capacitor C1 is switched to VCC
and the negative side is connected to GND,
allowing the charge pump cycle to begin again.
The charge pump cycle will continue as long as
the operational conditions for the internal
oscillator are present.
SP3223EB/3243EB +3.0V to +5.5V RS-232 Transceivers
12
© Copyright 2004 Sipex Corporation
Since both V+ and V– are separately generated
from VCC, in a no–load condition V+ and V– will
be symmetrical. Older charge pump approaches
that generate V– from V+ will show a decrease in
the magnitude of V– compared to V+ due to the
inherent inefficiencies in the design.
The clock rate for the charge pump typically
operates at 250kHz. The external capacitors can
be as low as 0.1µF with a 16V breakdown
voltage rating.
S
H
U
T
RECEIVER +2.7V
0V
RS-232 INPUT
VOLTAGES -2.7V
D
O
W
N
VCC
STATUS
0V
tSTSL
tSTSH
tONLINE
+5V
DRIVER
RS-232 OUTPUT
VOLTAGES
0V
-5V
Figure 20. AUTO ON-LINE® Timing Waveforms
Date: 6/2/04
SP3223EB/3243EB +3.0V to +5.5V RS-232 Transceivers
13
© Copyright 2004 Sipex Corporation
VCC = +5V
C4
+5V
C1
+
C2
–
–5V
+
–
–
+
VDD Storage Capacitor
+
–
VSS Storage Capacitor
C3
–5V
Figure 21. Charge Pump — Phase 1
VCC = +5V
C4
C1
+
C2
–
+
–
–
+
+
–
VDD Storage Capacitor
VSS Storage Capacitor
C3
–10V
Figure 22. Charge Pump — Phase 2
[
T
]
+6V
a) C2+
T
1
0V
2
2
0V
b) C2T
-6V
Ch1 2.00V Ch2 2.00V M 1.00µs Ch1 1.96V
Figure 23. Charge Pump Waveforms
VCC = +5V
C4
+5V
+
C1
+
C2
–
–5V
–
+
–
–
+
VDD Storage Capacitor
VSS Storage Capacitor
C3
–5V
Figure 24. Charge Pump — Phase 3
VCC = +5V
+10V
C1
+
–
C2
C4
+
–
–
+
+
–
VDD Storage Capacitor
VSS Storage Capacitor
C3
Figure 25. Charge Pump — Phase 4
Date: 6/2/04
SP3223EB/3243EB +3.0V to +5.5V RS-232 Transceivers
14
© Copyright 2004 Sipex Corporation
4
-2
8.6
3.46
2.67
1.82
1.57
1.38
1.23
1.12
1.02
0.939
0.62
0
4.93
Vout+
Vout-
2
0.869
Transmitter Output Voltage [V]
6
-4
-6
Load Current Per Transmitter [mA]
Figure 26. SP3243EB Driver Output Voltages vs. Load
Current per Transmitter
C5
C1
+
+
VCC
26
0.1µF
VCC
28 C1+
V+
27
0.1µF
C3
+
0.1µF
24 C1-
SP3243EB
1 C2+
C2
+
0.1µF
V-
3
C4
2 C214 T1IN
T1OUT
9
13 T2IN
T2OUT
10
12 T3IN
T3OUT
11
+
0.1µF
20 R2OUT
19 R1OUT
R1IN
4
R2IN
5
R3IN
6
R4IN
7
R5IN
8
5kΩ
18 R2OUT
5kΩ
17 R3OUT
5kΩ
16 R4OUT
5kΩ
15 R5OUT
VCC
22
23
To µP Supervisor
Circuit
5kΩ
DB-9
Connector
SHUTDOWN
ONLINE
21 STATUS
6
7
8
9
GND
25
DB-9 Connector Pins:
1. Received Line Signal Detector
2. Received Data
3. Transmitted Data
4. Data Terminal Ready
5. Signal Ground (Common)
6.
7.
8.
9.
1
2
3
4
5
DCE Ready
Request to Send
Clear to Send
Ring Indicator
Figure 27. Circuit for the connectivity of the SP3243EB with a DB-9 connector
Date: 6/2/04
SP3223EB/3243EB +3.0V to +5.5V RS-232 Transceivers
15
© Copyright 2004 Sipex Corporation
RS - 232 SIGNAL
AT RECEIVER
INPUT
SHUTDOWN
INPUT
ONLINE INPUT
STATUS OUTPUT
TRANCEIVER
STATUS
YES
HIGH
LOW
HIGH
Normal Operation
(AUTO ON-LINE®)
NO
HIGH
HIGH
LOW
Normal Operation
NO
HIGH
LOW
LOW
Sutdown
(AUTO ON-LINE® )
YES
LOW
HIGH/LOW
HIGH
Shutdown
NO
LOW
HIGH/LOW
LOW
Shutdown
Table 3. AUTO ON-LINE® Logic
RXINACT
Inactive Detection Block
RS-232
Receiver Block
RXIN
RXOUT
Figure 28. Stage I of AUTO ON-LINE® Circuitry
Delay
Stage
Delay
Stage
Delay
Stage
Delay
Stage
Delay
Stage
STATUS
R1INACT
R2INACT
R4INACT
R3INACT
R5INACT
SHUTDOWN
Figure 29. Stage II of AUTO ON-LINE® Circuitry
Date: 6/2/04
SP3223EB/3243EB +3.0V to +5.5V RS-232 Transceivers
16
© Copyright 2004 Sipex Corporation
receiver's RXINACT signals with an accumulated delay that disables the device to a 1µA
supply current.
The STATUS pin goes to a logic LOW when the
cable is disconnected, the external transmitters
are disabled, or the SHUTDOWN pin is
invoked. The typical accumulated delay is
around 20µs.
AUTO ON-LINE® Circuitry
The SP3223EB and SP3243EB devices have a
patent pending AUTO ON-LINE® circuitry on
board that saves power in applications such as
laptop computers, palmtop (PDA) computers,
and other portable systems.
When the SP3223EB and SP3243EB drivers or
internal charge pump are disabled, the supply
current is reduced to 1µA. This can commonly
occur in hand-held or portable applications where
the RS-232 cable is disconnected or the RS-232
drivers of the connected peripheral are turned off.
The SP3223EB and SP3243EB devices incorporate an AUTO ON-LINE® circuit that automatically enables itself when the external transmitters are enabled and the cable is connected.
Conversely, the AUTO ON-LINE® circuit also
disables most of the internal circuitry when the
device is not being used and goes into a standby
mode where the device typically draws 1µA.
This function can also be externally controlled
by the ONLINE pin. When this pin is tied to a
logic LOW, the AUTO ON-LINE® function is
active. Once active, the device is enabled until
there is no activity on the receiver inputs. The
receiver input typically sees at least ±3V, which
are generated from the transmitters at the other
end of the cable with a ±5V minimum. When the
external transmitters are disabled or the cable is
disconnected, the receiver inputs will be pulled
down by their internal 5kΩ resistors to ground.
When this occurs over a period of time, the
internal transmitters will be disabled and the
device goes into a shutdown or standby mode.
When ONLINE is HIGH, the AUTO ON-LINE®
mode is disabled.
The AUTO ON-LINE® mode can be disabled by
the SHUTDOWN pin. If this pin is a logic LOW,
the AUTO ON-LINE® function will not operate
regardless of the logic state of the ONLINE pin.
Table 3 summarizes the logic of the AUTO ONLINE® operating modes. The truth table logic of
the SP3223EB and SP3243EB driver and receiver outputs can be found in Table 2.
The STATUS pin outputs a logic LOW signal
if the device is shutdown. This pin goes to a
logic HIGH when the external transmitters are
enabled and the cable is connected.
When the SP3223EB and SP3243EB devices
are shut down, the charge pumps are turned off.
V+ charge pump output decays to VCC, the
V- output decays to GND. The decay time will
depend on the size of capacitors used for the
charge pump. Once in shutdown, the time
required to exit the shut down state and have
valid V+ and V- levels is typically 200µs.
The AUTO ON-LINE® circuit has two stages:
1) Inactive Detection
2) Accumulated Delay
The first stage, shown in Figure 28, detects an
inactive input. A logic HIGH is asserted on
RXINACT if the cable is disconnected or the
external transmitters are disabled. Otherwise,
RXINACT will be at a logic LOW. This circuit is
duplicated for each of the other receivers.
For easy programming, the STATUS can be
used to indicate DTR or a Ring Indicator signal.
Tying ONLINE and SHUTDOWN together
will bypass the AUTO ON-LINE® circuitry so
this connection acts like a shutdown input pin.
The second stage of the AUTO ON-LINE® circuitry, shown in Figure 29, processes all the
Date: 6/2/04
SP3223EB/3243EB +3.0V to +5.5V RS-232 Transceivers
17
© Copyright 2004 Sipex Corporation
normal usage. The transceiver IC receives most
of the ESD current when the ESD source is
applied to the connector pins. The test circuit for
IEC1000-4-2 is shown on Figure 31. There are
two methods within IEC1000-4-2, the Air
Discharge method and the Contact Discharge
method.
ESD TOLERANCE
The SP3223EB/3243EB series incorporates
ruggedized ESD cells on all driver output and
receiver input pins. The ESD structure is
improved over our previous family for more
rugged applications and environments sensitive
to electro-static discharges and associated
transients. The improved ESD tolerance is at
least +15kV without damage nor latch-up.
With the Air Discharge Method, an ESD voltage
is applied to the equipment under test (EUT)
through air. This simulates an electrically charged
person ready to connect a cable onto the rear of
the system only to find an unpleasant zap just
before the person touches the back panel. The
high energy potential on the person discharges
through an arcing path to the rear panel of the
system before he or she even touches the system.
This energy, whether discharged directly or
through air, is predominantly a function of the
discharge current rather than the discharge
voltage. Variables with an air discharge such as
approach speed of the object carrying the ESD
potential to the system and humidity will tend to
change the discharge current. For example, the
rise time of the discharge current varies with the
approach speed.
There are different methods of ESD testing
applied:
a) MIL-STD-883, Method 3015.7
b) IEC1000-4-2 Air-Discharge
c) IEC1000-4-2 Direct Contact
The Human Body Model has been the generally
accepted ESD testing method for semiconductors.
This method is also specified in MIL-STD-883,
Method 3015.7 for ESD testing. The premise of
this ESD test is to simulate the human body’s
potential to store electrostatic energy and
discharge it to an integrated circuit. The
simulation is performed by using a test model as
shown in Figure 30. This method will test the
IC’s capability to withstand an ESD transient
during normal handling such as in manufacturing
areas where the ICs tend to be handled frequently.
The Contact Discharge Method applies the ESD
current directly to the EUT. This method was
devised to reduce the unpredictability of the
ESD arc. The discharge current rise time is
constant since the energy is directly transferred
without the air-gap arc. In situations such as
hand held systems, the ESD charge can be directly
discharged to the equipment from a person already
holding the equipment. The current is transferred
on to the keypad or the serial port of the equipment
directly and then travels through the PCB and finally
to the IC.
The IEC-1000-4-2, formerly IEC801-2, is
generally used for testing ESD on equipment and
systems. For system manufacturers, they must
guarantee a certain amount of ESD protection
since the system itself is exposed to the outside
environment and human presence. The premise
with IEC1000-4-2 is that the system is required
to withstand an amount of static electricity when
ESD is applied to points and surfaces of the
equipment that are accessible to personnel during
R
RSS
R
RC
C
SW2
SW2
SW1
SW1
C
CSS
DC Power
Source
Device
Under
Test
Figure 30. ESD Test Circuit for Human Body Model
Date: 6/2/04
SP3223EB/3243EB +3.0V to +5.5V RS-232 Transceivers
18
© Copyright 2004 Sipex Corporation
Contact-Discharge Module
R
RSS
R
RC
C
RV
SW2
SW1
Device
Under
Test
CSS
DC Power
Source
RS and RV add up to 330
330Ω
Ω ffor
or IEC1000-4-2.
Figure 31. ESD Test Circuit for IEC1000-4-2
i➙
The circuit model in Figures 29 and 30 represent
the typical ESD testing circuit used for all three
methods. The CS is initially charged with the DC
power supply when the first switch (SW1) is on.
Now that the capacitor is charged, the second
switch (SW2) is on while SW1 switches off. The
voltage stored in the capacitor is then applied
through RS, the current limiting resistor, onto the
device under test (DUT). In ESD tests, the SW2
switch is pulsed so that the device under test
receives a duration of voltage.
30A
15A
0A
For the Human Body Model, the current limiting
resistor (RS) and the source capacitor (CS) are
1.5kΩ an 100pF, respectively. For IEC-1000-42, the current limiting resistor (RS) and the source
capacitor (CS) are 330Ω an 150pF, respectively.
t=0ns
t➙
t=30ns
Figure 32. ESD Test Waveform for IEC1000-4-2
The higher CS value and lower RS value in the
IEC1000-4-2 model are more stringent than the
Human Body Model. The larger storage capacitor
injects a higher voltage to the test point when
SW2 is switched on. The lower current limiting
resistor increases the current charge onto the test
point.
DEVICE PIN
TESTED
HUMAN BODY
MODEL
Air Discharge
Driver Outputs
Receiver Inputs
±15kV
±15kV
±15kV
±15kV
IEC1000-4-2
Direct Contact
±8kV
±8kV
Level
4
4
Table 4. Transceiver ESD Tolerance Levels
Date: 6/2/04
SP3223EB/3243EB +3.0V to +5.5V RS-232 Transceivers
19
© Copyright 2004 Sipex Corporation
PACKAGE: PLASTIC
DUAL–IN–LINE
(NARROW)
E1 E
D1 = 0.005" min.
(0.127 min.)
A1 = 0.015" min.
(0.381min.)
D
A = 0.210" max.
(5.334 max).
C
A2
B1
B
e = 0.100 BSC
(2.540 BSC)
Ø
L
eA = 0.300 BSC
(7.620 BSC)
ALTERNATE
END PINS
(BOTH ENDS)
DIMENSIONS (Inches)
Minimum/Maximum
(mm)
16–PIN
20–PIN
28–PIN
A2
0.115/0.195
(2.921/4.953)
0.115/0.195
(2.921/4.953)
0.115/0.195
(2.921/4.953)
B
0.014/0.022
(0.356/0.559)
0.014/0.022
(0.356/0.559)
0.014/0.022
(0.356/0.559)
B1
0.045/0.070
(1.143/1.778)
0.045/0.070
(1.143/1.778)
0.045/0.070
(1.143/1.778)
C
0.008/0.014
(0.203/0.356)
0.008/0.014
(0.203/0.356)
0.008/0.014
(0.203/0.356)
D
Date: 6/2/04
1.385/1.454
0.780/0.800
0.980/1.060
(19.812/20.320) (24.892/26.924) (35.17/36.90)
E
0.300/0.325
(7.620/8.255)
0.300/0.325
(7.620/8.255)
0.300/0.325
(7.620/8.255)
E1
0.240/0.280
(6.096/7.112)
0.240/0.280
(6.096/7.112)
0.240/0.280
(6.096/7.112)
L
0.115/0.150
(2.921/3.810)
0.115/0.150
(2.921/3.810)
0.115/0.150
(2.921/3.810)
Ø
0°/ 15°
(0°/15°)
0°/ 15°
(0°/15°)
0°/ 15°
(0°/15°)
SP3223EB/3243EB +3.0V to +5.5V RS-232 Transceivers
20
© Copyright 2004 Sipex Corporation
PACKAGE: PLASTIC SHRINK
SMALL OUTLINE
(SSOP)
E
H
D
A
Ø
e
A1
B
L
DIMENSIONS (Inches)
Minimum/Maximum
(mm)
Date: 6/2/04
16–PIN
20–PIN
24–PIN
28–PIN
A
0.068/0.078
(1.73/1.99)
0.068/0.078
(1.73/1.99)
0.068/0.078
(1.73/1.99)
0.068/0.078
(1.73/1.99)
A1
0.002/0.008
(0.05/0.21)
0.002/0.008
(0.05/0.21)
0.002/0.008
(0.05/0.21)
0.002/0.008
(0.05/0.21)
B
0.010/0.015
(0.25/0.38)
0.010/0.015
(0.25/0.38)
0.010/0.015
(0.25/0.38)
0.010/0.015
(0.25/0.38)
D
0.239/0.249
(6.07/6.33)
0.278/0.289
(7.07/7.33)
0.317/0.328
(8.07/8.33)
0.397/0.407
(10.07/10.33)
E
0.205/0.212
(5.20/5.38)
0.205/0.212
(5.20/5.38)
0.205/0.212
(5.20/5.38)
0.205/0.212
(5.20/5.38)
e
0.0256 BSC
(0.65 BSC)
0.0256 BSC
(0.65 BSC)
0.0256 BSC
(0.65 BSC)
0.0256 BSC
(0.65 BSC)
H
0.301/0.311
(7.65/7.90)
0.301/0.311
(7.65/7.90)
0.301/0.311
(7.65/7.90)
0.301/0.311
(7.65/7.90)
L
0.022/0.037
(0.55/0.95)
0.022/0.037
(0.55/0.95)
0.022/0.037
(0.55/0.95)
0.022/0.037
(0.55/0.95)
Ø
0°/8°
(0°/8°)
0°/8°
(0°/8°)
0°/8°
(0°/8°)
0°/8°
(0°/8°)
SP3223EB/3243EB +3.0V to +5.5V RS-232 Transceivers
21
© Copyright 2004 Sipex Corporation
PACKAGE: PLASTIC
SMALL OUTLINE (SOIC)
(WIDE)
E
H
D
A
Ø
e
B
A1
L
DIMENSIONS (Inches)
Minimum/Maximum
(mm)
Date: 6/2/04
28–PIN
A
0.090/0.104
(2.29/2.649)
A1
0.004/0.012
(0.102/0.300)
B
0.013/0.020
(0.330/0.508)
D
0.697/0.713
(17.70/18.09)
E
0.291/0.299
(7.402/7.600)
e
0.050 BSC
(1.270 BSC)
H
0.394/0.419
(10.00/10.64)
L
0.016/0.050
(0.406/1.270)
Ø
0°/8°
(0°/8°)
SP3223EB/3243EB +3.0V to +5.5V RS-232 Transceivers
22
© Copyright 2004 Sipex Corporation
PACKAGE: PLASTIC THIN
SMALL OUTLINE
(TSSOP)
DIMENSIONS
in inches (mm) Minimum/Maximum
Symbol
D
e
20 Lead
28 Lead
0.252/0.260 0.378/0.386
(6.40/6.60) (9.60/9.80)
0.026 BSC
(0.65 BSC)
0.026 BSC
(0.65 BSC)
e
0.126 BSC (3.2 BSC)
0.252 BSC (6.4 BSC)
1.0 OIA
0.169 (4.30)
0.177 (4.50)
0.039 (1.0)
0’-8’ 12’REF
e/2
0.039 (1.0)
0.043 (1.10) Max
D
0.033 (0.85)
0.037 (0.95)
0.007 (0.19)
0.012 (0.30)
0.002 (0.05)
0.006 (0.15)
(θ2)
0.008 (0.20)
0.004 (0.09) Min
0.004 (0.09) Min
Gage
Plane
0.010 (0.25)
(θ3)
0.020 (0.50)
0.026 (0.75)
(θ1)
1.0 REF
Date: 6/2/04
SP3223EB/3243EB +3.0V to +5.5V RS-232 Transceivers
23
© Copyright 2004 Sipex Corporation
PACKAGE: 32 PIN QFN
D
E
4X
Ø
º
A2
A
SEATING PLANE
A1
A3
D2
NX K
32 PIN QFN
JEDECMO220
( V H H D -4 )
A
Dimensions in
(mm)
NX L
MIN NOM MAX
0.80
0.90 1.00
A1
0
0.02
0.05
A2
0
0.65
1.00
A3
0.20 REF
D
5.00 BSC
E
5.00 BSC
0.50 BSC
e
b
0.18
0.25
Ø
0º
-
D2
3.50
3.65
3.80
3.80
3.50
3.65
L
0.35
0.40 0.45
K
0.20
-
NX K
0.30
e
14º
E2
N
E2
NX b
-
32
ND
8
NE
8
32 PIN QFN
Date: 6/2/04
SP3223EB/3243EB +3.0V to +5.5V RS-232 Transceivers
24
© Copyright 2004 Sipex Corporation
ORDERING INFORMATION
Part Number
Temperature Range
Package Types
SP3223EBCP .................................................... 0°C to +70°C -------------------------------------------- 20-pin PDIP
SP3223EBCA .................................................... 0°C to +70°C ------------------------------------------- 20-pin SSOP
SP3223EBCA/TR .............................................. 0°C to +70°C ------------------------------------------- 20-pin SSOP
SP3223EBCY .................................................... 0°C to +70°C ----------------------------------------- 20-pin TSSOP
SP3223EBCY/TR .............................................. 0°C to +70°C ----------------------------------------- 20-pin TSSOP
SP3223EBEP .................................................. -40°C to +85°C ------------------------------------------- 20-pin PDIP
SP3223EBEA .................................................. -40°C to +85°C ------------------------------------------ 20-pin SSOP
SP3223EBEA/TR ............................................ -40°C to +85°C ------------------------------------------ 20-pin SSOP
SP3223EBEY .................................................. -40°C to +85°C ---------------------------------------- 20-pin TSSOP
SP3223EBEY/TR ............................................ -40°C to +85°C ---------------------------------------- 20-pin TSSOP
SP3243EBCT .................................................... 0°C to +70°C ----------------------------------------- 28-pin WSOIC
SP3243EBCT/TR .............................................. 0°C to +70°C ----------------------------------------- 28-pin WSOIC
SP3243EBCA .................................................... 0°C to +70°C ------------------------------------------- 28-pin SSOP
SP3243EBCA/TR .............................................. 0°C to +70°C ------------------------------------------- 28-pin SSOP
SP3243EBCY ................................................... -0°C to +70°C ----------------------------------------- 28-pin TSSOP
SP3243EBCY/TR ............................................. -0°C to +70°C ----------------------------------------- 28-pin TSSOP
SP3243EBCR ................................................... -0°C to +70°C --------------------------------------------- 32-pin QFN
SP3243EBCR/TR ............................................. -0°C to +70°C --------------------------------------------- 32-pin QFN
SP3243EBET .................................................. -40°C to +85°C ---------------------------------------- 28-pin WSOIC
SP3243EBET/TR ............................................ -40°C to +85°C ---------------------------------------- 28-pin WSOIC
SP3243EBEA .................................................. -40°C to +85°C ------------------------------------------ 28-pin SSOP
SP3243EBEA/TR ............................................ -40°C to +85°C ------------------------------------------ 28-pin SSOP
SP3243EBEY .................................................. -40°C to +85°C ---------------------------------------- 28-pin TSSOP
SP3243EBEY/TR ............................................ -40°C to +85°C ---------------------------------------- 28-pin TSSOP
Available in lead free packaging. To order add "-L" suffix to part number.
Example: SP3243EBCY/TR = standard; SP3243EBCY-L/TR = lead free
/TR = Tape and Reel
Pack quantity is 1,500 for SSOP, TSSOP and WSOIC.
REVISION HISTORY
DATE
6/2/04
REVISION
A
DESCRIPTION
Replaced QFN package with QFN.
Corporation
ANALOG EXCELLENCE
Sipex Corporation
Headquarters and
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
FAX: (408) 935-7600
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the
application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
Date: 6/2/04
SP3223EB/3243EB +3.0V to +5.5V RS-232 Transceivers
25
© Copyright 2004 Sipex Corporation