SP3508 ® Evaluation Board Manual FEATURES ■ Easy Evaluation of SP3508 Multi-Protocol Transceiver ■ Eight (8) Drivers and Eight (8) Receivers ■ Current Mode V.35 Drivers ■ Internal Line or Digital Loopback ■ Internal Transceiver Termination Resistors for V.11 and V.35 ■ Termination Network Disable Option ■ Fast 20Mbps Differential Transmission Rates ■ Adheres to CTR1/CTR2 Compliancy Requirements ■ Interface modes: RS-232(V.28) X.21(V.11) RS-449/V.36(V.10&V.11) EIA-530(V.10&V.11) EIA-530A(V.10&V.11) V.35(V.35&V.28) DESCRIPTION The SP3508 Evaluation Board is designed to analyze the SP3508 multi-protocol transceivers. The evaluation board provides access points to all of the driver and receiver I/O pins so that the user can measure electrical characteristics and waveforms of each signal. The SP3508 Evaluation Board also includes a DB-25 serial port connector which is configured to a EIA-530 pinout. This allows easy connections to other DTE or DCE systems as well as network analyzers. The evaluation board also has a set of jumpers to allow the user to select the mode of operation and test the data latch feature. Furthermore, the SP3508 Evaluation Board provides the means to test both local and remote driver/receiver Loopback as well as evaluate the SP3508 in a DCE or DTE configuration. This Manual is split into sections to give the user the information necessary to perform a thorough evaluation of the SP3508. The Board Schematic and Layout section describes the I/O pins, the jumpers and the other components used on the evaluation board. The board schematic, layout diagram and DB-25 connector are also covered in the Board Schematic and Layout section. The Using the SP3508 Evaluation Board section details the configuration of the SP3508 evaluation board for parametric testing. Rev. 8/28/03 SP3508 Evaluation Board Manual 1 © Copyright 2003 Sipex Corporation Figure 1 V AV BNC VCC CC AGND 2 1 123 JP22 1 23 JP23 12 3 JP24 12 3 JP25 JP21 12 3 CC 2-4 Input frin external source V 1-2 2-3 Input toVCC JP20 123 R2 50Ω JP5 TTL Jumper Configuration 1 Input to GND Description 4 AC INPUT JP52 Jumper 1 2 3 JP51 1 2 GND CC GND JP50 2 1 ttl Vdd CVdd 1uF GNDTP V CC RTS DTR RTS ST TXCE DSR CTS LL RL 43 42 41 RI TM_OUT 45 46 D2 D2 latch termoff /D_LATCH TERM_OFF TM RI DCD_DTE DSR CTS TxC LOOPBACK D0 18 D0 D1 19 D1 20 D2 LOOPBACK 30 /LOOPBACK D1 D0 21 22 LATCH TERM_OFF TM RI RxC RxD LL RL DCD_DCE DTR RTS ST TxCE TxD VDD C1+ C1- VSS1 60 GNDV10 40 39 38 37 36 35 34 33 32 31 76 DCD_DTE 44 DSR CTS TXC JP9 RXC RXD LL RL DCE_DCE DCE_DCE DTR DCD_DTE TP28 TP27 TP26 TP25 TP24 TxCE ST TP22 TP23 TXD VDD C1 1uF + C1+ 74 TxD + TP21 + 68 C1- 70 CVss1 1uF C3- ST(a) 81 83 87 67 rla SDE TTE STE RSE TRE RRCE RLEN /LLEN /RDEN /RTEN /TxCEN /CSEN /DMEN /RRTEN /ICEN TMEN TM(a) IC RRT(b) RRT(a) DM(b) DM(a) CS(b) CS(a) TxC(b) TxC(a) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 64 63 61 62 58 59 56 57 53 55 51 sden tten sten rsen tren rrcen rlen llen rden rten txcen csen dmen rrten icen tmen TM_IN ic rrtb rrta dmb dma csb csa txcb txca rtb RT(a) RT(b) rdb rta 49 52 RD(b) lla rda 65 rrcb rrca trb tra rsb rsa stb sta ttb tta sdb sda VSS 50 RD(a) RL(a) 77 79 RRC(b) RRC(a) 85 TR(b) TR(a) RS(b) RS(a) 91 95 89 TT(b) 93 97 27 C2 1uF 1 2 C2- 72 C2+ 69 TT(a) ST(b) C3 1uF 1+ 26 C1-1 2 24 C1+1 99 LL(a) VSS2 C2- C2+ C3+ 92 96 28 SD(b) SD(a) Part Reference GND 57 4 15 0 48 1 24 5 77 8 88 21 18 RL_A Vss_2 CVss2 1uF P1-18 LL_A P1-21 + IC_IN Jumper 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 V CC VCC R R T _ B R R C _ B R R T_ A R R C _ A D M _ B T R _ B D M _ A T R _ A T M _ a C S _ B R S _ B C S _ A R S _ A 1 1 1 EIA-530A RS-449 X.21 1 0 0 1 1 0 0 0 0 V.35 EIA-530 RS-232 1 D0 1 MODE SHUTDOWN D1 0 1 0 1 0 1 1 JP3 2 1 3 JP2 2 1 3 D2 DECODER RT_B RT_A RD_B RD_A ST_B ST_A TT_B TT_A SD_B SD_A 11 15 P1-15 P1-24 P1-11 2-3 2-3 2-3 2-3 2-3 1-2 1-2 1-2 1-2 1-2 1-2 1-2 1-2 JP34 JP35 JP36 JP37 JP38 JP39 JP40 JP41 /LLEN RLEN RRCEN TREN RSEN STEN TTEN SDEN 2-3 2-3 2-3 2-3 2-3 2-3 1-2 1-2 1-2 JP31 JP32 JP33 /TxCEN /RTEN /RDEN 2-3 2-3 2-3 2-3 2-3 2-3 1-2 1-2 1-2 1-2 1-2 1-2 JP28 JP29 JP30 JP25 JP26 JP27 2-3 2-3 2-3 TP41 TP42 TP39 TP40 TP37 TP38 TP35 TP36 VCC TP57 TP58 TP55 TP56 TP53 TP54 TP51 TP52 TP49 TP50 TP47 TP48 TP45 TP46 TP43 TP44 1 2 3 Signal VCC 2-3 2-3 TP31 TP32 JP1 JP1 JP2 JP2 JP3 JP3 JP4 JP4 Jumper TP33 TP34 Jumper P1-1 /RRTEN /DMEN /CSEN /Loopback TMEN /ICEN GND 1-2 1-2 GND 1-2 1-2 1-2 Jumper JP20 JP21 P1-25 P1-10 P1-22 P1-8 P1-6 P1-13 P1-5 P1-9 P1-17 P1-16 P1-3 R1 50Ω P1-20 P1-23 P1-19 P1-4 P1-12 JP22 JP23 JP24 25 8 10 22 6 5 13 17 9 3 16 23 20 19 4 12 P1-2 P1-14 /D_Latch D0 D1 D2 Signal Term_off JP4 2 1 3 JP1 2 1 3 24 14 2 1 5) C1, C2, C3, CVdd, CVss1 and CVss2 footprint are size 1812 and are to be as close the the socket pins as 2 possible. 3 6) C7 is footprint 2220 and is to be placed where the power supply is attached to the board. Signal to be 7) Test points are MilMax part # 0300-1-15-01-4727100 0.040" round post. accessed by DB25 8) JP1, JP2 ,JP3, JP4 and JP20 - JP41 are 3 pin 0.100" headers with 0.025" square post STa TxCa 9) JP5, JP9, JP50 and JP51 are 2 pin 0.100" headers with 0.25" square post STb 10) P1 is 25 pin male right angle D-SUB connector TxCb RRTa 11) SP3508 is a 100 pin LQFP RRCa 12) R1 and R2 are 1/8 watt 50 ohm axial lead resistor RRTb 13) U4 is Pomona Type 4788 BNC right angle female PC mount RRCb 2) Add Test Point for VCC and GND for attachment of a power supply. 3) Scope probe jack is Berg part # 33JR135-1 4) VDD (pin 76) and VSS1 (Pin 68) are to be routed as directly as possible to CVdd and CVss1 respectively. 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 JP26 JP34 CC JP27 JP35 V JP28 JP36 C7 1uF JP37 0 26 048 09 88 999 12 JP29 NOTES 1) Avoid parrallel traces on receiver inputs JP33 78 73 66 48 23 JP32 VCC JP30 JP38 Figure 1. SP3508 Schematic JP31 JP39 2 JP40 SP3508 Evaluation Board Manual JP41 Rev. 8/28/03 © Copyright 2003 Sipex Corporation Jumper Config 1-2 2-3 1-2 2-3 1-2 2-3 1-2 2-3 SP508 EVALUATION BOARD BOARD LAYOUT 1. The SP3508 Evaluation Board has been designed to easily and conveniently provide access to all inputs and outputs under test. 6. Also located on the SP3508 evaluation board are six 1uf charge pump capacitors, a 1µF bypass capacitor for VCC and two 50Ω termination resistors. 2. Figure 1 is a schematic of the evaluation board. The schematic shows the location of the driver and receiver access points as well as the Jumpers, VCC, GND and the DB-25 Connector. 7. 1 Pomona BNC female connector is mounted on the board to provide input signal for evaluation. 8. Figure 2 shows a RS-232 & EIA530 DB25 Connector. 3. Figure 3 to Figure 6 shows the layout of the SP3508 Evaluation Board. 9. Table 1 shows the pinout of the DB-25 connector used to connect to a communication analyzer such as the TTC Firebird 6000. 4. I/O Pinouts The SP3508 Evaluation Board has been designed to easily and conveniently provide access to all inputs and outputs to the device under test. Each Driver has probe points for the inputs and outputs. Each Receiver has probe points for the inputs and outputs. 1 5. At the left of the board is a set of jumpers. Each driver and receiver has its own individual enable pin. This set of jumpers controls the enabling and disabling of each driver of receiver. Another set of jumpers is to configure the 3 bit decoder, to enable/ disable loopback, to enable/disable latch and to enable/disable term_off functions. In addition, JP1 - JP4 allow the user to choose which signals the user can access through the DB-25 connector. JP5 allows the user to set the driver input to GND, VCC or external source. Rev. 8/28/03 14 13 25 Figure 2. RS-232 & EIA530 Connector (ISO 2110), DTE Connector σ DB-25 Male, DCE Connector σ DB-25 Female SP3508 Evaluation Board Manual 3 © Copyright 2003 Sipex Corporation Transmitter Outputs Transmitter and Receiver Enable Pins Receiver Inputs Receiver Outputs Transmitter Inputs Note: All six charge pump caps are located next to the DUT. Control pins (D0,D1, D2), / LOOPBACK, / D_LATCH, and TERMOFF are also included. Figure 3. SP3508 Evaluation Board Layout Rev. 8/28/03 SP3508 Evaluation Board Manual 4 © Copyright 2003 Sipex Corporation Figure 4. SP3508 Evaluation Board Ground Plane Figure 5. SP3508 Evaluation Board VCC Plane Rev. 8/28/03 SP3508 Evaluation Board Manual 5 © Copyright 2003 Sipex Corporation Figure 6. SP3508 Evaluation Board Layout Bottom Layer Rev. 8/28/03 SP3508 Evaluation Board Manual 6 © Copyright 2003 Sipex Corporation TABLE 1. EIA-232 Signal Name Shield Transmitted data Received Data EIA-530 EIA-449 V.35 X.21 source Mnemonic Pin Mnemonic Pin Mnemonic Pin Mnemonic Pin Mnemonic Pin — — 1 — 1 — 1 — A — 1 DTE BA 2 BA(A) 2 SD(A) 4 103 P Circuit T(A) 2 BA(B) 14 SD(B) 22 103 S Circuit T(B) 9 BB(A) 3 RD(A) 6 104 R Circuit R(A) 4 BB(B) 16 RD(B) 24 104 T Circuit R(B) 11 RS(A) 7 105 C Circuit C(A) 3 Circuit C(B) 10 106 D Circuit I(A) 5 Circuit I(B) 12 107 E 108 H* Circuit G 8 Circuit S(A) 6 DCE BB 3 Request To Send DTE CA 4 CA(A) 4 CA(B) 19 RS(B) 25 Clear To Send DCE CB 5 CB(A) 5 CS(A) 9 CB(B) 13 CS(B) 27 DCE Ready (DSR) DCE CC 6 CC(A) 6 DM(A) 11 CC(B) 22 DM(B) 29 DTE Ready (DTR) DTE CD 20 CD(A) 20 TR(A) 12 CD(B) 23 TR(B) 30 Signal Ground — AB 7 AB 7 SG 19 102 B Recv. Line Sig. DCE CF 8 CF(A) 8 RR(A) 13 109 F CF(B) 10 RR(B) 31 DCE DB 15 DB(A) 15 ST(A) 5 114 Y DB(B) 12 ST(B) 23 114 AA Circuit S(B) 13 DTE RL 17 DD(A) 17 RT(A) 8 115 V Circuit B(A)** 7 DD(B) 9 RT(B) 26 115 X Circuit B(B)** 14 DCE DD 18 LL 18 LL 10 141 L* Det. (DCD) Trans. Sig. Elemt. Timing Recv. Sig. Elemt. Timing Local Loopback Remote Loopback DTE LL 21 RL 21 RL 14 140 N* Ring Indicator DCE CE 22 — — — — 125 J* Trans. Sig. DTE DA 24 Elemt. Timing Test Mode DCE TM 25 DA(A) 24 TT(A) 17 113 U* Circuit X(A)** 7 DA(B) 11 TT(B) 35 113 W* Circuit X(B)** 14 TM 25 TM 18 142 NN* * Optional signals ** Only one of the two x.21 signals, Circuit B or X, can be implemented and active at one time. Rev. 8/28/03 SP3508 Evaluation Board Manual 7 © Copyright 2003 Sipex Corporation USING THE EVALUATION BOARD Recommended Equipment • Oscilloscope • Digital multimeter • Signal Generator capable of >40MHz • Communications Analyzer (such as Firebird 6000) enable pin is not connected or floating. Set the appropriate jumper to enable the driver under test. Once the power is on and the driver input receives a signal, the driver outputs can be analyzed with an oscilloscope or a digital multimeter. Mode selection can be performed at any time by changing the jumper settings for the 3 bit decoder (D0-D2). The appropriate termination for the driver under test can be added to driver output and tied to the ground bus. Parametric Evaluation Located on the board are two pins identified as VCC and SIGNAL GND. Connect VCC to a +3.3V DC supply. If possible limit the supply current to 0.5 to 1.0 Amps. Be sure to have power off when connecting the supply to the board. Receiver Evaluation The SP3508 receivers have internal termination appropriate for V.35 and RS-422 modes (refer to the SP3508 datasheet for more detail on the receiver termination). This is activated when the receiver is set to act as a V.11 receiver (see Table 3) and the TERM_OFF pin is logic “0”. Each receiver has a fail-safe feature that outputs a logic “1” when the receiver is open, terminated but open, or shorted together. There is an individual enable line for each receiver that can be used to tri-state the driver. Each enable line has an internal pull up or pull down to insure the receiver is enabled if the enable pin is not connected or floating. Set the appropriate jumper to enable the receiver under test. The mode selection can be performed at any time after power up by changing the state of the 3 bit decoder (D0D2). To evaluate the receiver the appropriate input signal needs to be applied. This can be accomplished by providing a signal from an external source or use the SP3508 driver output and jumper it to the receiver input. For single ended receivers, tie the active driver output to the active receiver input. For differential drivers, tie the “A” driver output to the “A” receiver input and the “B” driver output to the “B” receiver input. Using the TTL signal on the driver input will allow the user to analyze receiver levels and timing characteristics. SP3508 Decoder The SP3508 uses a 3 bit decoder to designate the protocol selected. There is also a decoder latch pin available. Table 2 and Table 3 show the decoder modes for the driver and receiver. Upon power up the latch pin needs to be in a transparent state (logic low or floating) or the SP3508 will be in an unknown state. Note that D0, D1, and D2 set as logic high will put the device shutdown overriding all individual enable/ disable lines and the drivers outputs and receiver inputs will tri-state. In shutdown mode the termination resistors also disconnect. Driver Evaluation Each driver has an internal pull-up; therefore, it is in a defined state when the input is open. Connect a system clock or a signal generator with a TTL-level output and the appropriate frequency within the acceptable range of the driver to the input BNC connector. Set the jumper to the desired driver input to be evaluated. There is an individual enable line for each driver that can be used to tri-state the driver. Each enable line has an internal pull up or pull down to insure the driver is enabled if the Rev. 8/28/03 SP3508 Evaluation Board Manual 8 © Copyright 2003 Sipex Corporation USING THE EVALUATION BOARD: Continued Driver/Receiver Remote Loopback The following example uses the ST driver looped back into the TxC receiver. Use the 3 bit decoder to configure the SP3508 for the desired protocol. Connect a jumper cable between the ST(a) pin and the TxC(a) pin. If your mode select is set for a differential driver/receiver, then also connect a jumper cable between the ST(b) pin and the TxC(b) pin. The next step is to connect a signal generator to the ST input pin through BNC input connector. The signal generator output must be a TTL-level output at a frequency within the acceptable range of the driver mode under test. Be sure that the jumper settings of STEN signal and TxCEN signal are set to enable the ST driver and TxC receiver. The driver outputs are now connected back to the receiver inputs so that the driver input to receiver output can be examined. This configuration is similar for all other drivers. • Set the /TxCEN and /RRTEN to Logic “1”. This will disable the TxC and RRT receiver inputs. (Refer to the Jumper Setting Guide in the next section) • Use an external wire to tie the ST driver outputs to the TxC Receiver inputs. • Use an external wire to tie the RRC driver outputs to the RRT receiver inputs. • To enable a DTE configuration, set the STEN and RRCEN to Logic “1”. Be sure the TxC and RRT receivers are disabled by setting the /TxCEN and /RRTEN to Logic “1”. (Refer to the Jumper Setting Guide in the next section) • To enable a DCE configuration, set the / TxCEN and /RRTEN to Logic “0”. Be sure to disable the ST and RRC driver outputs by setting the STEN and RRCEN to Logic “0”. (Refer to the Jumper Setting Guide in the next section) System Level Evaluation • Use DB-25 Connector if the evaluation board is configured as a DTE for EIA-530 pinout. In order to connect to other DCE equipment or network analyzers ( i.e. the TTC Firebird 6000A), the RxC receiver output must be looped back to the TxCE driver input. The RxD output can also be looped back to the TxD input. • If connecting the evaluation board to a microcontroller such as the Motorola MC68360, jumper wires of the driver inputs and receiver outputs must connect to the uC’s appropriate pins. Driver/Receiver Local Loopback The SP3508 has the ability to provide an internal loopback. This feature is invoked by a logic “0” on the /LOOPBACK pin. The driver input and receiver output characteristics adhere to the appropriate specifications outlined in the datasheet under loopback conditions. The /LOOPBACK pin has an internal pull-up resistor so that the SP3508 defaults to normal operation during powerup or if the pin is left floating. DCE DTE selectable configuration • Configure the decoder for the desired mode. • The SP3508 evaluation board has jumper setup to allow for the evaluation of a selectable DCE DTE configuration. • Set the STEN and RRCEN to Logic “0”. This will disable the ST and RRC driver outputs. (Refer to the Jumper Setting Guide in the next section) Rev. 8/28/03 SP3508 Evaluation Board Manual 9 © Copyright 2003 Sipex Corporation TABLE 2 Driver Output Pin V.35 Mode EIA-530 Mode RS-232 EIA-530A RS-449 X.21 Mode (V.28) Mode Mode (v.36) Mode (v.11) Shutdown Suggested Signal MODE (D0,D1,D2) 001 010 011 100 101 110 111 T1OUT(a) V.35 V.11 V.28 V.11 V.11 V.11 High-Z T1OUT(b) V.35 V.11 High-Z V.11 V.11 V.11 High-Z TxD(b) T2OUT(a) V.35 V.11 V.28 V.11 V.11 V.11 High-Z TxCE(a) T2OUT(b) V.35 V.11 High-Z V.11 V.11 V.11 High-Z TxCE(b) T3OUT(a) V.35 V.11 V.28 V.11 V.11 V.11 High-Z TxC_DCE(a) T3OUT(b) V.35 V.11 High-Z V.11 V.11 V.11 High-Z TxC_DCE(b) T4OUT(a) V.28 V.11 V.28 V.11 V.11 V.11 High-Z RTS(a) T4OUT(b) High-Z V.11 High-Z V.11 V.11 V.11 High-Z RTS(b) T5OUT(a) V.28 V.11 V.28 V.10 V.11 V.11 High-Z DTR(a) T5OUT(b) High-Z V.11 High-Z High-Z V.11 V.11 High-Z DTR(b) T6OUT(a) V.28 V.11 V.28 V.11 V.11 V.11 High-Z DCD_DCE(a) T6OUT(b) High-Z V.11 High-Z V.11 V.11 V.11 High-Z DCD_DCE(b) T7OUT(a) V.28 V.10 V.28 V.10 V.10 High-Z High-Z RL T8OUT(a) V.28 V.10 V.28 V.10 V.10 High-Z High-Z LL V.35 Mode EIA-530 Mode Shutdown Suggested Signal TxD(a) TABLE 3 Receiver Input Pin RS-232 EIA-530A RS-449 X.21 Mode (V.28) Mode mode (v.36) Mode (v.11) MODE (D0,D1,D2) 001 010 011 100 101 110 111 R1IN(a) V.35 V.11 V.28 V.11 V.11 V.11 High-Z R1IN(b) V.35 V.11 High-Z V.11 V.11 V.11 High-Z RxD(b) R2IN(a) V.35 V.11 V.28 V.11 V.11 V.11 High-Z RxC(a) R2IN(b) V.35 V.11 High-Z V.11 V.11 V.11 High-Z RxC(b) R3IN(a) V.35 V.11 V.28 V.11 V.11 V.11 High-Z TxC_DTE(a) R3IN(b) V.35 V.11 High-Z V.11 V.11 V.11 High-Z TxC_DTE(b) R4IN(a) V.28 V.11 V.28 V.11 V.11 V.11 High-Z CTS(a) R4IN(b) High-Z V.11 High-Z V.11 V.11 V.11 High-Z CTS(b) R5IN(a) V.28 V.11 V.28 V.10 V.11 V.11 High-Z DSR(a) R5IN(b) High-Z V.11 High-Z High-Z V.11 V.11 High-Z DSR(b) R6IN(a) V.28 V.11 V.28 V.11 V.11 V.11 High-Z DCD_DTE(a) R6IN(b) High-Z V.11 High-Z V.11 V.11 V.11 High-Z DCD_DTE(b) R7IN(a) V.28 V.10 V.28 V.10 V.10 High-Z High-Z RI R8IN(a) V.28 V.10 V.28 V.10 V.10 High-Z High-Z TM RxD(a) JUMPER SETTING GUIDE JP52 allows the user to set the driver input to GND, VCC or external source. TABLE 4. JP52 JUMPER SETTING 1 2 3 4 Figure 7. JP52 Jumper Configuration. Rev. 8/28/03 Description Jumper Configuration Input to GND 1-2 Input to VCC 2-3 Input from External Source 2-4 SP3508 Evaluation Board Manual 10 © Copyright 2003 Sipex Corporation Figure 8 shows 3-pin jumper configuration and Table 5 describes the fuctionalities of each jumper setting configuration. 1 3 2 Figure 8. 3-Pin Jumper Configuration TABLE 5. SP3508 LOGIC JUMPER SETTING Switch D0 D1 D2 LOOPBACK TERM_OFF D_LATCH SDEN TTEN STEN RSEN TREN RRCEN RLEN /LLEN /RDEN /RTEN /TXCEN /CSEN /DMEN /RRTEN /ICEN Jumper JP22 JP23 JP24 JP25 JP20 JP21 JP41 JP40 JP39 JP38 JP37 JP36 JP35 JP34 JP33 JP32 JP31 JP30 JP29 JP28 JP27 LOGIC 1 VCC (2-3) VCC (2-3) VCC (2-3) VCC (2-3) VCC (2-3) VCC (2-3) VCC (2-3) VCC (2-3) VCC (2-3) VCC (2-3) VCC (2-3) VCC (2-3) VCC (2-3) VCC (2-3) VCC (2-3) VCC (2-3) VCC (2-3) VCC (2-3) VCC (2-3) VCC (2-3) VCC (2-3) LOGIC 2 GND (1-2) GND (1-2) GND (1-2) GND (1-2) GND (1-2) GND (1-2) GND (1-2) GND (1-2) GND (1-2) GND (1-2) GND (1-2) GND (1-2) GND (1-2) GND (1-2) GND (1-2) GND (1-2) GND (1-2) GND (1-2) GND (1-2) GND (1-2) GND (1-2) DECODER DECODER DECODER Logic 0 indicates SP508 is in LOOPBACK mode Logic 1 internal termination is disables Logic 0 Latch is disabled Logic 1 TXD driver is enabled Logic 1 TXCE driver is enabled Logic 1 ST driver is enabled Logic 1 RTS driver is enabled Logic 1 DTR driver is enabled Logic 1 DCD_DCE driver is enabled Logic 1 SD driver is enabled Logic 0 LL driver is enabled Logic 0 RXD receiver is enabled Logic 0 RXT receiver is enabled Logic 0 TXC receiver is enabled Logic 0 CTS receiver is enabled Logic 0 DSR receiver is enabled Logic 0 DCD_DTE receiver is enabled Logic 0 RI receiver is enabled TMEN JP26 VCC (2-3) GND (1-2) Logic 1 TM receiver is enabled JP1 - JP4 are set of jumpers that the user can select which signals to be accessed by DB25. Figure 9 shows 3-pin jumper configuration and Table 5 describes the signal to be accessed by DB25 per its configuration. TABLE 6. SP3508 JUMPER SETTINGS Signal to be accessed by DB25 1 2 STa TxCa STb TxCb RRTa RRCa RRTb RRCb 3 Figure 9. 3-Pin Jumper Configuration Rev. 8/28/03 SP3508 Evaluation Board Manual 11 Jumper Jumper Configuration JP1 JP1 JP2 JP2 JP3 JP3 JP4 JP4 1-2 2-3 1-2 2-3 1-2 2-3 1-2 2-3 © Copyright 2003 Sipex Corporation SP3508 Pin Designation Pin Number Pin Name 1 GND Signal Ground Description Pin Number Pin Name 51 RT(B) Description 2 SDEN TxD Driver Enable Input 52 RT(A) RxT Non-Inverting Input 3 TTEN TxCE Driver Enable Input 53 TxC(B) TxC Non-Inverting Input RxT Non-Inverting Input 4 STEN ST Driver Enable Input 54 GND 5 RSEN RTS Driver Enable Input 55 TxC(A) TxC Inverting Input Signal Ground 6 TREN DTR Driver Enable Input 56 CS(B) CTS Non-Inverting Input 7 RRCEN DCD Driver Enable Input 57 CS(A) CTS Inverting Input 8 RLEN RL Driver Enable Input 58 DM(B) DSR Non-Inverting Input 9 LLEN LL Driver Enable Input 59 DM(A) DSR Inverting Input 10 RDEN RxD Receiver Enable Input 60 GNDV10 11 RTEN RxT Receiver Enable Input 61 RRT(B) DCDDTE Non-Inverting Input 12 TxCEN TxC Receiver Enable Input 62 RRT(A) DCDDTE Non-Inverting Input 13 CSEN CTS Receiver Enable Input 63 IC 14 DMEN DSR Receiver Enable Input 64 TM(A) TM Receiver Input 15 RRTEN DCDDTE Receiver Enable Input 65 LL(A) LL Driver Output Power Supply Input V.10 Rx Reference Node RI Receiver Input 16 ICEN RI Receiver Enable Input 66 VCC 17 TMEN TM Receiver Enable Input 67 RL(A) RL Driver Output 18 D0 Mode Select Input 68 VSS1 -2xVCC Charge Pump Output 19 D1 Mode Select Input 69 C2N Charge Pump Capacitor 20 D2 Mode Select Input 70 C1N Charge Pump Capacitor 21 D_LATCH Decoder Latch Input 71 GND Signal Ground 72 C2P Charge Pump Capacitor 22 TERM_OFF Termination Disable Input 23 VCC Power Supply Input 73 VCC Power Supply Input 24 C3P Charge Pump Capacitor 74 C1P Charge Pump Capacitor 25 GND Signal Ground 75 GND Signal Ground 26 C3N Charge Pump Capacitor 76 VDD 2xVCC Charge Pump Output 27 VSS2 Minus VCC 77 RRC(B) DCDDCE Non-Inverting Output 28 AGND Signal Ground 78 VCC 29 AVCC Power Supply Input 79 RRC(A) 30 LOOPBACK Loopback Mode Enable Input 31 TxD 32 TxCE 33 ST Power Supply Input DCDDCE Inverting Output 80 GND Signal Ground TxD Driver TTL Input 81 RS(A) RTS Inverting Output TxCE Driver TTL Input 82 VCC Power Supply Input ST Driver TTL Input 83 RS(B) RTS Non-Inverting Output 34 RTS RTS Driver TTL Input 84 GND Signal Ground 35 DTR DTR Driver TTL Input 85 TR(A) DTR Inverting Output 36 DCD_DCE DCDDCE Driver TTL Input 86 VCC Power Supply Input 37 RL RL Driver TTL Input 87 TR(B) DTR Non-Inverting Output 38 LL LL Driver TTL Input 88 GND Signal Ground 39 RxD RxD Receiver TTL Output 89 ST(A) ST Inverting Output 40 RxC RxC Receiver TTLOutput 90 VCC Power Supply Input 41 TxC TxC Receiver TTL Output 91 ST(B) ST Non-Inverting Output 42 CTS CTS Receiver TTL Output 92 GND Signal Ground 43 DSR DSR Receiver TTL Output 93 TT(A) TxCE Inverting Output 44 DCD_DTE DCDDTE Receiver TTL Output 94 VCC Power Supply Input 45 RI TI Receiver TTL Output 95 TT(B) TxCE Inverting Output 46 TM TM Receiver TTL Output 96 GND Signal Ground 47 GND Signal Ground 97 SD(A) TxD Inverting Output 48 VCC Power Supply Input 98 VCC 49 RD(B) RXD Non-Inverting Input 99 SD(B) 50 RD(A) RXD Inverting Input 100 VCC Rev. 8/28/03 SP3508 Evaluation Board Manual 12 Power Supply Input TxD Non-Inverting Output Power Supply Input © Copyright 2003 Sipex Corporation ORDERING INFORMATION Model TEMPERATURE Package SP3508CF ........................................................ 0°C TO +70°C ..................................... 100-pin JEDEC LQFP SP508CEB ....................................................... 0°C TO +70°C ................................. SP508 Evaluation Board Corporation ANALOG EXCELLENCE Sipex Corporation Headquarters and Sales Office 233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600 Sales Office 22 Linnell Circle Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: [email protected] Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Rev. 8/28/03 SP3508 Evaluation Board Manual 13 © Copyright 2003 Sipex Corporation