SS6383B(G) 3A DDR Termination Regulator FEATURES DESCRIPTION Source and sink current capability of 3A The SS6383B linear regulator is designed to provide 3A source and sink current while regulating an output voltage to within 45mV. Low output voltage offset, ±20mV High accuracy output voltage at full-load VOUT adjustable by external resistors The SS6383B converts voltage supplies ranging from 1.6V to 6V into an output voltage that is set by two external voltage-divider resistors. It provides an excellent voltage source for active termination schemes for high-speed transmission lines such as those seen in highspeed memory buses. Low external component count Current limit protection Thermal protection SO-8, TO-252-5 and TO-263-5 packages APPLICATIONS Mother Boards Graphic Cards DDR Termination Voltage Supply - supports DDR1 (1.25VTT), DDR2 (0.9VTT), and meets JEDEC SSTL-2 and SSTL-3 term. specifications The built-in current-limiting in source and sink mode, together with thermal shutdown, provides maximum protection to the SS6383B against fault conditions. TYPICAL APPLICATION CIRCUIT 1 VIN=2.5V + CIN 470µF VOUT 2 3 VCNTL=3.3V VIN + GND VCNTL VREF SS6383BCE5 CCNTL 47µF 5 4 VOUT R1 100K COUT 220µF R2 C1 100K 100pF + EN SSM7002EN This device is available with Pb-free lead finish (second-level interconnect) as SS6383BGxx 11/07/2004 Rev.2.01 www.SiliconStandard.com 1 of 8 SS6383B(G) ORDERING INFORMATION PIN CONFIGURATION SS6383BXXX XX TO-263-5 Packing TR: Tape and reel Package type CM5: TO-263-5, commercial CE5 : TO-252-5, commercial CS : SO-8, commercial GM5 : TO-263-5, commercial, Pb-free GE5 : TO-252-5, commercial, Pb-free GS : SO-8, commercial, Pb-free Example: SS6383BGE5TR in TO-252-5 package, with Pb-free lead finish, shipped on tape and reel FRONT VIEW 1: VIN 2: GND 3. VCNTL 4. VREF 5: VOUT 12345 TO-252-5 TOP VIEW 1: VIN 2: GND 3. VCNTL 4. VREF 5: VOUT 1234 5 SO-8 TOP VIEW VIN 1 8 VCNTL GND 2 7 VCNTL VREF 3 6 VCNTL VOUT 4 5 VCNTL ABSOLUTE MAXIMUM RATINGS Supply Voltage -0.4V to 7V Operating Temperature Range -40°C~85°C -65°C ~150°C Storage Temperature Range 260°C Lead Temperature (Solder, 10sec) Thermal Resistance θJC TO-263 3°C /W TO-252 12.5°C /W SO-8 40°C /W Thermal Resistance θJA TO-263 60°C /W (Assume no ambient airflow, no heatsink) TO-252 100°C /W SO-8 160°C /W Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. 11/07/2004 Rev.2.01 www.SiliconStandard.com 2 of 8 SS6383B(G) TEST CIRCUIT 1 2.5V VIN VOUT 2 3 3.3V 5 VOUT + GND VREF 4 1.25V COUT 10µF VCNTL SS6383B ELECTRICAL CHARACTERISTICS (VCNTL=3.3V, VIN=2.5V, VREF=0.5VIN, COUT=10µF, TA=25°C, unless otherwise specified) PARAMETER SYMBOL MIN. TYP. MAX. VIN 1.6 2.5 6 power on and off sequences VCNTL 3.0 3.3 6 Output Voltage IOUT = 0mA VOUT Output Voltage Offset IOUT = 0mA VOS Input Voltage (DDR1/2) Load Regulation (DDR1/2) TEST CONDITIONS Keep VCNTL≥VIN during IOUT =0.1mA ~ +3A IOUT =0.1mA ~ -3A Quiescent Current VREF<0.2V, VOUT = OFF Operating Current of VCNTL No load VREF Bias Current V VREF -20 V 20 mV 35 45 35 45 IQ 8 30 µA ICNTL 3 10 mA 1 µA 6.5 A ∆VLOR VREF=1.25V Current Limit UNIT mV 0 IIL 3.2 4 TSD 125 150 °C 30 °C THERMAL PROTECTION Thermal Shutdown Temperature Thermal Shutdown Hysteresis 3.3V≤VCNTL≤5V Guaranteed by design SHUTDOWN SPECIFICATIONS Shutdown Threshold Output ON (VREF=0V 1.25V) Output OFF (VREF=1.25V 0V) 0.8 V 0.2 Note 2: VOS is the voltage measurement, which is defined as the difference between VOUT and VREF. Note 3: Load regulation is measured at constant junction temperature, using pulse testing with a low ON time. Note 4: Current limit is measured by pulsing a short time. Note 5: To operate the system safely; V CNTL must be always greater than VIN. Note 6: Specifications are guaranteed by Statistical Quality Controls (SQC), and not production tested, within the operating temperature range of -40°C to 85°C. Note 7: DDR2 is not supported in the TO-263 package. 11/07/2004 Rev.2.01 www.SiliconStandard.com 3 of 8 SS6383B(G) TYPICAL PERFORMANCE CHARACTERISTICS 0.48 0.52 VCNTL=3.3V Threshold Voltage (V) Threshold Voltage (V) 0.52 VIN=2.5V 0.44 0.40 0.36 VCNTL=5V 0.48 VIN=2.5V 0.44 0.40 0.36 0.32 0.32 -20 0 20 40 60 80 Temperature (°C) 100 40 120 20 0 20 40 60 80 100 120 Temperature (°C) Fig. 2 Turn On Threshold vs. Temp. Fig. 1 Turn-On Threshold vs. Temp. 4.5 4.0 3.5 3.0 VCNTL=3.3V VIN=2.5V VREF=1.25V No Load Sourcing Current (A) Output Voltage Offset (mV) 6 2.5 2.0 1.5 1.0 VCNTL=3.3V VIN=2.5V VREF=1.25V 5 4 3 0.5 0.0 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Fig. 3 Output Voltage Offset vs. Temp. 2 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Fig. 4 Current-Limit (Sourcing) vs. Temp. Sinking Current (A) 6 VCNTL=3.3V VIN=2.5V, VREF=1.25V VCNTL=3.3V VIN=2.5V VREF=1.25V 5 VOUT, 50mV/div IOUT, 2A/div 4 3 2 -40 -20 0 20 40 60 80 100 Temperature (°C) Fig. 5 Current-Limit (Sinking) vs. Temp. 11/07/2004 Rev.2.01 120 Fig. 6 Transient Response at 1.25VTT/3A www.SiliconStandard.com 4 of 8 SS6383B(G) TYPICAL PERFORMANCE CHARACTERISTICS (Continued) VCNTL=3.3V VIN=2.5V VREF=1.25V VCNTL=3.3V VIN=2.5V VREF=1.25V Iout, 2A/div Iout, 2A/div Fig. 7 Output Short-Circuit Protection (Sinking) Fig. 8 Output Short-Circuit Protection (Sourcing) BLOCK DIAGRAM VCNTL VIN + Control VREF VOUT Current Limit Thermal Shutdown VOUT Shutdown GND 11/07/2004 Rev.2.01 www.SiliconStandard.com 5 of 8 SS6383B(G) PIN DESCRIPTIONS (Pin numbers refer to TO-252/263) PIN 4: PIN 1: PIN 2: PIN 3: VIN - Input supply pin. It provides main power to create the external reference voltage by divider resistors for regulating VREF and VOUT. GND - Ground pin. VCNTL - Input supply pin. It is used to supply all the internal control circuitry. PIN 5: VREF - Reference voltage input. Pull this pin low to shutdown device. VOUT - Output pin. APPLICATION INFORMATION Layout Consideration As the SS6383B is in either SO-8, TO-252-5 or TO-263-5 packages, it is unable to dissipate heat easily when it operates at high current. To avoid exceeding the maximum junction temperature, a suitable copper area must be used. Fig. 9 Top layer for SO-8 11/07/2004 Rev.2.01 The large copper area shown at V CNTL pins is able to relieve the thermal dissipation. Using the via to direct heat into the large copper area shown on the bottom layer also helps significantly. All capacitors should be placed as close as possible to the relevant pins. Fig. 10 Bottom layer for SO-8 www.SiliconStandard.com Fig. 11 Placement for SO-8 6 of 8 SS6383B(G) PHYSICAL DIMENSIONS TO-263-5 A E c2 SYMBOL MIN MAX A 4.06 4.83 A1 0 0.15 C2 1.14 1.40 D 8.38 9.65 E 9.65 10.29 L2 D L e A 1.70 BSC L 14.61 15.88 L1 2.29 2.79 L2 A e 1.40 L4 θ Gauge Plane 0.25 BSC θ 0° 8° SYMBOL MIN MAX A 2.19 2.38 A1 0 0.13 b3 5.21 5.46 c2 0.46 0.58 D 5.33 5.59 E 6.35 6.73 Seating Plane L4 L1 A1 TO-252-5 A E b3 c2 L3 D H e e A A L L2 11/07/2004 Rev.2.01 A1 1.27 BSC H 9.40 10.41 L 1.4 1.78 L1 2.67 REF L2 0.51 BSC L3 1.52 2.03 θ 0° 8° L1 www.SiliconStandard.com 7 of 8 SS6383B(G) PHYSICAL DIMENSIONS (cont.) SO-8 D SYMBOL MIN MAX A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 H E e e A A1 C B 1.27(TYP) H 5.80 6.20 L 0.40 1.27 L Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 11/07/2004 Rev.2.01 www.SiliconStandard.com 8 of 8