SS811, SS812 Reset Circuits with Manual Reset Input FEATURES DESCRIPTION Ultra-low supply current of 1µA (typ.) The SS811 and SS812 are low-power microprocessor Guaranteed reset valid to Vcc=0.9V (µP ) supervisory circuits used to monitor power supplies Available in two output yypes: in µP and digital systems. They improve circuit reliability Push-pull active -low (SS811) and reduce cost by eliminating external components. Push-pull active -high (SS812) The SS811 and SS812 also offer a manual reset input. Power-on reset pulse width minimum 140ms Internally fixed threshold 2.3V, 2.6V, 2. 9V, 3.1V, 4.0V, 4.4V, and 4.6V These devices perform as valid singles in applications Tight voltage threshold tolerance: 1.5% with Vcc ranging from 6.0V down to 0.9V. The reset Low profile package: SOT-23-5 signal lasts for a minimum period of 140ms whenever the VCC supply voltage falls below a preset threshold. Both APPLICATIONS the SS811 and SS812 were designed with a reset l Notebook Computers l Digital Still Cameras l PDAs than 140ms. The only difference between the SS811 and l Critical Microprocessor Monitoring the SS812 is that one has an active -low RESET output comparator to help identify invalid signals lasting less and the other has an active -high RESET output . A low supply current (1µA) makes the SS811 and SS812 ideal for portable equipment. The devices are available in a SOT-23-5 package. TYPICAL APPLICATION CIRCUIT VCC VCC SS811 (SS812) RESET MR (RESET) VCC µP RESET INPUT GND GND Pushbutton Switch Rev.1.01 4/06/2004 www.SiliconStandard.com 1 of 8 SS811, SS812 ORDERING INFORMATION PIN CONFIGURATION SS811-XXCXXX SS812-XXCXXX SOT- 23- 5 TOP VIEW 1: G ND 2: NC 3: RESET (RESET) 4: MR 5: VCC Packing type TR: T ape and reel Package type V: SOT- 23- 5 5 1 4 2 3 Reset Threshold Voltage 23: 2.3V 26: 2.6V 29: 2.9V 31: 3.1V 40: 4.0V 44: 4.4V 46: 4.6V (Additional voltage versions with a unit of 0.1V within the voltage range from 1.5V to 5.5V for this product line may be available on demand with prior consultation with SSC.) Example: SS811 -31C VTR à 3.1V version in SOT- 23- 5 package, shipped in tape and reel. SOT -23-5 Marking Rev.1.01 4/06/2004 Part No. Marking Part No. Marking SS811-23CV BQ23 SS812-23CV BR23 SS811-26CV BQ26 SS812-26CV BR26 SS811-29CV BQ29 SS812-29CV BR29 SS811-31CV BQ31 SS812-31CV BR31 SS811-40CV BQ40 SS812-40CV BR40 SS811-44CV BQ44 SS812-44CV BR44 SS811-46CV BQ46 SS812-46CV BR46 www.SiliconStandard.com 2 of 8 SS811, SS812 ABSOLUTE MAXIMUM RATINGS VCC -0.3V ~6.5V RESET, RESET -0.3V ~ (VCC+0.3V) Input Current (V CC, MR ) 20mA Output Current (RESET or RESET ) 20mA Continuous Power Dissipation (TA = +70°C) 320mW Operating Junction Temperature Range -40°C ~ 85°C Storage Temperature Range - 65°C ~ 150°C Lead Temperature (Soldering) 10 sec 260°C Note1: Any stress beyond the Absolute Maximum Ratings above may cause permanent damage to the device. TEST CIRCUIT 1 2 3 GND NC MR 4 Iin Vin RESET SS811 Rev.1.01 4/06/2004 5 VCC Pushbutton Switch www.SiliconStandard.com 3 of 8 SS811, SS812 ELECTRICAL CHARACTERISTICS (Typical values are at TA=25° C, unless otherwise specified) PARAMETER TEST CONDITIONS SYMBOL Operating Voltage Range VCC Supply Current ICC VCC = VTH +0.1V SS811-26 SS811-29 VTH SS811-31 SS811-40 SS811-44 SS811-46 VCC to Reset Delay TRD Reset Active Timeout Period TRP MR to Reset Propagation Delay MR Input Threshold TMD TA=+25°C 2.265 TA= -40°C to +85°C 2.254 TA=+25°C 2.561 TA= -40°C to +85°C 2.548 TA=+25°C 2.857 TA= -40°C to +85°C 2.842 TA=+25°C 3.054 TA= -40°C to +85°C 3.038 TA=+25°C 3.940 TA= -40°C to +85°C 3.920 TA=+25°C 4.334 TA= -40°C to +85°C 4.312 TA=+25°C 4.531 TA=-40°C to +85°C 4.508 VCC=VTH to (VTH –0.1V), VTH=3.1V VCC TA=+25°C = VTH(MAX) TA= -40°C to +85°C RESET Output Voltage MAX. UNIT 6 V 1 3 µA 2.3 2.335 VIH 2.346 2.6 2.639 2.652 2.9 2.944 2.958 3.1 3.147 3.162 4.0 4.060 4.4 4.466 140 4.488 4.6 4.669 4.692 230 100 µS 560 1030 0.7V CC VIL 0.25V CC VOH VCC=VTH+0.1V, ISOURCE =1mA VOL VCC=VTH - 0.1V, ISINK =1mA VOH VCC=VTH+0.1V, ISOURCE =1mA VOL VCC=VTH - 0.1V, ISINK =1mA 20 mS µS 0.5 10 V 4.080 20 Vcc=6V MR Pull-Up Resistance RESET Output Voltage TYP. 0.9 SS811-23 Reset Threshold MIN. 30 0.8V CC 0.2Vcc 0.8V CC 0.2Vcc V KΩ V V Note2: RESET output is for the SS811; RESET output is for the SS812. Note3: Specifications for operating temperature ranges from -40°C to 85°C, are guaranteed by Statistical Quality Controls (SQC), with no production testing. Rev.1.01 4/06/2004 www.SiliconStandard.com 4 of 8 SS811, SS812 TYPICAL PERFORMANCE CHARACTERISTICS 120 Supply Current (µA) 1.4 VTH=2.3V 1.3 1.2 1.1 VTH=3.1V 1.0 VTH=4.6V 0.9 0.8 0.7 0.6 Power -Down Reset Delay (µs ) 1.5 110 VTH=2.3V VO D=VTH-VCC 100 90 80 70 VOD=50mV 60 50 VOD=100mV 40 30 VOD=200mV 20 10 0 0.5 - 20 -40 0 40 20 60 80 100 -60 Temperature (° C) -40 -20 0 20 40 60 80 100 Temperature (° C) Fig 2 Power-Down Reset Delay vs. Temperature Fig 1 Supply Current vs. Temperature VTH=3.1V VO D=VTH-VCC 220 200 Power -Down Reset Delay (µs ) Power -Down Reset Delay (µs ) 240 180 160 140 VOD=50mV 120 100 80 60 VOD=100mV 40 VOD=200mV 20 0 VTH=4.6V VOD=50mV 400 VOD=VTH-VCC 300 200 VOD=100mV 100 VOD=200mV 0 -60 - 40 0 -20 20 40 60 80 100 -60 - 40 - 20 0 20 40 60 80 100 Temperature (° C) Temperature (° C) Fig 3 Power-Down Reset Delay vs. Temperature Fig 4 Power-Down Reset Delay vs. Temperature Power -Up Reset Timeout (ms) Normalized Reset Threshold (V) 600 1.015 VTH=4.6V 1.010 1.005 1.000 VTH=3.1V 0.995 VTH=2.3V 0.990 0.985 -40 -20 0 20 40 60 80 100 Temperature (° C) Fig 5 Normalized Reset Threshold vs. Temperature Rev.1.01 4/06/2004 500 400 VTH=3.1V VTH=4.6V 300 200 VTH=2.3V 100 0 -60 -40 -20 0 20 40 60 80 100 Temperature (° C) Fig 6 Power-Up Reset Timeout vs. Temperature www.SiliconStandard.com 5 of 8 SS811, SS812 BLOCK DIAGRAM VCC RESET (RESET) R1 Bandgap - Reset Generator + R PULL_UP R2 20K GND MR PIN DESCRIPTIONS GND Pin RESET Pin (SS811) : Ground. : Active low output pin. RESET Output remains low while Vcc is below reset threshold. RESET Pin (SS812) : Active high output pin. RESET output remains high while Vcc is below reset threshold. MR Pin : Logic low manual reset input. This active -low input has an internal 20k Ω pull-up resistor. It can be driven by a TTL or CMOS, or shorted to ground with a switch. Leave open when unused. Vcc Pin : Supply voltage. DETAILED DESCRIPTIONS OF TECHNICAL TERMS goes high. RESET OUTPUT The microprocessor will be activated at a valid reset state. These µ P supervisory circuits assert reset to prevent code execution errors during power-up, If a brownout condition occurs (VCC drops below the reset threshold), RESET goes low. Any time VCC goes below the reset threshold, the internal timer resets to zero, and RESET goes low. The internal power-down, or brownout conditions. timer is activated after VCC returns above the reset threshold, and RESET remains low for the reset RESET is guaranteed to be a logic low for timeout period. VTH>VCC>0.9V. Once VCC exceeds the reset threshold, an internal timer keeps RESET low for The manual reset input (MR ) can also initiate a the reset timeout period; after this interval, RESET Rev.1.01 4/06/2004 reset. The SS812 has an active-high RESET output that is the inverse of the SS811’s RESET output. www.SiliconStandard.com 6 of 8 SS811, SS812 MANUAL RESET INPUT Many microprocessor-based products require manual prevent noise caused by long cables of MR or noisy environment. reset capability, allowing operators, test technicians, or external logic circuitry to initiate a reset. Logic low on MR asserts reset. Reset will remain asserted for the BENEFITS OF HIGHLY ACCURATE RESET Reset Active Timeout Period (t RP) after MR returns THRESHOLD The SS811/812 with specified voltage as 5V±10% or 3V high. This input has an internal 20KO pull-up resistor, so it can be floating if it is not used. MR can be driven power supply. The reset is guaranteed to assert after ±10% are ideal for systems using a 5V±5% or 3V±5% with the power supply falls out of regulation, but before open-drain/collector outputs. Another alternative is to connect a normal switch from MR to GND to create a power drops below the minimum specified operating manual reset function. Connecting a 0.1µF capacitor from MR to ground can provide noise immunity to thresholds reduce the range over which an undesirable with TTL or CMOS-logic levels, or voltage range of the system ICs. The pre-trimmed reset may occur. APPLICATION INFORMATION 0V, adding a pull-down resistor to RESET causes NEGATIVE-GOING VCC TRANSIENTS any leakage currents to flow to ground, holding In addition to issuing a reset to the microprocessor during power-up, power-down, and RESET low. brownout conditions, the SS811 series are relatively resistant to INTERFACING TO MICROPROCESSORS WITH short-duration negative-going VCC transient. BIDIRECTIONAL RESET PINS Microprocessors with bidirectional res et pins may ENSURING A VALID RESET OUTPUT DOWN TO VCC=0 When VCC falls below 0.9V, the SS811 RESET output no longer sinks current; it becomes an open circuit. In this case, high-impedance CMOS logic inputs connected to RESET can drift to undetermined voltages. Therefore, the SS811/2 is perfect for most CMOS applications with VCC down to 0.9V. However in applications where RESET must be valid down to Rev.1.01 4/06/2004 have contention with the SS811/812 reset outputs. If the SS811 RESET output is asserted high and the microprocessor wants to pull it low, indeterminate logic levels may occur. To correct such cases, connect a resistor between the SS811 RESET (or SS812 RESET) output and the microprocessor reset I/O. Buffer the reset output to other system components. www.SiliconStandard.com 7 of 8 SS811, SS812 PHYSICAL DIMENSIONS SOT-23-5 (unit: mm) C D L H E θ1 e SYMBOL MIN MAX A 1.00 1.30 A1 — 0.10 A2 0.70 0.90 b 0.35 0.50 C 0.10 0.25 D 2.70 3.10 E 1.40 1.80 A A2 A1 b e 1.90 (TYP) H 2.60 3.00 L 0.37 — θ1 1° 9° Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. Rev.1.01 4/06/2004 www.SiliconStandard.com 8 of 8