Audio, Dual-Matched NPN Transistor SSM2212 Very low voltage noise: 1 nV/√Hz maximum @ 100 Hz Excellent current gain match: 0.5% Low offset voltage (VOS): 200 μV maximum Outstanding offset voltage drift: 0.03 μV/°C High gain bandwidth product: 200 MHz PIN CONFIGURATION C1 1 8 C2 B1 2 7 B2 E1 3 6 E2 5 NIC NIC 4 SSM2212 NIC = NO INTERNAL CONNECTION 09043-001 FEATURES Figure 1. 8-Lead SOIC_N GENERAL DESCRIPTION The SSM2212 is a dual, NPN-matched transistor pair that is specifically designed to meet the requirements of ultralow noise audio systems. With its extremely low input base spreading resistance (rbb' is typically 28 Ω) and high current gain (hFE typically exceeds 600 at IC = 1 mA), the SSM2212 can achieve outstanding signal-tonoise ratios. The high current gain results in superior performance compared to systems incorporating commercially available monolithic amplifiers. Excellent matching of the current gain (ΔhFE) to about 0.5% and low VOS of less than 10 μV typical make the SSM2212 ideal for symmetrically balanced designs, which reduce high-order amplifier harmonic distortion. Stability of the matching parameters is guaranteed by protection diodes across the base-emitter junction. These diodes prevent degradation of beta and matching characteristics due to reverse biasing of the base-emitter junction. The SSM2212 is also an ideal choice for accurate and reliable current biasing and mirroring circuits. Furthermore, because a current mirror’s accuracy degrades exponentially with mismatches of VBE between transistor pairs, the low VOS of the SSM2212 does not need offset trimming in most circuit applications. The SSM2212 performance and characteristics are guaranteed over the extended temperature range of −40°C to +85°C. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. SSM2212 TABLE OF CONTENTS Features .............................................................................................. 1 Thermal Resistance .......................................................................4 Pin Configuration............................................................................. 1 ESD Caution...................................................................................4 General Description ......................................................................... 1 Typical Performance Characteristics ..............................................5 Revision History ............................................................................... 2 Applications Information .................................................................8 Specifications..................................................................................... 3 Fast Logarithmic Amplifier..........................................................8 Electrical Characteristics............................................................. 3 Outline Dimensions ..........................................................................9 Absolute Maximum Ratings............................................................ 4 Ordering Guide .............................................................................9 REVISION HISTORY 7/10—Rev. A to Rev. B Changes to Figure 1.......................................................................... 1 6/10—Rev. 0 to Rev. A Changes to Fast Logarithmic Amplifier Section .......................... 8 6/10—Revision 0: Initial Version Rev. B | Page 2 of 12 SSM2212 SPECIFICATIONS ELECTRICAL CHARACTERISTICS VCB = 15 V, IO = 10 μA, TA = 25°C, unless otherwise specified. Table 1. Parameter DC AND AC CHARACTERISTICS Current Gain 1 Current Gain Match 2 Noise Voltage Density 3 Symbol Text Conditions/Comments Min Typ Max Unit IC = 1 mA −40°C ≤ TA ≤ +85°C IC = 10 μA −40°C ≤ TA ≤ +85°C 10 μA ≤ IC ≤ 1 mA IC = 1 mA, VCB = 0 V fO = 10 Hz fO = 100 Hz fO = 1 kHz fO = 10 kHz IC = 1 mA VCB = 0 V, IC = 1 mA −40°C ≤ TA ≤ +85°C 0 V ≤ VCB ≤ VMAX 4 ,1 μA ≤ IC ≤ 1 mA 5 1 μA ≤ IC ≤ 1 mA5, VCB = 0 V −40°C ≤ TA ≤ +85°C −40°C ≤ TA ≤ +85°C, VOS trimmed to 0 V 300 300 200 200 605 0.5 5 % 1.6 0.9 0.85 0.85 0.4 10 2 1 1 1 nV/√Hz nV/√Hz nV/√Hz nV/√Hz μV p-p μV μV μV μV μV/°C μV/°C V MHz pA nA pA nA pA nA nA nA nA nA pA/°C V pF Ω pF hFE ΔhFE eN Low Frequency Noise (0.1 Hz to 10 Hz) Offset Voltage eN p-p VOS Offset Voltage Change vs. VCB Offset Voltage Change vs. IC Offset Voltage Drift ΔVOS/ΔVCB ΔVOS/ΔIC ΔVOS/ΔT Breakdown Voltage Gain Bandwidth Product Collector-to-Base Leakage Current BVCEO fT ICBO Collector-to-Collector Leakage Current ICC Collector-to-Emitter Leakage Current ICES Input Bias Current IB Input Offset Current IOS Input Offset Current Drift Collector Saturation Voltage Output Capacitance Bulk Resistance Collector-to-Collector Capacitance ΔIOS/ΔT VCE (SAT) COB RBE CCC 550 10 5 0.08 0.03 200 220 50 70 1 0.3 40 IC = 100 mA, VCE = 10 V VCB = VMAX −40°C ≤ TA ≤ +85°C VCC = VMAX 6, 7 −40°C ≤ TA ≤ +85°C VCE = VMAX, VBE = 0 V6, 7 −40°C ≤ TA ≤ +85°C IC = 10 μA −40°C ≤ TA ≤ +85°C IC = 10 μA −40°C ≤ TA ≤ +85°C IC = 10 μA6, −40°C ≤ TA ≤ +85°C IC = 1 mA, IB = 100 μA VCB = 15 V, IE = 0 μA 10 μA ≤ IC ≤ 10 mA6 VCC = 0 V 1 Current gain is guaranteed with collector-to-base voltage (VCB) swept from 0 V to VMAX at the indicated collector currents. Current gain match (ΔhFE) is defined as follows: ΔhFE = (100(ΔIB)(hFE min)/IC). 3 Noise voltage density is guaranteed, but not 100% tested. 4 This is the maximum change in VOS as VCB is swept from 0 V to 40 V. 5 Measured at IC = 10 μA and guaranteed by design over the specified range of IC. 6 Guaranteed by design. 7 ICC and ICES are verified by measurement of ICBO. 2 Rev. B | Page 3 of 12 200 25 3 35 4 35 4 40 0.05 23 0.3 35 500 500 500 50 50 6.2 13 150 0.2 1.6 SSM2212 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Parameter Breakdown Voltage of Collector-to-Base Voltage (BVCBO) Breakdown Voltage of Collector-to-Emitter Voltage (BVCEO) Breakdown Voltage of Collector-to-Collector Voltage (BVCC) Breakdown Voltage of Emitter-to-Emitter Voltage (BVEE) Collector Current (IC) Emitter Current (IE) Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature (Soldering, 60 sec) θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Rating 40 V Table 3. Thermal Resistance 40 V Package Type 8-Lead SOIC (R-8) 40 V 40 V ESD CAUTION 20 mA 20 mA −65°C to +150°C −40°C to +85°C −65°C to +150°C 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. B | Page 4 of 12 θJA 120 θJC 45 Unit °C/W SSM2212 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VCE = 5 V, unless otherwise specified. 900 CH1 4.92V p-p 800 TA = +125°C CURRENT GAIN (h FE) 700 1 TA = +25°C 600 500 400 TA = –55°C 300 M4.00s A CH1 15.8V 100 0.001 0.01 0.1 1 COLLECTOR CURRENT (mA) Figure 2. Low Frequency Noise (0.1 Hz to 10 Hz), IC = 1 mA, Gain = 10,000,000 09043-005 CH1 2.00V 09043-002 200 Figure 5. Current Gain vs. Collector Current (VCB = 0 V) 1k 900 1mA 700 100 CURRENT GAIN (hFE) NOISE VOLTAGE DENSITY (nV/ Hz) 800 IC = 1µA TEST 10 IC = 10µA TEST IC = 1mA TEST 1 600 500 400 300 1µA 200 1 10 100 1k 10k 100k FREQUENCY (Hz) 0 –100 09043-003 0.1 0.1 –50 0 50 100 150 TEMPERATURE (°C) Figure 3. Noise Voltage Density vs. Frequency 09043-006 100 Figure 6. Current Gain vs. Temperature (Excludes ICBO) 100 0.70 BASE EMITTER VOLTAGE, VBE (V) 0.65 60 RS = 100kΩ 40 RS = 10kΩ 0.01 0.55 VCE = 5V 0.50 0.45 0.40 0.35 RS = 1kΩ 0 0.001 0.60 0.1 COLLECTOR CURRENT, IC (mA) 1 Figure 4. Total Noise vs. Collector Current, f = 1 kHz 0.30 0.001 0.01 0.1 1 COLLECTOR CURRENT, IC (mA) Figure 7. Base Emitter Voltage vs. Collector Current Rev. B | Page 5 of 12 10 09043-008 20 09043-004 TOTAL NOISE (nV/ Hz) 80 1000 10 100 CURRENT, I CBO (nA) 100 1 VCE = 5V 0.1 10 1 0.01 0.001 0.001 0.01 0.1 1 10 COLLECTOR CURRENT, IC (mA) 0.01 25 50 75 100 125 TEMPERATURE (°C) Figure 8. Small Signal Input Resistance vs. Collector Current 09043-012 0.1 09043-009 INPUT RESISTANCE, hIE (MΩ) SSM2212 Figure 11. Collector-to-Base Leakage Current vs. Temperature 1m 40 CAPACITANCE, C CB (pF) CONDUCTANCE, h OE (mho) 35 0.1m 0.01m VCE = 5V 1µ 30 25 20 15 10 0.1µ 0.01 0.1 1 10 100 0 09043-010 0.01µ 0.001 1000 COLLECTOR CURRENT, IC (mA) 0 10 20 30 40 50 REVERSE BIAS VOLTAGE (V) Figure 9. Small Signal Output Conductance vs. Collector Current 09043-013 5 Figure 12. Collector-to-Base Capacitance vs. Reverse Bias Voltage 40 100 CAPACITANCE, C CC (pF) TA = +125°C 10 TA = +25°C 1 0.1 30 25 20 15 10 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 SATURATION VOLTAGE, VSAT (V) 0.9 0 0 10 20 30 40 COLLECTOR-TO-SUBSTRATE VOLTAGE (V) Figure 13. Collector-to-Collector Capacitance vs. Collector-to-Substrate Voltage Figure 10. Collector Current vs. Saturation Voltage Rev. B | Page 6 of 12 50 09043-014 5 0.01 09043-017 COLLECTOR CURRENT, IC (mA) 35 TA = –55°C SSM2212 1000 4.0 3.5 CAPACITANCE, C CC (pF) CURRENT, ICC (nA) 100 10 1 3.0 2.5 2.0 1.5 1.0 0.1 50 75 100 125 TEMPERATURE (°C) Figure 14. Collector-to-Collector Leakage Current vs. Temperature 0 09043-015 0.01 25 0 10 20 30 REVERSE BIAS VOLTAGE (V) 40 50 09043-016 0.5 Figure 15. Collector-to-Collector Capacitance vs. Reverse Bias Voltage Rev. B | Page 7 of 12 SSM2212 APPLICATIONS INFORMATION To compensate for the temperature dependence of the kT/q term, a resistor with a positive 0.35%/°C temperature coefficient is chosen for R2. The output is inverted with respect to the input and is nominally −1 V/decade using the component values indicated. FAST LOGARITHMIC AMPLIFIER The circuit of Figure 16 is a modification of a standard logarithmic amplifier configuration. Running the SSM2212 at 2.5 mA per side (full-scale) allows for a fast response with a wide dynamic range. The circuit has a 7 decade current range and a 5 decade voltage range, and it is capable of 2.5 μs settling time to 1% with a 1 V to 10 V step. The output follows the equation: R3 + R2 kT V REF ln R2 q V IN +15V VIN (0V TO 10V) RS 4kΩ 2 8 AD8512 1 VO 3 4 –15V 330pF R3 7.5kΩ 330pF VREF 10V R1 4kΩ SSM2212 R2 500Ω 6 1/2 AD8512 7 4kΩ R2 = TEL LABS QB1E (+0.35%/°C) 09043-018 VO = 5 Figure 16. Fast Logarithmic Amplifier Rev. B | Page 8 of 12 SSM2212 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 1 5 6.20 (0.2441) 5.80 (0.2284) 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) 0.50 (0.0196) 0.25 (0.0099) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 012407-A 8 4.00 (0.1574) 3.80 (0.1497) Figure 17. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model 1 SSM2212RZ SSM2212RZ-R7 SSM2212RZ-RL 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] Z = RoHS Compliant Part. Rev. B | Page 9 of 12 Package Option R-8 R-8 R-8 SSM2212 NOTES Rev. B | Page 10 of 12 SSM2212 NOTES Rev. B | Page 11 of 12 SSM2212 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09043-0-7/10(B) Rev. B | Page 12 of 12