SST38VF6401B / SST38VF6402B SST38VF6403B / SST38VF6404B 64 Mbit (x16) Advanced Multi-Purpose Flash Plus Features • Organized as 4M x16 • Single Voltage Read and Write Operations - 2.7-3.6V • Superior Reliability - Endurance: 100,000 Cycles minimum - Greater than 100 years Data Retention • Low Power Consumption (typical values at 5 MHz) - Active Current: 25 mA (typical) - Standby Current: 5 µA (typical) - Auto Low Power Mode: 5 µA (typical) • 128-bit Unique ID • Security-ID Feature - 248 Word, user One-Time-Programmable • Protection and Security Features - Hardware Boot Block Protection/WP# Input Pin, Uniform (32 KWord), and Non-Uniform (8 KWord) options available - User-controlled individual block (32 KWord) protection, using software only methods - Password protection • Hardware Reset Pin (RST#) • Fast Read and Page Read Access Times: - 70 ns Read access time - 25 ns Page Read access times - 8-Word Page Read buffer • Latched Address and Data • Fast Erase Times: - Block-Erase Time: 18 ms (typical) - Chip-Erase Time: 40 ms (typical) • Erase-Suspend/-Resume Capabilities • Fast Word and Write-Buffer Programming Times: - Word-Program Time: 7 µs (typical) - Write Buffer Programming Time: 1.75 µs / Word (typical) - 16-Word Write Buffer • Automatic Write Timing - Internal VPP Generation • End-of-Write Detection - Toggle Bits - Data# Polling - RY/BY# Output • CMOS I/O Compatibility 2013 Microchip Technology Inc. • JEDEC Standard - Flash EEPROM Pinouts and command sets • CFI Compliant • Packages Available - 48-lead TSOP - 48-ball TFBGA • All non-Pb (lead-free) devices are RoHS compliant Description The SST38VF6401B, SST38VF6402B, SST38VF6403B, and SST38VF6404B devices are 4M x16 CMOS Advanced Multi-Purpose Flash Plus (Advanced MPF+) manufactured with Microchip proprietary, high-performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST38VF6401B/6402B/6403B/6404B write (Program or Erase) with a 2.7-3.6V power supply. These devices conform to JEDEC standard pin assignments for x16 memories. Featuring high performance Word-Program, the SST38VF6401B/6402B/6403B/6404B provide a typical Word-Program time of 7 µsec. For faster word-programming performance, the Write-Buffer Programming feature, has a typical word-program time of 1.75 µsec. These devices use Toggle Bit, Data# Polling, or the RY/ BY# pin to indicate Program operation completion. In addition to single-word Read, Advanced MPF+ devices provide a Page-Read feature that enables a faster word read time of 25 ns, eight words on the same page. To protect against inadvertent write, the SST38VF6401B/6402B/6403B/6404B have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices are available with 100,000 cycles minimum endurance. Data retention is rated at greater than 100 years. The SST38VF6401B/6402B/6403B/6404B are suited for applications that require the convenient and economical updating of program, configuration, or data memory. For all system applications, Advanced MPF+ significantly improve performance and reliability, while lowering power consumption. These devices inherently use less energy during Erase and Program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. For any given voltage range, the SuperFlash technology uses less current to program and has Preliminary DS25002B-page 1 SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B a shorter erase time; therefore, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore, the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. 1.0 The SST38VF6401B/6402B/6403B/6404B also offer flexible data protection features. Applications that require memory protection from program and erase operations can use the Boot Block, Individual Block Protection, and Advanced Protection features. For applications that require a permanent solution, the Irreversible Block Locking feature provides permanent protection for memory blocks. To meet high-density, surface mount requirements, the SST38VF6401B/6402B/6403B/6404B devices are offered in 48-lead TSOP and 48-ball TFBGA packages. See Figures 2-1 and 2-2 for pin assignments and Table 2-1 for pin descriptions. FUNCTIONAL BLOCK DIAGRAM SuperFlash Memory X-Decoder Memory Address Address Buffer & Latches Y-Decoder CE# OE# WE# WP# RST# I/O Buffers and Data Latches Control Logic DQ15 - DQ0 RY/BY# 1309 B1.1 FIGURE 1-1: DS25002B-page 2 FUNCTIONAL BLOCK DIAGRAM Preliminary 2013 Microchip Technology Inc. SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B 2.0 PIN ASSIGNMENTS A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# RST# A21 WP# RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Standard Pinout Top View Die Up A16 NC VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VDD DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 25002 48-tsop P1.0 FIGURE 2-1: PIN ASSIGNMENTS FOR 48-LEAD TSOP 6 5 4 3 2 1 A13 A12 A14 A15 A16 NC DQ15 VSS A10 A11 DQ7 DQ14 DQ13 DQ6 WE# RST# A21 A19 DQ5 DQ12 VDD DQ4 RY/BY# WP# A18 A20 DQ2 DQ10 DQ11 DQ3 A9 A8 A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1 A3 A4 A2 A1 A0 CE# OE# VSS A B C D E F G H FIGURE 2-2: 25002 48-tfbga P1.0 TOP VIEW (balls facing down) PIN ASSIGNMENTS FOR 48-BALL TFBGA 2013 Microchip Technology Inc. Preliminary DS25002B-page 3 SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B TABLE 2-1: PIN DESCRIPTION Symbol Pin Name Functions AMS1-A0 Address Inputs To provide memory addresses. During Block-Erase AMS-A15 address lines will select the block. DQ15-DQ0 Data Input/output To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. WP# Write Protect To protect the top/bottom boot block from Erase/Program operation when grounded. RY/BY# Ready/Busy To indicate when the device is actively programming or erasing. RST# Reset To reset and return the device to Read mode. CE# Chip Enable To activate the device when CE# is low. OE# Output Enable To gate the data output buffers. WE# Write Enable To control the Write operations. VDD Power Supply To provide power supply voltage: 2.7-3.6V VSS Ground NC No Connection Unconnected pins. 1. AMS = Most significant address AMS = A21 for SST38VF6401B/6402B/6403B/6404B DS25002B-page 4 Preliminary 2013 Microchip Technology Inc. SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B 3.0 MEMORY MAPS TABLE 3-1: SST38VF6401B AND SST38VF6402B MEMORY MAPS SST38VF6401B Size Block1 B04 32 KWord B1 32 KWord B2 32 KWord B3 32 KWord B4 32 KWord B5 32 KWord B6 32 KWord B7 32 KWord B8 - B119 follow the same pattern B120 32 KWord B121 32 KWord B122 32 KWord B123 32 KWord B124 32 KWord B125 32 KWord B126 32 KWord B127 32 KWord Address A21-A152 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 VPB3 YES YES YES YES YES YES YES YES NVPB3 YES YES YES YES YES YES YES YES WP#4 YES NO NO NO NO NO NO NO 1111000 1111001 1111010 1111011 1111100 1111101 1111110 1111111 YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES NO NO NO NO NO NO NO NO Address A21-A152 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 VPB3 YES YES YES YES YES YES YES YES NVPB3 YES YES YES YES YES YES YES YES WP#5 NO NO NO NO NO NO NO NO 1111000 1111001 1111010 1111011 1111100 1111101 1111110 1111111 YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES NO NO NO NO NO NO NO YES SST38VF6402B Size Block1 B0 32 KWord B1 32 KWord B2 32 KWord B3 32 KWord B4 32 KWord B5 32 KWord B6 32 KWord B7 32 KWord B8 - B119 follow the same pattern B120 32 KWord B121 32 KWord B122 32 KWord B123 32 KWord B124 32 KWord B125 32 KWord B126 32 KWord 32 KWord B1275 1. 2. 3. 4. 5. Each block, B0-B127 is 32KWord. X = 0 or 1. Block Address (BA) = A21 - A15 Each block has an associated VPB and NVPB. Block B0 is the boot block. Block B127 is the boot block. 2013 Microchip Technology Inc. Preliminary DS25002B-page 5 SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B TABLE 3-2: SST38VF6403B AND SST38VF6404B MEMORY MAPS (SHEET 1 OF 2) SST38VF6403B Block1 3,4 Size Address A21-A152 VPB3 NVPB3 WP#4 B0 4 KWord 0000000000 YES YES YES B1 4 KWord 0000000001 YES YES YES B2 4 KWord 0000000010 YES YES NO B3 4 KWord 0000000011 YES YES NO B4 4 KWord 0000000100 YES YES NO B5 4 KWord 0000000101 YES YES NO B6 4 KWord 0000000110 YES YES NO B7 4 KWord 0000000111 YES YES NO B8 32 KWord 0000001XXX YES YES NO B9 32 KWord 0000010XXX YES YES NO B10 32 KWord 0000011XXX YES YES NO B11 32 KWord 0000100XXX YES YES NO B12 32 KWord 0000101XXX YES YES NO B13 32 KWord 0000110XXX YES YES NO B14 32 KWord 0000111XXX YES YES NO B15 32 KWord 0001000XXX YES YES NO B16 - B126 follow the same pattern B127 32 KWord 1111000XXX YES YES NO B128 32 KWord 1111001XXX YES YES NO B129 32 KWord 1111010XXX YES YES NO B1230 32 KWord 1111011XXX YES YES NO B1231 32 KWord 1111100XXX YES YES NO B1232 32 KWord 1111101XXX YES YES NO B133 32 KWord 1111110XXX YES YES NO B134 32 KWord 1111111XXX YES YES NO Size Address A21-A152 VPB3 NVPB3 WP#5 SST38VF6404B Block1 B0 32 KWord 0000000XXX YES YES NO B1 32 KWord 0000001XXX YES YES NO B2 32 KWord 0000010XXX YES YES NO B3 32 KWord 0000011XXX YES YES NO B4 32 KWord 0000100XXX YES YES NO B5 32 KWord 0000101XXX YES YES NO B6 32 KWord 0000110XXX YES YES NO B7 32 KWord 0000111XXX YES YES NO B8 - B119 follow the same pattern B120 32 KWord 1111000XXX YES YES NO B121 32 KWord 1111001XXX YES YES NO B122 32 KWord 1111010XXX YES YES NO B123 32 KWord 1111011XXX YES YES NO B124 32 KWord 1111100XXX YES YES NO B125 32 KWord 1111101XXX YES YES NO B126 32 KWord 1111110XXX YES YES NO B1273, 5 4 KWord 1111111000 YES YES NO DS25002B-page 6 Preliminary 2013 Microchip Technology Inc. SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B TABLE 3-2: SST38VF6403B AND SST38VF6404B MEMORY MAPS (CONTINUED) (SHEET 2 OF 2) B128 4 KWord 1111111001 YES YES NO B129 4 KWord 1111111010 YES YES NO B130 4 KWord 1111111011 YES YES NO B131 4 KWord 1111111100 YES YES NO B132 4 KWord 1111111101 YES YES NO B133 4 KWord 1111111110 YES YES YES B134 4 KWord 1111111111 YES YES YES 1. Each block, B0-B127 is 32KWord. 2. X = 0 or 1. Block Address (BA) = A21 - A15 3. Each block has an associated VPB and NVPB, except for some blocks in SST38VF6403B and SST38VF6404B. In SST38VF6403B, Block B0 does not have a single VPB or NVPB for all 32 KWords. Instead, each block (4 KWord) in Block B0 has its own VPB and NVPB. In SST38VF6404B, Block B127 does not have a single VPB or NVPB for all 32 KWords. Instead, each block (4 KWord) in Block B127 has its own VPB and NVPB. 4. The 8KWord boot block consists of S0 and S1 in Block B0. 5. The 8KWord boot block consists of S1022 and S1023 in Block B127. 2013 Microchip Technology Inc. Preliminary DS25002B-page 7 SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B 4.0 DEVICE OPERATION 4.3 The memory operations functions of these devices are initiated using commands written to the device using standard microprocessor Write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. The SST38VF6401B/6402B/6403B/6404B also have the Auto Low Power mode which puts the device in a nearstandby mode after data has been accessed with a valid Read operation. This reduces the IDD active read current from typically 6 mA to typically 5 µA. The device requires no access time to exit the Auto Low Power mode after any address transition or control signal transition used to initiate another Read cycle. The device does not enter Auto-Low Power mode after power-up with CE# held steadily low, until the first address transition or CE# is driven high. 4.1 Read The Read operation of the SST38VF6401B/6402B/ 6403B/6404B is controlled by CE# and OE#, both of which have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to Figure 6-1, the Read cycle timing diagram, for further details. 4.2 Page Read The Page Read operation utilizes an asynchronous method that enables the system to read data from the SST38VF6401B/6402B/6403B/6404B at a faster rate. This operation allows users to read an eight-word page of data at an average speed of 33 ns per word. In Page Read, the initial word read from the page requires TACC to be valid, while the remaining seven words in the page require only TPACC. All eight words in the page have the same address bits, A21-A3, which are used to select the page. Address bits A2-A0 are toggled, in any order, to read the words within the page. The Page Read operation of the SST38VF6401B/ 6402B/6403B/6404B is controlled by CE# and OE#. Both CE# and OE# must be low for the system to obtain data from the output pins. CE# controls device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to Figure 6-2, the Page Read cycle timing diagram, for further details. DS25002B-page 8 Word-Program Operation The SST38VF6401B/6402B/6403B/6404B can be programmed on a word-by-word basis. Before programming, the block where the word exists must be fully erased. The Program operation is accomplished in three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 7 µs. See Figures 6-3 and 6-4 for WE# and CE# controlled Program operation timing diagrams and Figure 6-19 for flowcharts. During the Program operation, the only valid reads are Data# Polling, Toggle Bits, and RY/BY#. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored. During the command sequence, WP# should be statically held high or low. When programming more than a few words, Microchip recommends Write-Buffer Programming. 4.4 Write-Buffer Programming The SST38VF6401B/6402B/6403B/6404B offer WriteBuffer Programming, a feature that enables faster effective word programming. To use this feature, write up to 16 words with the Write-to-Buffer command, then use the Program Buffer-to-Flash command to program the Write-Buffer to memory. The Write-to-Buffer command consists of between 5 and 20 write cycles. The total number of write cycles in the Write-to-Buffer command sequence is equal to the number of words to be written to the buffer plus four. The first three cycles in the command sequence tell the device that a Write-to-Buffer operation will begin. The fourth cycle tells the device the number of words to be written into the buffer and the block address of these words. Specifically, the write cycle consists of a block address and a data value called the Word Count (WC), which is the number of words to be written to the buffer minus one. If the WC is greater than 15, the maximum buffer size minus 1, then the operation aborts. For the fifth cycle, and all subsequent cycles of the Write-to-Buffer command, the command sequence consists of the addresses and data of the words to be written into the buffer. All of these cycles must have the same A21 - A4 address, otherwise the operation aborts. The number of Write cycles required is equal to the number of words to be written into the Write-Buffer, which is equal to WC plus one. The correct number of Preliminary 2013 Microchip Technology Inc. SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B Write cycles must be issued or the operation will abort. Each Write cycle decrements the Write-Buffer counter, even if two or more of the Write cycles have identical address values. Only the final data loaded for each buffer location is held in the Write-Buffer. Once the Write-to-Buffer command sequence is completed, the Program Buffer-to-Flash command should be issued to program the Write-Buffer contents to the specified block in memory. The block address (i.e. A21 - A15) in this command must match the block address in the 4th write cycle of the Write-to-Buffer command or the operation aborts. See Table 5-2 for details on Writeto-Buffer and Program-Buffer-to-Flash commands. While issuing these command sequences, the WriteBuffer Programming Abort detection bit (DQ1) indicates if the operation has aborted. There are several cases in which the device can abort: • In the fourth write cycle of the Write-to-Buffer command, if the WC is greater than 15, the operation aborts. • In the fifth and all subsequent cycles of the Writeto-Buffer command, if the address values, A21 A4, are not identical, the operation aborts. • If the number of write cycles between the fifth to the last cycle of the Write-to-Buffer command is greater than WC +1, the operation aborts. • After completing the Write-to-Buffer command sequence, issuing any command other than the Program Buffer-to-Flash command, aborts the operation. • Loading a block address, i.e. A21-A15, in the Program Buffer-to-Flash command that does not match the block address used in the Write-to-Buffer command aborts the operation. If the Write-to-Buffer or Program Buffer-to-Flash operation aborts, then DQ1 = 1 and the device enters WriteBuffer-Abort mode. To execute another operation, a Write-to-Buffer Abort-Reset command must be issued to clear DQ1 and return the device to standard read mode. After the Write-to-Buffer and Program Buffer-to-Flash commands are successfully issued, the programming operation can be monitored using Data# Polling, Toggle Bits, and RY/BY#. 4.5 Block-Erase Operations The Block-Erase operation allows the system to erase the device on a block-by-block basis. The Block-Erase architecture is based on block size of 32 KWords. In SST38VF6401B and SST38VF6402B devices, the Block-Erase command can erase any 32KWord Block (B0-B127). For the non-uniform boot block devices, SST38VF6403B and SST38VF6404B, the Block-Erase command can erase any 32 KWord 2013 Microchip Technology Inc. block except the block that contains the boot area. In the boot area, Block-Erase only erases a 4KWord block. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (30H) and block address (BA) in the last bus cycle. The block address is latched on the falling edge of the sixth WE# pulse, while the command (30H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle Bit methods. The RY/BY# pin can also be used to monitor the erase operation. For more information, see Figure 6-10 for timing waveforms and Figure 6-24 for the flowchart. Any commands, other than Erase-Suspend, issued during the Block-Erase operation are ignored. Any attempt to Block-Erase memory inside a block protected by Volatile Block Protection, Non-Volatile Block Protection, or WP# (low) will be ignored. During the command sequence, WP# should be statically held high or low. 4.6 Erase-Suspend/Erase-Resume Commands The Erase-Suspend operation temporarily suspends a Block-Erase operation thus allowing data to be read or programmed into any block that is not engaged in an Erase operation. The operation is executed with a onebyte command sequence with Erase-Suspend command (B0H). The device automatically enters read mode within 20 µs (max) after the Erase-Suspend command had been issued. Valid data can be read, using a Read or Page Read operation, from any block that is not being erased. Reading at an address location within Erase-Suspended blocks will output DQ2 toggling and DQ6 at ‘1’. While in Erase-Suspend, a WordProgram or Write-Buffer Programming operation is allowed anywhere except the block selected for EraseSuspend. To resume a suspended Block-Erase operation, the system must issue the Erase-Resume command. The operation is executed by issuing one byte command sequence with Erase-Resume command (30H) at any address in the last Byte sequence. When an erase operation is suspended, or re-suspended, after resume the cumulative time needed for the erase operation to complete is greater than the erase time of a non-suspended erase operation. If the hold time from Erase-Resume to the next Erase- Suspend operation is less than 200µs, the accumulative erase time can become very long Therefore, after issuing an Erase-Resume command, the system must wait at least 200µs before issuing another Erase-Suspend command. The Erase-Resume command will be ignored until any program operations initiated during Erase-Suspend are complete. Preliminary DS25002B-page 9 SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B Bypass mode can be entered while in Erase-Suspend, but only Bypass Word-Program is available for those blocks that are not suspended. Bypass Block-Erase, Bypass Chip-Erase, Erase-Suspend, and EraseResume are not available. In order to resume an Erase operation, the Bypass mode must be exited before issuing Erase-Resume. For more information about Bypass mode, see “Bypass Mode” on page 13. 4.7 Chip-Erase Operation The SST38VF6401B/6402B/6403B/6404B devices provide a Chip-Erase operation, which erases the entire memory array to the ‘1’ state. This operation is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a six-byte command sequence with Chip-Erase command (10H) at address 555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid reads are Toggle Bit, Data# Polling, or RY/BY#. See Table 5-2 for the command sequence, Figure 6-9 for timing diagram, and Figure 6-24 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. If WP# is low, or any VPBs or NVPBs are in the protect state, any attempt to execute a Chip-Erase operation is ignored. During the command sequence, WP# should be statically held high or low. 4.8 Write Operation Status Detection To optimize the system Write cycle time, the SST38VF6401B/6402B/6403B/6404B provide two software means to detect the completion of a Write (Program or Erase) cycle The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system. Therefore, Data# Polling or Toggle Bit maybe be read concurrent with the completion of the write cycle. If this occurs, the system may possibly get an incorrect result from the status detection process. For example, valid data may appear to conflict with either DQ7 or DQ6. To prevent false results, upon detection of failures, the software routine should loop to read the accessed location an additional two times. If both reads are valid, then the device has completed the Write cycle, otherwise the failure is valid. For the Write-Buffer Programming feature, DQ1 informs the user if either the Write-to-Buffer or Program Buffer-to-Flash operation aborts. If either operation aborts, then DQ1 = 1. DQ1 must be cleared to '0' by issuing the Write-to-Buffer Abort Reset command. DS25002B-page 10 The SST38VF6401B/6402B/6403B/6404B also provide a RY/BY# signal. This signal indicates the status of a Program or Erase operation. If a Program or Erase operation is attempted on a protected block, the operation will abort. After the device initiates an abort, the corresponding Write Operation Status Detection Bits will stay active for approximately 200ns (program or erase) before the device returns to read mode. For the status of these bits during a Write operation, see Table 4-1. 4.8.1 DATA# POLLING (DQ7) When the SST38VF6401B/6402B/6403B/6404B are in an internal Program operation, any attempt to read DQ7 will produce the complement of true data. For a Program Buffer-to-Flash operation, DQ7 is the complement of the last word loaded in the Write-Buffer using the Write-to-Buffer command. Once the Program operation is completed, DQ7 will produce valid data. Note that even though DQ7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid. Valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µs. During an internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Block- or ChipErase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 6-7 for Data# Polling timing diagram and Figure 6-21 for a flowchart. 4.8.2 TOGGLE BITS (DQ6 AND DQ2) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating ‘1’s and ‘0’s, i.e., toggling between ‘1’ and ‘0’. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling, and the device is then ready for the next operation. For Block- or Chip-Erase, the toggle bit (DQ6) is valid after the rising edge of sixth WE# (or CE#) pulse. DQ6 will be set to ‘1’ if a Read operation is attempted on an Erase-Suspended Block. If Program operation is initiated in a block not selected in Erase-Suspend mode, DQ6 will toggle. An additional Toggle Bit is available on DQ2, which can be used in conjunction with DQ6 to check whether a particular block is being actively erased or erase-suspended. Table 4-1 shows detailed bit status information. The Toggle Bit (DQ2) is valid after the rising edge of the last WE# (or CE#) pulse of Write operation. See Figure 6-8 for Toggle Bit timing diagram and Figure 621 for a flowchart. Preliminary 2013 Microchip Technology Inc. SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B 4.8.3 DQ1 4.8.4 If an operation aborts during a Write-to-Buffer or Program Buffer-to-Flash operation, DQ1 is set to ‘1’. To reset DQ1 to ‘0’, issue the Write-to-Buffer Abort Reset command to exit the abort state. A power-off/power-on cycle or a Hardware Reset (RST# = 0) will also clear DQ1. TABLE 4-1: RY/BY# The RY/BY# pin can be used to determine the status of a Program or Erase operation. The RY/BY# pin is valid after the rising edge of the final WE# pulse in the command sequence. If RY/BY# = 0, then the device is actively programming or erasing. If RY/BY# = 1, the device is in Read mode. The RY/BY# pin is an open drain output pin. This means several RY/BY# can be tied together with a pull-up resistor to VDD.. WRITE OPERATION STATUS DQ71 Status Normal Operation Standard Program DQ7# Standard Erase Erase-Suspend Mode Read from Non- Erase-Suspended Data Block Program Bufferto-Flash DQ6 DQ21 DQ1 RY/BY#2 Toggle No Toggle 0 0 0 Toggle Toggle N/A 0 Read from Erase-Suspended Block 1 No toggle Toggle N/A 1 Data Data Data 1 Program DQ7# Toggle N/A N/A 0 Busy DQ7#3 Toggle N/A 0 0 Abort DQ7#3 Toggle N/A 1 0 1. DQ7 and DQ2 require a valid address when reading status information. 2. RY/BY# is an open drain pin. RY/BY# is high in Read mode, and Read in Erase-Suspend mode. 3. During a Program Buffer-to-Flash operation, the datum on the DQ7 pin is the complement of DQ7 of the last word loaded in the Write-Buffer using the Write-to-Buffer command. 4.9 Data Protection The SST38VF6401B/6402B/6403B/6404B provide both hardware and software features to protect nonvolatile data from inadvertent writes. 4.9.1 4.9.1.1 HARDWARE DATA PROTECTION Noise/Glitch Protection The SST38VF6401B and SST38VF6403B devices support bottom hardware block protection, which protects the bottom boot block of the device. For SST38VF6401B, the boot block consists of the bottom 32 KWord block, and for SST38VF6403B the Boot Block consists of the bottom two 4 KWord blocks (8 KWord total). The boot block addresses are described in Table 4-2. A WE# or CE# pulse of less than 5 ns will not initiate a write cycle. 4.9.1.2 VDD Power Up/Down Detection The Write operation is inhibited when VDD is less than 1.5V. 4.9.1.3 Write Inhibit Mode Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. 4.9.2 HARDWARE BLOCK PROTECTION The SST38VF6402B and SST38VF6404B devices support top hardware block protection, which protects the top boot block of the device. For SST38VF6402B, the boot block consists of the top 32 KWord block, and for SST38VF6404B the boot block consists of the top two 4 KWord blocks (8 KWord total). 2013 Microchip Technology Inc. Preliminary DS25002B-page 11 SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B TABLE 4-2: BOOT BLOCK ADDRESS RANGES Product tents of DQ15-DQ8 can be VIL or VIH, but no other value, during any SDP command sequence. Size Address Range 32 KW 000000H007FFFH 32 KW 3F8000H3FFFFFH Bottom Boot Uniform SST38VF6401B The SST38VF6401B/6402B/6403B/6404B devices provide Bypass Mode, which allows for reduced Program and Erase command sequence lengths. In this mode, the SDP portion of Program and Erase command sequences are omitted. See “Bypass Mode” on page 13 for further details. Top Boot Uniform SST38VF6402B 4.10 Bottom Boot NonUniform SST38VF6403B 8 KW 000000H001FFFH 8 KW 3FE000H3FFFFFH The SST38VF6401B/6402B/6403B/6404B contain Common Flash Memory Interface (CFI) information that describes the characteristics of the device. In order to enter the CFI Query mode, the system can write a onebyte sequence using a standard CFI Query Entry command. Once the device enters the CFI Query mode, the system can read CFI data at the addresses given in Tables 5-4 through 5-7. Top Boot NonUniform SST38VF6404B Program and Erase operations are prevented on the Boot Block when WP# is low. If WP# is left floating, it is internally held high via a pull-up resistor. When WP# is high, the Boot Block is unprotected, which allows Program and Erase operations on that area. 4.9.3 The interrupted Erase or Program operation must be re-initiated after the device resumes normal operation mode to ensure data integrity. SOFTWARE DATA PROTECTION (SDP) The SST38VF6401B/6402B/6403B/6404B devices implement the JEDEC approved Software Data Protection (SDP) scheme for all data alteration operations, such as Program and Erase. These devices are shipped with the Software Data Protection permanently enabled. See Table 5-2 for the specific software command codes. All Program operations require the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations. SDP for Erase operations is similar to Program, but a sixbyte load sequence is required for Erase operations. During SDP command sequence, invalid commands will abort the device to read mode within TRC. The con- DS25002B-page 12 The system must write the CFI Exit command to return to Read mode. Note that the CFI Exit command is ignored during an internal Program or Erase operation. See Table 5-2 for software command codes, Figures 612 and 6-13 for timing waveform, and Figures 6-22 and 6-23 for flowcharts. 4.11 HARDWARE RESET (RST#) The RST# pin provides a hardware method of resetting the device to read array data. When the RST# pin is held low for at least TRP, any in-progress operation will terminate and return to Read mode. When no internal Program/Erase operation is in progress, a minimum period of TRHR is required after RST# is driven high before a valid Read can take place. See Figure 6-15 for more information. 4.9.4 Common Flash Memory Interface (CFI) Product Identification The Product Identification mode identifies the devices as the SST38VF6401B, SST38VF6402B, SST38VF6403B, or SST38VF6404B, and the manufacturer as Microchip. See Table 4-3 for specific address and data information. Product Identification mode is accessed through software operations. The software Product Identification operations identify the part, and can be useful when using multiple manufacturers in the same socket. For details, see Table 5-2 for software operation, Figure 6-11 for the software ID Entry and Read timing diagram, and Figure 6-22 for the software ID Entry command sequence flowchart. TABLE 4-3: PRODUCT IDENTIFICATION Add Data Add Data Add Data Manufacturer’s ID 00H BFH 01H 227EH 0EH 220CH 0FH 2200H Device ID SST38VF6401B SST38VF6402B 01H 227EH 0EH 220CH 0FH 2201H SST38VF6403B 01H 227EH 0EH 2210H 0FH 2200H SST38VF6404B 01H 227EH 0EH 2210H 0FH 2201H While in Product Identification mode, the Read Block Protection Status command determines if a block is protected. The status returned indicates if the block has been protected, but does not differentiate between Volatile Block Protection and Non-Volatile Block Protection. See Table 5-2 for further details. Preliminary 2013 Microchip Technology Inc. SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B The Read-Irreversible Block-Lock Status command indicates if the Irreversible Block Command has been issued. If DQ0 = 0, then the Irreversible Lock command has been previously issued. In order to return to the standard Read mode, the software Product Identification mode must be exited. The exit is accomplished by issuing the software ID Exit command sequence, which returns the device to the Read mode. See Table 5-2 for software command codes, Figure 6-13 for timing waveform, and Figures 622 and 6-23 for flowcharts. 4.12 Security ID The SST38VF6401B/6402B/6403B/6404B devices offer a Security ID feature. The Secure ID space is divided into two segments — one factory programmed 128 bit segment and one user programmable 248 word segment. See Table 4-4 for address information. The first segment is programmed and locked at Microchip and contains a 128 bit Unique ID which uniquely identifies the device. The user segment is left un-programmed for the customer to program as desired. TABLE 4-4: ADDRESS RANGE FOR SEC ID Microchip Unique ID User Entering Bypass Mode while already in Erase-Suspend limits the available commands. See “Erase-Suspend/ Erase-Resume Commands” on page 9 for more information. 4.14 Protection Settings Register (PSR) The Protection Settings Register (PSR) is a user-programmable register that allows for further customization of the SST38VF6401B/6402B/6403B/6404B protection features. The 16-bit PSR provides four One Time Programmable (OTP) bits for users, each of which can be programmed individually. However, once an OTP bit is programmed to ‘0’, the value cannot be changed back to a ‘1’. The other 12 bits of the PSR are reserved. See Table 4-5 for the definition of all 16-bits of the PSR. TABLE 4-5: Bit PSR BIT DEFINITIONS Default from Factory Definition Size Address 128 bits 000H – 007H DQ15DQ5 248 W 008H – 0FFH DQ4 1 DQ3 1 Reserved DQ2 1 Password mode 0 = Password only mode 1 = Pass-Through mode DQ1 1 Pass-Through mode 0 = Pass-Through only mode 1 = Pass-Through mode DQ0 1 SEC ID Lock Out Bit 0 = locked 1 = unlocked The user segment of the Security ID can be programmed by first using the SEC ID Entry command to enter the Secure ID space. Once in the Secure ID space, for smaller data sets, use the Word-Program command to program data. To program larger sets of data more quickly, use the Write-Buffer Programming feature. Note that Bypass Mode is not available. To detect end-of-write for the SEC ID, read the toggle bits. Do not use Data# Polling to detect end of Write. Once the programming is complete, lock the Sec ID by programming bit ‘0’ in the PSR with the PSR Program command. Locking the Sec ID disables any corruption of this space. Note that regardless of whether or not the Sec ID is locked, the Sec ID segments can not be erased. The Secure ID space can be queried by executing a three-byte command sequence with Enter Sec ID command (88H) at address 555H in the last byte sequence. To exit this mode, the Exit Sec ID command should be executed. Refer to Table 5-2 for software commands and Figures 6-22 and 6-23 for flow charts. 4.13 Chip Erase, Erase-Suspend, and Erase-Resume commands are available. The Bypass Exit command exits Bypass mode. See Table 5-2 for further details. Bypass Mode Bypass mode shortens the time needed to issue program and erase commands by reducing these commands to two write cycles each. After using the Bypass Entry command to enter the Bypass mode, only the Bypass Word-Program, Bypass Block Erase, Bypass 2013 Microchip Technology Inc. FFFh Reserved VPB power-up / hardware reset state 0 = all protected 1 = all unprotected Note that DQ4, DQ2, DQ1, DQ0 do not have to be programmed at the same time. In addition, DQ2 and DQ1 cannot both be programmed to ‘0’. The valid combinations of states of DQ2 and DQ1 are shown in Table 4-6. TABLE 4-6: VALID DQ2 AND DQ1 COMBINATIONS Combination Definition DQ2, DQ1 = 11 Pass-Through mode (factory default) DQ2, DQ1 = 10 Pass-Through only mode DQ2, DQ1 = 01 Password only mode DQ2, DQ1 = 00 Not Allowed Preliminary DS25002B-page 13 SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B The PSR can be accessed by issuing the PSR Entry command. Users can then use the PSR Program and PSR Read commands. The PSR Exit command must be issued to leave this mode. See Table 5-2 for further details. 4.15 Individual Block Protection The SST38VF6401B/6402B/6403B/6404B provide two methods for Individual Block protection: Volatile Block Protection and Non-Volatile Block Protection. Data in protected blocks cannot be altered. 4.15.1 After using the Volatile Block Protection Mode Entry command to enter the Volatile Block Protection mode, individual VPBs can be set or reset with VPB Set/Clear, or be read with VPB Status Read. If the VPB is ‘0’, then the block is protected from Program and Erase. If the VPB is ‘1’, then the block is unprotected. The Volatile Block Protection Exit command must be issued to exit Volatile Block Protection mode. See Table 5-2 for further details on the commands and Figure 6-26 for a flow chart. If the device experiences a hardware reset or a power cycle, all the VPBs return to their default state as determined by user-programmable bit DQ4 in the PSR. If DQ4 is ‘0’, then all VPBs default to ‘0’ (protected). If DQ4 is ‘1’, then all VPBs default to ‘1’ (unprotected). NON-VOLATILE BLOCK PROTECTION The Non-Volatile Block Protection feature provides protection to individual blocks using Non-Volatile Protection Bits (NVPBs). Each block has it’s own Non-Volatile Protection Bit. In the SST38VF6401B/2, the 32 KWord boot block also has a it's own NVPB. In the SST38VF6403B/6404B, each 4 KWord block in the 8KWord boot area has it's own NVPB. All NVPBs come from the factory set to ‘1’, the unprotected state. Use the Non-Volatile Block Protection Mode Entry command to enter the Non-Volatile Block Protection mode. Once in this mode, the NVPB Program command can be used to protect individual blocks by setting individual NVPBs to ‘0’. The time needed to program an NVPB is two times TBP, which is a maximum of 20µs. The NVPB Status Read command can be used to check the protection state of an individual NVPB. To change an NVPB to ‘1’, the unprotected state, the NVPB must be erased using NVPBs Erase command. This command erases all NVPBs to ‘1’ and can take up DS25002B-page 14 Upon a power cycle or hardware reset, the NVPBs retain their states. Memory areas that are protected using Non-Volatile Block Protection remain protected. The NVPB Program and NVPBs Erase commands are permanently disabled once the Irreversible Block Lock command is issued. See “Irreversible Block Locking” on page 15 for further information. 4.16 VOLATILE BLOCK PROTECTION The Volatile Block Protection feature provides a faster method than Non-Volatile Protection to protect and unprotect 32 KWord blocks. Each block has it’s own Volatile Protection Bit (VPB). In the SST38VF6401B/ 6402B, the 32 KWord boot block also has a VPB. In the SST38VF6403B/6404B devices, each of the two 4 KWord blocks in the 8 KWord boot area has it's own VPB. 4.15.2 to 25 ms to complete. NVPB Program should be used to set the NVPBs of any blocks that are to be protected before exiting the Non-Volatile Block Protection mode. See Table 5-2 and Figure 6-27 for further details. Advanced Protection The SST38VF6401B/6402B/6403B/6404B provide Advanced Protection features that allow users to implement conditional access to the NVPBs. Specifically, Advanced Protection uses the Global Lock Bit to protect the NVPBs. If the Global Lock bit is ‘0’ then all the NVPBs states are frozen and cannot be modified in any mode. If the Global Lock bit is ‘1’, then all the NVPBs can be modified in Non-Volatile Block Protection mode. After using the Global Lock of NVPBs Entry command to enter the Global Lock of NVPBs mode, the Global Lock Bit can be activated by issuing a Set Global Lock Bit command, which sets the Global Lock Bit to ‘0’. The Global Lock bit cannot be set to ‘1’ with this command. The status of the bit can be read with the Global Lock Bit Status command. Use the Global Lock of NVPBs Exit command to exit Global Lock of NVPBs mode. See Table 5-2 and Figure 6-28 for further details. The steps used to change the Global Lock Bit from '0' to'1,' to allow access to the NVPBs, depend on whether the device has been set to use Pass-Through or Password mode. When using Advanced Protection, select either Pass-Through only mode or Password only mode by programming the DQ2 and DQ1 bits in the PSR. Although the factory default is Pass-Through mode (DQ2 = 1, DQ1 = 1), the user should explicitly chose either Pass-Through only mode (DQ2 = 1, DQ1 = 0), or Password only mode (DQ2 = 0, DQ1 = 1). Keeping the SST38VF6401B/6402B/6403B/6404B in the factory default Pass-Through mode leaves the device open to unauthorized changes of DQ2 and DQ1 in the PSR. See “Protection Settings Register (PSR)” on page 13. for more information about the PSR. 4.16.1 PASS-THROUGH MODE (DQ2, DQ1 = 1,0) The Pass-Through Mode allows the Global Lock Bit state to be cleared to ‘1’ by a power-down power-up sequence or a hardware reset (RST# pin = 0). No password is required in Pass-Through mode. To set the Global Lock Bit to ‘0’, use the Set Global Lock Bit command while in the Global Lock of NVPBs mode. Select the Pass-Through only mode by programming PSR bit DQ2 = 1 and DQ1 = 0. Preliminary 2013 Microchip Technology Inc. SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B 4.16.2 PASSWORD MODE (DQ2, DQ1 = 0,1) In the Password Mode, the Global Lock Bit is set to ‘0’ by the Set Global Lock Bit command, a power-down power-up sequence, or a hardware reset (RST# pin = 0). Select the Password only mode by programming PSR bit DQ2 = 0 and DQ1 = 1. Note that when the PSR Program command is issued in Password mode, the Global Lock bit is automatically set to ‘0’. In contrast to the Pass-Through Mode, in the Password mode, the only way to clear the Global Lock Bit to ‘1’ is to submit the correct 64-bit password using the Submit Password command in Password Commands Mode. The words of the password can be submitted in any order as long as each 16 bit section of the password is matched with its correct address. After the entire 64 bit password is submitted, the device takes approximately 1 µs to verify the password. A subsequent Submit Password command cannot be issued until this verification time has elapsed. The 64-bit password must be chosen by the user before programming the DQ2 and DQ1 OTP bits of the PSR to choose Password Mode. The default 64 bit password on the device from the factory is FFFFFFFFFFFFFFFFh. Enter the Password Commands mode by issuing the Password Commands Entry command. Then, use the Password Program command to program the desired password. Use caution when programming the password because there is no method to reset the password to FFFFFFFFFFFFFFFFh. Once a password bit has been set to ‘0’, it cannot be changed back to ‘1’. See Table 5-2 for further details about Password-related commands. mands are permanently disabled. There is no longer any method for reading or modifying the password. In addition, Microchip is unable to read or modify the password. If a Password Read command is issued while in Password mode, the data presented for each word of the password is FFFFh. If the Password Mode is not explicitly chosen in the PSR, then the password can still be read and modified. Therefore, Microchip strongly recommends that users explicitly choose Password Mode in the PSR. 4.17 The SST38VF6401B/6402B/6403B/6404B provides Irreversible Block Locking, a feature that allows users to customize the size of Read-Only Memory (ROM) on the device and provides more flexibility than One-Time Programmable (OTP) memory. Applying Irreversible Block Locking turns user-selected memory areas into ROM by permanently disabling Program and Erase operations to these chosen areas. Any area that becomes ROM cannot be changed back to Flash. Any memory blocks in the main memory, including boot blocks, can be irreversibly locked. In non-uniform boot block devices (SST38VF6403B and SST38VF6404B) each 4 KW block in the boot area can be irreversibly locked. If desired, all blocks in the main memory can be irreversibly locked. To use Irreversible Block Locking do the following: 1. The password can be read using the Password Read command to verify the desired password has been programmed. Microchip recommends testing the password before permanently choosing Password Mode. 2. 3. To test the password, do the following: 4. 5. 1. 2. 3. 4. 5. 6. 7. 8. 9. Enter the Global Lock of NVPBs mode. Set the Global Lock Bit to ‘0’, and verify the value. Exit the Global Lock of NVPBs mode. Enter the Password Commands mode. Submit the 64-bit password with the Submit Password command. Wait 2 µs for the device to verify the password. Exit the Password Commands mode. Re-enter the Global Lock of NVPBs mode Read the Global Lock Bit with the Global Lock Bit Status Read command. The Global Lock bit should now be ‘1’. After verifying the password, program the DQ2 and DQ1 OTP bits of the PSR to explicitly choose Password mode. Once the Password mode has been selected, the Password Read and Password Program com- 2013 Microchip Technology Inc. Irreversible Block Locking Global Lock Bit should be ‘1’. The Irreversible Block Lock command is disabled when Global Lock Bit is ‘0’. Enter the Non-Volatile Block Protection mode. Use the NVPB Program command to protect only the blocks that are to be changed into ROM. Exit the Non-Volatile Block Protection mode. Issue the Irreversible Block Lock command (see Table 5-2 for details). The Irreversible Block Lock command can only be used once. Issuing the command after the first time has no effect on the device. Important: Once the Irreversible Block Lock command is used, the state of the NVPBs can no longer be changed or overridden. Therefore, the following features no longer have any effect on the device: • • • • • Global Lock of NVPBs feature Password feature NVPB Program command NVPB Erase command DQ2 and DQ1 of PSR In addition, WP# has no effect on any memory in the boot block area that has been irreversibly locked. Preliminary DS25002B-page 15 SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B To verify whether the Irreversible Block Lock command has already been issued, enter the Product ID mode and read address 5FEH. If DQ0 = 0, then Irreversible Block Lock has already been executed. When using this feature to determine if a specific block is ROM, use the NVPB Status Read. DS25002B-page 16 Preliminary 2013 Microchip Technology Inc. SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B 5.0 OPERATIONS TABLE 5-1: OPERATION MODES SELECTION Mode CE# OE# WE# Read VIL VIL VIH RST# H WP# Program VIL VIH VIL H VIL/VIH1 DIN AIN Erase VIL VIH VIL H VIL/VIH1 X2 Block address, XXH for Chip-Erase Standby X DQ Address DOUT AIN VIH X X VIH X High Z X Write Inhibit X VIL X X X High Z/ DOUT X Product Identification X X VIH H X High Z/ DOUT X Reset X X X L X High Z X VIL VIH VIL H X See Table 5-2 See Table 5-2 Software Mode 1. WP# can be VIL when programming or erasing outside of the bootblock. WP# must be VIH when programming or erasing inside the bootblock area. 2. X can be VIL or VIH, but no other value. TABLE 5-2: Command Sequence SOFTWARE COMMAND SEQUENCE (SHEET 1 OF 3) 1st Bus Cycle Addr1 Data2 2nd Bus Cycle 3rd Bus Cycle 4th Bus Cycle Addr1 Data2 Addr1 Data2 Addr1 Data2 Data0 WA1 Data1 WA2 Data2 WA3 Data3 555H AAH 2AAH 55H 555H A0H WA Data XXH F0H 2AAH 55H BA 25H BA Read3 WA Data Page Read3 WA0 Word-Program Reset 5th Bus Cycle 6th Bus Cycle 7th Bus Cycle Addr1 Data2 Addr1 Data2 Addr1 Data2 WC WAX Data WAX Data Write-Buffer Programming Write-to-Buffer4 555H AAH Program Buffer-to- Flash BAX 29H Write-to-Buffer Abort-Reset 555H AAH 2AAH 55H 555H F0H Bypass Mode Entry 555H AAH 2AAH 55H 555H 20H Bypass WordProgram XXXH A0H WA Data Bypass Block Erase XXXH 80H BA 30H Bypass Chip Erase XXXH 80H 555H 10H Bypass Mode Exit XXXH 90H XXXH 00H 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H BAx 30H Chip-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H Erase Suspend XXXH B0H Erase Resume XXXH 30H WAX Data Bypass Mode5 Erase Related Block-Erase 2013 Microchip Technology Inc. Preliminary DS25002B-page 17 SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B TABLE 5-2: Command Sequence SOFTWARE COMMAND SEQUENCE (CONTINUED) (SHEET 2 OF 3) 1st Bus Cycle 2nd Bus Cycle 3rd Bus Cycle Addr1 Data2 Addr1 Data2 Addr1 Data2 SEC ID Entry6 555H AAH 2AAH 55H 555H 88H SEC ID Read3,7 WAX Data SEC ID Exit 555H AAH 2AAH 55H 555H 90H 2AAH 55H 555H 90H 555H E0H 555H C0H 4th Bus Cycle Addr1 Data2 XXH 00H 5th Bus Cycle Addr1 6th Bus Cycle Data2 Addr1 7th Bus Cycle Data2 Addr1 Data2 Security ID Product Identification Software ID Entry8 555H AAH Manufacturer ID3,9 X00 BFH Device ID3,9 X01 Data Read Block Protection Status3 BAX0210 Data11 Read Irreversible Block Lock Status3 5FEH Data12 Read Global Lock Bit Status3 9FFH Data13 Software ID Exit /CFI Exit14 XXH F0H Volatile Block Protection Volatile Block Protection Mode Entry 555H AAH 2AAH 55H Volatile Protection Bit (VPB) Set/ Clear XXH A0H BAX15 Data16 VPB Status Read3 BAX Data16 Volatile Block Protection Mode Exit XXH 90H XXH 00H Non-Volatile Block Protection Non-Volatile Block Protection Mode Entry 555H AAH 2AAH 55H Non-Volatile Protect Bit (NVPB) Program XXH A0H BAX15 00H Non-Volatile Protect Bits (NVPB) Erase17 XXH 80H 00H 30H NVPB Status Read3 BAX15 Data16 Non-Volatile Block Protection Mode Exit XXH 90H XXH 00H DS25002B-page 18 Preliminary 2013 Microchip Technology Inc. SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B TABLE 5-2: Command Sequence SOFTWARE COMMAND SEQUENCE (CONTINUED) (SHEET 3 OF 3) 1st Bus Cycle Addr1 2nd Bus Cycle 3rd Bus Cycle Data2 Addr1 Data2 Addr1 Data2 555H 50H 555H 60H 00H PWD0 555H 40H 555H 87H 4th Bus Cycle 5th Bus Cycle 6th Bus Cycle Addr1 Data2 Addr1 Data2 Addr1 01H PWD1 02H PWD2 03H XXH 00H 7th Bus Cycle Data2 Addr1 Data2 Global Lock of NVPBs Global Lock of NVPBs Entry 555H AAH 2AAH 55H Set Global Lock Bit XXH A0H XXH 00H Global Lock Bit Status Read3 XXXH Data13 Global Lock of NVPBs Exit XXH 90H XXH 00H Password Commands Password Commands Mode Entry 555H AAH 2AAH 55H Password Program18 XXH A0H PWAX PWDX PWAX PWDX Submit Password19 00H 25H 00H 03H Password Commands Mode Exit XXH 90H XXH 00H Password Read3 PWD3 00H 29H Program and Settings Register (PSR) PSR Entry 555H AAH 2AAH 55H PSR Program PSR Read3 XXH A0H XXXH Data XXH Data PSR Exit XXH 90H XXH 00H CFI Query Entry 55H 98H Software ID Exit/CFI Exit14 XXH F0H 2AAH 55H CFI Irreversible Block Lock Irreversible Block Lock20 555H AAH 1. Address format A10-A0 (Hex). Addresses A11- A21 can be VIL or VIH, but no other value, for the SST38VF6401B/6402B/ 6403B/6404B command sequence. 2. DQ15-DQ8 can be VIL or VIH, but no other value, for command sequence 3. All read commands are in Bold Italics. 4. Total number of cycles in this command sequence depends on the number of words to be written to the buffer. Additional words are written by repeating Write Cycle 5. Address (WAX) values for Write Cycle 6 and later must have the same A21-A4 values as WAX in Write Cycle 5. WC = Word Count. The value of WC is the number of words to be written into the buffer, minus 1. Maximum WC value is 15 (i.e. F Hex) 5. Erase-Suspend and Erase-Resume commands are also available in Bypass Mode. 6. Once in SEC ID mode, the Word-Program, Write-Buffer Programming, and Bypass Word-Program features can be used to program the SEC ID area. 7. Lock-out Status is read with A7-A0 = FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0. Lock status can also be checked by reading Bit ‘0’ in the PSR. 8. The device does not remain in Software Product ID Mode if powered down. 9. With AMS-A1 =0; Microchip Manufacturer ID = 00BFH, is read with A0 = 0, SST38VF6401B/6402B/6403B/6404B Device IDs are read with the results shown in Table 4-3 on page 12. 10. BAX02: AMS-A15 = Block Address; A14-A8 = xxxxxx; A7-A0 = 02 2013 Microchip Technology Inc. Preliminary DS25002B-page 19 SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B 11. Data = 00H unprotected block; Data = 01H protected block. 12. DQ0 = 0 means the Irreversible Block Lock command has been previously used. DQ0 = 1 means the Irreversible Block Lock command has not yet been used. 13. DQ0 = 0 means that the Global Lock Bit is locked. DQ0 = 1 means that the Global Lock Bit is unlocked. 14. Both Software ID Exit operations are equivalent. 15. For Non-Uniform Boot Block devices (i.e. 8 KWord size), in the boot area, use BAX = Block Address. 16. DQ0 = 0 means protected; DQ0 = 1 means unprotected 17. Erases all NVPBs to ‘1’ (unprotected) 18. Entire two-bus cycle sequence must be entered for each portion of the password. 19. Entire password sequence required for validation. The word order doesn’t matter as long as the Address and Data pair match. 20. Global Lock Bit must be ‘1’ before executing this command. Note: Table 5-2 uses the following abbreviations: X = Don’t care (VIL or VIH, but no other value. BAX= Block Address; uses AMS-A15 address lines WA = Word Address WC = Word Count PWAX = Password Address; PWAX = PWA0, PWA1, PWA2 or PWA3; A1 and A0 are used to select each 16-bit portion of the password PWDX = Password Data; PWDX = PSWD0, PWD1, PWD2, or PWD3 AMS = Most significant Address TABLE 5-3: PROTECTION PRIORITY FOR MAIN ARRAY NVPB1 VPB1 Protection State of Block protect X protected X protect protected unprotect unprotect unprotected 1. X = protect or unprotect CFI QUERY IDENTIFICATION STRING1 FOR SST38VF6401B/6402B/6403B/6404B TABLE 5-4: Address Data Description 10H 0051H Query Unique ASCII string “QRY” 11H 0052H 12H 0059H 13H 0002H 14H 0000H 15H 0040H 16H 0000H 17H 0000H 18H 0000H 19H 0000H 1AH 0000H Primary OEM command set Address for Primary Extended Table Alternate OEM command set (00H = none exists) Address for Alternate OEM Extended Table (00H = none exits) 1. Refer to CFI publication 100 for more details. DS25002B-page 20 Preliminary 2013 Microchip Technology Inc. SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B TABLE 5-5: SYSTEM INTERFACE INFORMATION FOR SST38VF6401B/6402B/6403B/6404B Address Data Description 1BH 0027H VDD Min (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts 1CH 0036H VDD Max (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts 1DH 0000H VPP min. (00H = no VPP pin) 1EH 0000H VPP max. (00H = no VPP pin) 1FH 0003H Typical time out for Word-Program 2N µs (23 = 8 µs) 20H 0003H Typical time out for min. size buffer program 2N µs (00H = not supported) 21H 0004H Typical time out for individual Block-Erase 2N ms (24 = 16 ms) 22H 0005H Typical time out for Chip-Erase 2N ms (25 = 32 ms) 23H 0001H Maximum time out for Word-Program 2N times typical (21 x 23 = 16 µs) 24H 0003H Maximum time out for buffer program 2N times typical 25H 0001H Maximum time out for individual Block-Erase 2N times typical (21 x 24 = 32 ms) 26H 0001H Maximum time out for Chip-Erase 2N times typical (21 x 25 = 64 ms) TABLE 5-6: DEVICE GEOMETRY INFORMATION FOR SST38VF6401B/6402B/6403B/6404B Address Data Description 27H 0017H Device size = 2N Bytes (17H = 23; 223 = 8 MByte) 28H 0001H Flash Device Interface description; 0001H = x16-only asynchronous interface 29H 0000H 2AH 0005H Maximum number of bytes in multi-byte write = 2N (00H = not supported) 2BH 0000H 2CH 000xH Number of Erase Block regions in the device (01H = uniform boot device, 02H = non-uniform boot device. 2DH 00xxH Erase Block Region 1 Information 007FH, 0000H, 0000H, 0001H, for SST38VF6401B/6402B 0007H, 0000H, 0020H, 0000H for SST38VF6403B/6404B 2EH 000xH 2FH 00x0H 30H 000xH 31H 32H 33H Erase Block Region 2 Information 0000H, 0000H, 0000H, 0000H, for SST38VF6401B/6402B 007EH, 0000H, 0000H, 0001H for SST38VF6403B/6404B 34H 2013 Microchip Technology Inc. Preliminary DS25002B-page 21 SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B TABLE 5-7: Address PRIMARY VENDOR-SPECIFIC EXTENDED INFORMATION FOR SST38VF6401B/ 6402B/6403B/6404B Data Description 40H 0050H Query-unique ASCII string “PRI” 41H 0052H 42H 0049H 43H FFFFH Reserved 44H FFFFH Reserved 45H 0000H Reserved 46H 0002H Erase Suspend 0 = Not supported 1 = Only read during Erase Suspend, 2 = Read and Program during Erase Suspend. 47H 0001H Individual Block Protection 0 = Not supported 1 = Supported 48H 0000H Reserved 49H 0008H Protection 0008H = Advanced 4AH 0000H Simultaneous Operation 00 = Not supported 4BH 0000H Burst Mode 00 = Not supported 4CH 0002H Page Mode 00 = Not supported 02 = 8 Word page. 4DH 0000H Acceleration Supply Minimum 00 = Not supported 4EH 0000H Acceleration Supply Maximum 00 = Not supported 4FH 00XXH Top / Bottom Boot Block 02H = 8 KWord Bottom Boot 03H = 8 KWord Top Boot 04H = Uniform (32 KWord) Bottom Boot 05H = Uniform (32 KWord) Top Boot 50H 0000H Program Suspend 00H = Not Supported 01H = Supported DS25002B-page 22 Preliminary 2013 Microchip Technology Inc. SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . .-2.0V to VDD+2.0V Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 12.5V Voltage on RST# Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 12.5V Voltage on WP# Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 12.5V Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA 1. Outputs shorted for no more than one second. No more than one output shorted at a time. TABLE 5-8: Range Commercial Industrial OPERATING RANGE Ambient Temp TABLE 5-9: AC CONDITIONS OF TEST1 VDD Input Rise/Fall Time Output Load 0°C to +70°C 2.7-3.6V 5ns CL = 30 pF -40°C to +85°C 2.7-3.6V 2013 Microchip Technology Inc. 1. See Figures 6-17 and 6-18 Preliminary DS25002B-page 23 SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B 5.1 Power-Up Specifications All functionalities and DC specifications are specified for a VDD ramp rate faster than 1V per 100 ms (0V to 3V in less than 300 ms). If the VDD ramp rate is slower than 1V per 100 ms, a hardware reset is required. The TABLE 5-10: recommended VDD power-up to RESET# high time should be greater than 100 µs to ensure a proper reset. See Table 5-10and Figure 5-1 for more information. RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter Minimum Units TPU-READ1 Power-up to Read Operation 100 µs TPU-WRITE1 Power-up to Erase/Program Operation 100 µs 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TPU-READ > 100 µs VDD min VDD 0V VIH RESET# TRHR > 50ns CE# 25002 F37.0 FIGURE 5-1: DS25002B-page 24 POWER-UP DIAGRAM Preliminary 2013 Microchip Technology Inc. SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B 5.2 DC Characteristics TABLE 5-11: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V1 Limits Symbol Parameter IDD Min Max Units Test Conditions Address input=VILT/VIHT2, VDD=VDD Max Power Supply Current Read3 30 mA CE#=VIL, OE#=WE#=VIH at f= 5 MHz Intra-Page Read @5 MHz 2.5 mA CE#=VIL, OE#=WE#=VIH Intra-Page Read @40 MHz 20 mA CE#=VIL, OE#=WE#=VIH Program and Erase 35 mA CE#=WE#=VIL, OE#=VIH Program-Write-Bufferto-Flash 50 mA CE#=WE#=VIL, OE#=VIH ISB Standby VDD Current 40 µA CE#=VIHC, VDD=VDD Max IALP Auto Low Power 40 µA CE#=VILC, VDD=VDD Max All inputs=VSS or VDD, WE#=VIHC ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max ILIW Input Leakage Current on WP# pin and RST# 10 µA WP#=GND to VDD or RST#=GND to VDD ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max VIL Input Low Voltage 0.8 V VDD=VDD Min VILC Input Low Voltage (CMOS) 0.3 V VDD=VDD Max VIH Input High Voltage 0.7VDD V VDD=VDD Max VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max VOL Output Low Voltage VOH Output High Voltage 0.2 VDD-0.2 V IOL=100 µA, VDD=VDD Min V IOH=-100 µA, VDD=VDD Min 1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C (room temperature), and VDD = 3V. Not 100% tested. 2. See Figure 6-22 3. The IDD current listed is typically less than 2mA/MHz, with OE# at VIH. Typical VDD is 3V. TABLE 5-12: CAPACITANCE (TA = 25°C, F=1 MHZ, OTHER PINS OPEN) Parameter Description CI/O1 CIN1 Test Condition Maximum I/O Pin Capacitance VI/O = 0V 12 pF Input Capacitance VIN = 0V 6 pF 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 5-13: RELIABILITY CHARACTERISTICS Symbol Parameter Minimum Specification Units Test Method NEND1,2 Endurance 100,000 Cycles JEDEC Standard A117 TDR1 Data Retention 100 Years JEDEC Standard A103 ILTH1 Latch Up 100 + IDD mA JEDEC Standard 78 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. NEND endurance rating is qualified as 100,000 cycles minimum per block. 2013 Microchip Technology Inc. Preliminary DS25002B-page 25 SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B 6.0 AC CHARACTERISTICS TABLE 6-1: READ CYCLE TIMING PARAMETERS VDD = 2.7-3.6V Symbol Parameter TRC Read Cycle Time Min Max TCE Chip Enable Access Time 70 ns TAA Address Access Time 70 ns 25 ns 70 Units ns TPACC Page Access Time TOE Output Enable Access Time TCLZ1 CE# Low to Active Output 0 TOLZ1 OE# Low to Active Output 0 TCHZ1 CE# High to High-Z Output 20 ns TOHZ1 OE# High to High-Z Output 20 ns TOH 1 25 Output Hold from Address Change ns ns ns 0 ns TRP1 RST# Pulse Width 500 ns TRHR1 RST# High before Read 50 ns TRYE1,2 RST# Pin Low to Read Mode 20 µs TRY1 RST# Pin Low to Read Mode – not during Program or Erase algorithms. 500 ns TRPD1 RST# Input Low to Standby mode TRB 1 TPWD 20 µs RY / BY# Output high to CE# / OE# pin Low 0 ns Delay for each password check 1 µs 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. This parameter applies to Block-Erase and Program operations. This parameter does not apply to Chip-Erase operations. DS25002B-page 26 Preliminary 2013 Microchip Technology Inc. SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B TABLE 6-2: PROGRAM/ERASE CYCLE TIMING PARAMETERS Symbol Parameter Min Max Units TBP Word-Program Time 10 µs TWBP1 Program Buffer-to-Flash Time 40 µs TAS Address Setup Time 0 ns TAH Address Hold Time 30 ns TCS WE# and CE# Setup Time 0 ns TCH WE# and CE# Hold Time 0 ns TOES OE# High Setup Time 0 ns TOEH OE# High Hold Time 10 ns TCP CE# Pulse Width 40 ns TWP WE# Pulse Width 40 ns TWPH2 WE# Pulse Width High 30 ns TCPH2 CE# Pulse Width High 30 ns TDS Data Setup Time 30 ns TCEPH CE# Pulse Width High During Toggle Bit Polling 20 ns ns TOEPH OE# Pulse Width High During Toggle bit Polling 20 TDH2 Data Hold Time 0 TIDA2 Software ID, Volatile Protect, Non-Volatile Protect, Global Lock Bit, Password mode, Lock Bit, Bypass Entry, and Exit Times 150 ns TBE Block-Erase 25 ms TSCE Chip-Erase 50 ms TBUSY 2 CE# High or WE# High to RY / BY# Low 90 ns ns 1. Effective programming time is 2.5 µs per word if 16-words are programmed during this operation. 2. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2013 Microchip Technology Inc. Preliminary DS25002B-page 27 SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B TAA TRC ADDRESS AMS-0 TCE CE# TOE OE# WE# DQ15-0 TOHZ TOLZ VIH TCLZ TCHZ TOH HIGH-Z DATA VALID DATA VALID HIGH-Z TRB RY/BY# 25002 F03.1 Note: AMS = Most significant address AMS = A21 for SST38VF6401B/6402B/6403B/6404B FIGURE 6-1: READ CYCLE TIMING DIAGRAM Same Page ADDRESS AMS-3 Ax A2 - A0 Ax TPACC TAA DQ15-0 Ax Ax TPACC DATA VALID DATA VALID TPACC DATA VALID CE# OE# RY/BY# 25002 F24.3 Note: AMS = Most significant address AMS = A21 for SST38VF6401B/6402B/6403B/6404B AX = either 000, 001,... 111 FIGURE 6-2: DS25002B-page 28 PAGE READ TIMING DIAGRAM Preliminary 2013 Microchip Technology Inc. SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B INTERNAL PROGRAM OPERATION STARTS TBP ADDRESS AMS-0 555 TAH 2AA 555 ADDR TWP TDH WE# TDS TWPH TAS OE# TCH CE# TCS DQ15-0 XXAA XX55 XXA0 SW0 SW1 SW2 DATA WORD (ADDR/DATA) RY/BY# TBUSY Note: AMS = Most significant address AMS = A21 for SST38VF6401B/6402B/6403B/6404B WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence. X can be VIL or VIH, but no other value. FIGURE 6-3: 25002 F04.1 WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM 2013 Microchip Technology Inc. Preliminary DS25002B-page 29 SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B INTERNAL PROGRAM OPERATION STARTS TBP ADDRESS AMS-0 555 TAH 2AA 555 ADDR TCP TDH CE# TDS TCPH TAS OE# TCH WE# TCS DQ15-0 XXAA XX55 XXA0 SW0 SW1 SW2 DATA WORD (ADDR/DATA) RY/BY# TBUSY Note: AMS = Most significant address AMS = A21 for SST38VF6401B/6402B/6403B/6404B WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence. X can be VIL or VIH, but no other value. FIGURE 6-4: 25002 F05.1 CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM FILL WRITE BUFFER WITH DATA ADDRESS AMS-0 555 2AA BA BA WAX WAX CE# OE# TWP WE# DQ15-0 XXAA XX55 XX25 WC SW0 SW1 SW2 SW3 DATA SW4 DATAn SWn RY/BY# 25002 F34.2 Note: BA= Block Address WAx = Word Address WC = Word Count DATAn = nth Data X can be VIL or VIH, but no other value. FIGURE 6-5: DS25002B-page 30 WE# CONTROLLED WRITE-BUFFER CYCLE TIMING DIAGRAM Preliminary 2013 Microchip Technology Inc. SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B TWBP BA ADDRESS AMS-0 CE# OE# TWP WE# TAS TDH DQ15-0 29H TBusy RY/BY# 25002 F35.1 Note: BA= Block Address FIGURE 6-6: WE# CONTROLLED PROGRAM-WRITE-BUFFER-TO-FLASH CYCLE TIMING DIAGRAM ADDRESS AMS-0 TCE CE# TOEH TOES OE# TOE WE# DQ7 DATA DATA# DATA# DATA 25002 F06.1 Note: AMS = Most significant address AMS = A21 for SST38VF6401B/6402B/6403B/6404B FIGURE 6-7: DATA# POLLING TIMING DIAGRAM 2013 Microchip Technology Inc. Preliminary DS25002B-page 31 SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B ADDRESS AMS-0 TCEPH TCE CE# TOEPH TOEH TOES OE# TOE WE# DQ6 and DQ2 TWO READ CYCLES WITH SAME OUTPUTS 25002 F07.0 Note: AMS = Most significant address AMS = A21 for SST38VF6401B/6402B/6403B/6404B FIGURE 6-8: TOGGLE BITS TIMING DIAGRAM TSCE SIX-BYTE CODE FOR CHIP-ERASE ADDRESS AMS-0 555 2AA 555 555 2AA 555 CE# OE# TWP WE# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX10 SW0 SW1 SW2 SW3 SW4 SW5 TBUSY RY/BY# 25002 F08.1 Note: This device also supports CE# controlled Chip-Erase operation The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 6-2) AMS = Most significant address AMS = A21 for SST38VF6401B/6402B/6403B/6404B WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence. X can be VIL or VIH, but no other value. FIGURE 6-9: DS25002B-page 32 WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM Preliminary 2013 Microchip Technology Inc. SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B TBE SIX-BYTE CODE FOR BLOCK-ERASE ADDRESS AMS-0 555 2AA 555 555 2AA BAX CE# OE# TWP WE# DQ15-0 XXAA XX55 XX80 XXAA XX55 SW0 SW1 SW2 SW3 SW4 XX30 SW5 TBusy RY/BY# 25002 F09.1 Note: This device also supports CE# controlled Block-Erase operation The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 6-2) BAX = Block Address AMS = Most significant address AMS = A21 for SST38VF6401B/6402B/6403B/6404B WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence. X can be VIL or VIH, but no other value. FIGURE 6-10: WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM 2013 Microchip Technology Inc. Preliminary DS25002B-page 33 SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B Three-Byte Sequence for Software ID Entry ADDRESS AMS-0 555 2AA 555 0000 0001 CE# OE# TIDA TWP WE# TAA TWPH DQ15-0 XXAA SW0 XX55 SW1 XX90 00BF Device ID SW2 25002 F11.0 Note: Device ID = 536B for SST38VF6401B, 536A for SST38VF6402B, 536D for SST38VF6403B, 536C for SST38VF6404B AMS = Most significant address AMS = A21 for SST38VF6401B/6402B/6403B/6404B WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence. X can be VIL or VIH, but no other value. FIGURE 6-11: ADDRESS AMS-0 SOFTWARE ID ENTRY AND READ 55H CE# OE# TWP TIDA WE# TAA DQ15-0 98H 25002 F12.2 Note: WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence. AMS = Most significant address AMS = A21 for SST38VF6401B/6402B/6403B/6404B X can be VIL or VIH, but no other value. FIGURE 6-12: DS25002B-page 34 CFI QUERY ENTRY AND READ Preliminary 2013 Microchip Technology Inc. SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B ONE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET ADDRESS AMS-0 DQ15-0 XXF0 TIDA CE# OE# TWP WE# TWHP SW0 25002 F13.1 Note: WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence. AMS = Most significant address AMS = A21 for SST38VF6401B/6402B/6403B/6404B X can be VIL or VIH, but no other value. FIGURE 6-13: SOFTWARE ID EXIT/CFI EXIT THREE-BYTE SEQUENCE FOR SEC ID ENTRY ADDRESS AMS-0 555 2AA 555 CE# OE# TIDA TWP WE# TWPH DQ15-0 TAA XXAA XX55 XX88 SW0 SW1 SW2 25002 F14.1 Note: AMS = Most significant address AMS = A21 for SST38VF6401B/6402B/6403B/6404B WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence. X can be VIL or VIH, but no other value. FIGURE 6-14: SEC ID ENTRY 2013 Microchip Technology Inc. Preliminary DS25002B-page 35 SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B TRY TRP RST# TRHR CE#/OE# RY/BY# 25002 F15.2 FIGURE 6-15: RST# TIMING DIAGRAM (WHEN NO INTERNAL OPERATION IS IN PROGRESS) TRP RST# TRYE CE#/OE# TRB RY/BY# 25002 F16.2 FIGURE 6-16: RST# TIMING DIAGRAM (DURING PROGRAM OR ERASE OPERATION) VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT VILT 25002 F17.0 AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test FIGURE 6-17: DS25002B-page 36 AC INPUT/OUTPUT REFERENCE WAVEFORMS Preliminary 2013 Microchip Technology Inc. SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B VDD TO TESTER 25KΩ TO DUT CL 25KΩ 25002 F18.1 FIGURE 6-18: A TEST LOAD EXAMPLE 2013 Microchip Technology Inc. Preliminary DS25002B-page 37 SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B Start Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Load data: XXA0H Address: 555H Load Word Address Word Data Wait for end of Program Program Complete 25002 F19.1 Note: X can be VIL or VIH, but no other value. FIGURE 6-19: DS25002B-page 38 WORD-PROGRAM ALGORITHM Preliminary 2013 Microchip Technology Inc. SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B Start Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Load data: XX25H Address: BA Load data: WC Address: BA Load data: Data Address: WA Keep writing to buffer No Is Data Load complete? Yes Program Buffer to Flash Load data: XX29H Address: BA Wait for end of Program Program Complete 25002 F25.2 Note: BA= Block Address WC = Word Count WA = Address of word to program All subsequent Address values (WAX) in Write Cycle 6 and later must have the same A21-A4 as WAX in Write Cycle 5. X can be VIL or VIH, but no other value FIGURE 6-20: WRITE-BUFFER PROGRAMMING 2013 Microchip Technology Inc. Preliminary DS25002B-page 39 SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B Internal Timer Toggle Bit Data# Polling RY/BY# Program/Erase Initiated Program/Erase Initiated Program/Erase Initiated Program/Erase Initiated Wait TBP, TWBP, TSCE, or TBE Read word Read DQ7 Read RY/BY# Read same word Program/Erase Completed No Is DQ7 = true data? Yes No Does DQ6 match? Program/Erase Completed No Is RY/BY# = 1? Yes Program/Erase Completed Yes Program/Erase Completed 25002 F20.1 Note: For a Program Buffer-to-Flash Operation, the valid DQ7 is from the last word loaded in the buffer using the Writeto-Program Buffer command. FIGURE 6-21: DS25002B-page 40 WAIT OPTIONS Preliminary 2013 Microchip Technology Inc. SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B CFI Query Entry Command Sequence Sec ID Entry Command Sequence Software Product ID Entry Command Sequence Load data: XX98H Address: 555H Load data: XXAAH Address: 555H Load data: XXAAH Address: 555H Wait TIDA Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Read CFI data Load data: XX88H Address: 555H Load data: XX90H Address: 555H Wait TIDA Wait TIDA Read Sec ID Read Software ID 25002 F21.0 Note: X can be VIL or VIH, but no other value. FIGURE 6-22: CFI/SEC ID/SOFTWARE ID ENTRY COMMAND FLOWCHARTS 2013 Microchip Technology Inc. Preliminary DS25002B-page 41 SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B CFI Exit Command Sequence SEC ID Exit Command Sequence Load data: XXF0H Address: XXH Load data: XXAAH Address: 555H Wait TIDA Load data: XX55H Address: 2AAH Return to normal operation Load data: XX90H Address: 555H Load data: XX00H Address: XXXH Wait TIDA Return to normal operation 25002 F26.2 Note: X can be VIL or VIH, but no other value. FIGURE 6-23: DS25002B-page 42 SOFTWARE ID/CFI/SEC ID EXIT COMMAND FLOWCHARTS Preliminary 2013 Microchip Technology Inc. SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B Chip-Erase Command Sequence Block-Erase Command Sequence Load data: XXAAH Address: 555H Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX80H Address: 555H Load data: XX80H Address: 555H Load data: XXAAH Address: 555H Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX10H Address: 555H Load data: XX30H Address: BAX Wait TSCE Wait TBE Chip erased to FFFFH Block erased to FFFFH 25002 F23.0 Note: X can be VIL or VIH, but no other value. BA= Block Address FIGURE 6-24: ERASE COMMAND SEQUENCE 2013 Microchip Technology Inc. Preliminary DS25002B-page 43 SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B Start Erase Operation Load data: XXB0H Address: XXXH Wait Time (20 µs max) Erase Suspend Active Execute valid operations while in Erase Suspend mode Load data: XX30H Address: XXXH Resume Erase Operation 25002 F27.0 Note: X can be VIL or VIH, but no other value. FIGURE 6-25: DS25002B-page 44 ERASE SUSPEND/RESUME Preliminary 2013 Microchip Technology Inc. SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Load data: XXE0H Address: 555H Wait TIDA Protect / Unprotect Read Protect Status Load data: XXA0H Address: 555H Read data: Data Address: BA Load data: Data Address: BA Yes More Blocks to protect/unprotect or Read status? No Load data: XX90H Address: XXXH Load data: XX00H Address: XXXH Note: Data = 00H (unprotect); Data = 01H (protect). BA = Block Address X can be VIL or VIH, but no other value. FIGURE 6-26: 25003 F28.3 VOLATILE BLOCK PROTECTION 2013 Microchip Technology Inc. Preliminary DS25002B-page 45 SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Load data: XXC0H Address: 555H Wait TIDA Program, Erase or Read Program (Protect Block) Erase Read Protect Status Load data: XXA0H Address: XXH Load data: XX80H Address: XXH Read data: Data Address: BA Load data: XX00H Address: BA Load data: XX30H Address: 00H Wait for end of Program, Erase, or Read More to Program,Erase, or Read? Yes No Load data: XX90H Address: XXH Load data: XX00H Address: XXH 25002 F30.1 Note: Data = 00H (unprotect); Data = 01H (protect). X can be VIL or VIH, but no other value. Programming NVPB requires 2x TBP, which results in a 20µs maximum programming time FIGURE 6-27: DS25002B-page 46 NON-VOLATILE BLOCK PROTECT MODE Preliminary 2013 Microchip Technology Inc. SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Load data: XX50H Address: 555H Wait TIDA Set Read Status Load data: XXA0H Address: XXH Read data: Status Data Address: XXXH Load data: XX00H Address: XXH Load data: XX90H Address: XXH Load data: XX00H Address: XXH 25002 F31.0 Note: Status Data: DQ0 = 0 (locked); DQ0 = 1 (unlocked). X can be VIL or VIH, but no other value. FIGURE 6-28: GLOBAL LOCK OF NVPBS 2013 Microchip Technology Inc. Preliminary DS25002B-page 47 SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B Program / Read Password Submit Password Load data: XXAAH Address: 555H Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX60H Address: 555H Load data: XX60H Address: 555H Wait TIDA Wait TIDA Load data: XX25H Address: 00H Program Read Load data: XXA0H Address: XXH Read data: Status Data Address: PWAX Load data: PWDX Address: PWAX Load data: XX03H Address: 00H Load data: PWD0 Address: PWA0 Load data: PWD1 Address: PWA1 Load data: PWD2 Address: PWA2 Yes Load data: PWD3 Address: PWA3 More to Program or Read? Load data: XX29H Address: 00H No Wait TPWD Load data: XX90H Address: XXH Load data: XX90H Address: XXH Load data: XX00H Address: XXH Load data: XX00H Address: XXH Note: The PWDX and PWAX data and address pairs can be submitted in any order. PWDX = PWD0, PWD1, PWD2, PWD3 PWAX = PWA0, PWA1,PWA2, PWA3 X can be VIL or VIH, but no other value. FIGURE 6-29: DS25002B-page 48 Exit Password Command Mode 25002 F32.0 PASSWORD OPERATIONS (PROGRAM, READ, SUBMIT) Preliminary 2013 Microchip Technology Inc. SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B Load data: AAH Address: 555H Load data: 55H Address: 2AAH Load data: 87H Address: 555H Load data: 00H Address: XXH 25002 F33.0 Note: Global Lock Bit must be ‘1’ before executing this command. X can be VIL or VIH, but no other value. FIGURE 6-30: IRREVERSIBLE BLOCK LOCK IN MAIN ARRAY 2013 Microchip Technology Inc. Preliminary DS25002B-page 49 SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B 7.0 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. XXX XX XXX X Device Read Access Speed Endurance/ Temperature Package Tape/Reel Indicator Device: SST38VF6401B = 64 Mbit, 2.7-3.6V, Advanced MultiPurpose Flash Plus Bottom Boot-Block Uniform (32 KWord) SST38VF6402B = 64 Mbit, 2.7-3.6V, Advanced MultiPurpose Flash Plus Top Boot-Block Uniform (32 KWord) SST38VF6403B = 64 Mbit, 2.7-3.6V, Advanced MultiPurpose Flash Plus Bottom Boot-Block Non- Uniform (8 KWord) SST38VF6403B = 64 Mbit, 2.7-3.6V, Advanced MultiPurpose Flash Plus Top Boot-Block Non- Uniform (8 KWord) Tape and Reel Flag: T = Tape and Reel Read Access Speed: 70 = 70 ns Endurance: 5 = 100,000 cycles minimum Temperature: I = -40°C to +85°C Package: TV CD = TSOP (12mm x 20mm), 48-lead = TFBGA (6mm x 8mm), 48-lead TABLE 7-1: Valid Combinations: SST38VF6401B-70-5I-TV SST38VF6401BT-70-5I-TV SST38VF6401B-70-5I-CD SST38VF6401BT-70-5I-CD SST38VF6402B-70-5I-TV SST38VF6402BT-70-5I-TV SST38VF6402B-70-5I-CD SST38VF6402BT-70-5I-CD SST38VF6403B-70-5I-TV SST38VF6403BT-70-5I-TV SST38VF6403B-70-5I-CD SST38VF6403BT-70-5I-CD SST38VF6404B-70-5I-TV SST38VF6404BT-70-5I-TV SST38VF6404B-70-5I-CD SST38VF6404BT-70-5I-CD PART MARKING Ordering Number Marking On Part SST38VF6401B-70-5I-TV 38VF6401B-70-I/TV SST38VF6401B-70-5I-CD 38VF6401B-70-I/CD SST38VF6402B-70-5I-TV 38VF6402B-70-I/TV SST38VF6402B-70-5I-CD 38VF6402B-70-I/CD SST38VF6403B-70-5I-TV 38VF6403B-70-I/TV SST38VF6403B-70-5I-CD 38VF6403B-70-I/CD SST38VF6404B-70-5I-TV 38VF6404B-70-I/TV SST38VF6404B-70-5I-CD 38VF6404B-70-I/CD DS25002B-page 50 Preliminary 2013 Microchip Technology Inc. SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B 8.0 PACKAGING DIAGRAMS 2013 Microchip Technology Inc. Preliminary DS25002B-page 51 SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B DS25002B-page 52 Preliminary 2013 Microchip Technology Inc. SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B 2013 Microchip Technology Inc. Preliminary DS25002B-page 53 SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B DS25002B-page 54 Preliminary 2013 Microchip Technology Inc. SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B TABLE 8-1: REVISION HISTORY Number Description Date A • Initial release Aug 2011 B • • • • Applied new document format Revised Table 5-7 and Table 6-2 Updated “Product Identification System” on page 50 Migrated to new package drawing style Jan 2013 2013 Microchip Technology Inc. Preliminary DS25002B-page 55 SST38VF6401B / SST38VF6402B / SST38VF6403B / SST38VF6404B THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: Users of Microchip products can receive assistance through several channels: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQs), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives • • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://microchip.com/support CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions. DS25002B-page 56 Preliminary 2013 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MTP, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. Analog-for-the-Digital Age, Application Maestro, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. & KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2013, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-62076-905-8 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2013 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. Preliminary DS25002B-page 57 Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Japan - Osaka Tel: 81-66-152-7160 Fax: 81-66-152-9310 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 2013 Microchip Technology Inc. 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