32 Mbit (x16) Multi-Purpose Flash SST39VF320 Preliminary Specifications SST39VF3202.7V 32Mb (x16) MPF memory FEATURES: • Organized as 2M x16 • Single 2.7-3.6V Read and Write Operations • Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention • Low Power Consumption (typical values at 5 MHz) – Active Current: 9 mA (typical) – Standby Current: 3 µA (typical) – Auto Low Power Mode: 3 µA (typical) • Sector-Erase Capability – Uniform 2 KWord sectors • Block-Erase Capability – Uniform 32 KWord blocks • Fast Read Access Time – 70 ns – 90 ns • Latched Address and Data • Fast Erase and Word-Program – Sector-Erase Time: 18 ms (typical) – Block-Erase Time: 18 ms (typical) – Chip-Erase Time: 40 ms (typical) – Word-Program Time: 7 µs (typical) – Chip Rewrite Time: 15 seconds (typical) • Automatic Write Timing – Internal VPP Generation • End-of-Write Detection – Toggle Bit – Data# Polling • CMOS I/O Compatibility • JEDEC Standard – Flash EEPROM Pinouts and command sets • Packages Available – 48-lead TSOP (12mm x 20mm) – 48-ball TFBGA (6mm x 8mm) PRODUCT DESCRIPTION The SST39VF320 devices are 2M x16 CMOS Multi-Purpose Flash (MPF) manufactured with SST's proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39VF320 write (Program or Erase) with a 2.7-3.6V power supply. Featuring high performance Word-Program, the SST39VF320 devices provide a typical Word-Program time of 7 µsec. The devices use Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, these devices have on-chip hardware and software data protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, the SST39VF320 are offered with a guaranteed typical endurance of 100,000 cycles. Data retention is rated at greater than 100 years. The SST39VF320 devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, the SST39VF320 significantly improve performance and reliability, while lowering power consumption. The SST39VF320 inherently use less energy during Erase and Program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to pro©2003 Silicon Storage Technology, Inc. S71143-02-000 11/03 1 gram and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. The devices also improve flexibility while lowering the cost for program, data, and configuration storage applications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. To meet high density, surface mount requirements, the SST39VF320 is offered in 48-lead TSOP and 48-ball TFBGA packages. See Figures 1 and 2 for pinouts. Device Operation Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 32 Mbit Multi-Purpose Flash SST39VF320 Preliminary Specifications is based on uniform block size of 32 KWord. The SectorErase operation is initiated by executing a six-byte command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-ofErase operation can be determined using either Data# Polling or Toggle Bit methods. See Figures 9 and 10 for timing waveforms. Any commands issued during the Sectoror Block-Erase operation are ignored. The SST39VF320 also have the Auto Low Power mode which puts the device in a near standby mode after data has been accessed with a valid Read operation. This reduces the IDD active read current from typically 9 mA to typically 3 µA. The Auto Low Power mode reduces the typical IDD active read current to the range of 2 mA/MHz of read cycle time. The device exits the Auto Low Power mode with any address transition or control signal transition used to initiate another Read cycle, with no access time penalty. Note that the device does not enter Auto Low Power mode after power-up with CE# held steadily low until the first address transition or CE# is driven high. Read The Read operation of the SST39VF320 is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 3). Chip-Erase Operation The SST39VF320 provide a Chip-Erase operation, which allows the user to erase the entire memory array to the “1” state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 8 for timing diagram, and Figure 19 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. Word-Program Operation The SST39VF320 are programmed on a word-by-word basis. Before programming, the sector where the word exists must be fully erased. The Program operation is accomplished in three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 10 µs. See Figures 4 and 5 for WE# and CE# controlled Program operation timing diagrams and Figure 16 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored. Write Operation Status Detection The SST39VF320 provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Sector/Block-Erase Operation The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or block-byblock) basis. The SST39VF320 offer both Sector-Erase and Block-Erase modes. The sector architecture is based on uniform sector size of 2 KWord. The Block-Erase mode ©2003 Silicon Storage Technology, Inc. S71143-02-000 2 11/03 32 Mbit Multi-Purpose Flash SST39VF320 Preliminary Specifications Data# Polling (DQ7) Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence. This group of devices are shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode within TRC. The contents of DQ15-DQ8 can be VIL or VIH, but no other value, during any SDP command sequence. When the SST39VF320 are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. Note that even though DQ7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µs. During internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 6 for Data# Polling timing diagram and Figure 17 for a flowchart. Common Flash Memory Interface (CFI) The SST39VF320 also contain the CFI information to describe the characteristics of the device. In order to enter the CFI Query mode, the system must load the three-byte sequence, similar to the Software ID Entry command. The last byte cycle of this command loads 98H (CFI Query command) to address 5555H. Once the device enters the CFI Query mode, the system can read CFI data at the addresses given in Tables 5 through 7. The system must write the CFI Exit command to return to Read mode from the CFI Query mode. Toggle Bit (DQ6) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating 1s and 0s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 7 for Toggle Bit timing diagram and Figure 17 for a flowchart. Product Identification The Product Identification mode identifies the devices as the SST39VF320 and manufacturer as SST. This mode may be accessed by software operations. Users may use the Software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Table 4 for software operation, Figure 11 for the Software ID Entry and Read timing diagram, and Figure 18 for the Software ID Entry command sequence flowchart. Data Protection The SST39VF320 provide both hardware and software features to protect nonvolatile data from inadvertent writes. TABLE 1: PRODUCT IDENTIFICATION Hardware Data Protection Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle. Manufacturer’s ID VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. SST39VF320 Address Data 0000H 00BFH 0001H 2783H Device ID T1.1 1143 Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. Product Identification Mode Exit/ CFI Mode Exit In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read mode. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit/ Software Data Protection (SDP) The SST39VF320 provide the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent ©2003 Silicon Storage Technology, Inc. S71143-02-000 3 11/03 32 Mbit Multi-Purpose Flash SST39VF320 Preliminary Specifications CFI Exit command is ignored during an internal Program or Erase operation. See Table 4 for software command codes, Figure 13 for timing waveform, and Figure 18 for a flowchart. FUNCTIONAL BLOCK DIAGRAM X-Decoder Memory Address SuperFlash Memory Address Buffer & Latches Y-Decoder CE# I/O Buffers and Data Latches Control Logic OE# WE# DQ15 - DQ0 SST39VF320 A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# NC NC NC NC A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1143 B1.1 SST39VF320 Standard Pinout Top View Die Up SST39VF320 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 NC VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VDD DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 1143 48-tsop EK P01.10 FIGURE 1: PIN ASSIGNMENTS FOR 48-LEAD TSOP ©2003 Silicon Storage Technology, Inc. S71143-02-000 4 11/03 32 Mbit Multi-Purpose Flash SST39VF320 Preliminary Specifications TOP VIEW (balls facing down) SST39VF320 5 4 3 2 1 A13 A12 A14 A15 A16 NC DQ15 VSS A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6 WE# NC NC A19 DQ5 DQ12 VDD DQ4 NC NC A18 A20 DQ2 DQ10 DQ11 DQ3 A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1 A3 A4 A2 A1 A0 CE# OE# VSS A B C D E F G 1143 48-tfbga B3K P02a.3 6 H FIGURE 2: PIN ASSIGNMENTS FOR 48-BALL TFBGA TABLE 2: PIN DESCRIPTION Symbol Pin Name Functions A20-A0 Address Inputs To provide memory addresses. During Sector-Erase A20-A11 address lines will select the sector. During Block-Erase A20-A15 address lines will select the block. DQ15-DQ0 Data Input/output To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. CE# Chip Enable To activate the device when CE# is low. OE# Output Enable To gate the data output buffers. WE# Write Enable To control the Write operations. VDD Power Supply To provide power supply voltage: VSS Ground NC No Connection 2.7-3.6V for SST39VF320 Unconnected pins. T2.2 1143 TABLE 3: OPERATION MODES SELECTION Mode CE# OE# WE# DQ Address Read VIL VIL VIH DOUT AIN Program VIL VIH VIL DIN AIN Erase VIL VIH VIL X1 Sector or Block address, XXH for Chip-Erase Standby VIH X X High Z X X VIL X High Z/ DOUT X X X VIH High Z/ DOUT X VIL VIL VIH Write Inhibit Product Identification Software Mode See Table 4 T3.1 1143 1. X can be VIL or VIH, but no other value ©2003 Silicon Storage Technology, Inc. S71143-02-000 5 11/03 32 Mbit Multi-Purpose Flash SST39VF320 Preliminary Specifications TABLE 4: SOFTWARE COMMAND SEQUENCE Command Sequence 1st Bus Write Cycle 2nd Bus Write Cycle 3rd Bus Write Cycle 4th Bus Write Cycle Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Word-Program 5555H AAH 2AAAH 55H 5555H A0H WA3 Data Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 5th Bus Write Cycle 6th Bus Write Cycle Addr1 Data2 Addr1 Data2 2AAAH 55H SAX4 30H 50H 10H Block-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H BAX4 Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 5555H AAH 2AAAH 55H 5555H 90H 5555H AAH 2AAAH 55H 5555H 98H XXH F0H 5555H AAH 2AAAH 55H 5555H F0H Software ID Entry5,6 CFI Query Entry5 Software ID /CFI Exit Exit7 Software ID Exit7 /CFI Exit T4.4 1143 1. Address format A14-A0 (Hex), Addresses AMS-A15 can be VIL or VIH, but no other value, for the Command sequence AMS = Most significant address AMS = A20 for SST39VF320 2. DQ15 - DQ8 can be VIL or VIH, but no other value, for the Command sequence 3. WA = Program word address 4. SAX for Sector-Erase; uses AMS-A11 address lines BAX, for Block-Erase; uses AMS-A15 address lines 5. The device does not remain in Software Product ID Mode if powered down. 6. With AMS-A1 =0; SST Manufacturer’s ID= 00BFH, is read with A0 = 0, SST39VF320 Device ID = 2783H, is read with A0 = 1. 7. Both Software ID Exit operations are equivalent TABLE 5: CFI QUERY IDENTIFICATION STRING1 FOR SST39VF320 Address 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH Data 0051H 0052H 0059H 0001H 0007H 0000H 0000H 0000H 0000H 0000H 0000H Data Query Unique ASCII string “QRY” Primary OEM command set Address for Primary Extended Table Alternate OEM command set (00H = none exists) Address for Alternate OEM extended Table (00H = none exits) T5.1 1143 1. Refer to CFI publication 100 for more details. ©2003 Silicon Storage Technology, Inc. S71143-02-000 6 11/03 32 Mbit Multi-Purpose Flash SST39VF320 Preliminary Specifications TABLE 6: SYSTEM INTERFACE INFORMATION FOR SST39VF320 Address Data 1BH 0027H Data 1CH 0036H VDD Max (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts 1DH 0000H VPP Min (00H = no VPP pin) VDD Min (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts 1EH 0000H VPP max (00H = no VPP pin) 1FH 0003H Typical time out for Word-Program 2N µs (23 = 8 µs) 20H 0000H Typical time out for min size buffer program 2N µs (00H = not supported) 21H 0004H Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms) 22H 0005H Typical time out for Chip-Erase 2N ms (25 = 32 ms) 23H 0001H Maximum time out for Word-Program 2N times typical (21 x 23 = 16 µs) 24H 0000H Maximum time out for buffer program 2N times typical 25H 0001H Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32 ms) 26H 0001H Maximum time out for Chip-Erase 2N times typical (21 x 25 = 64 ms) T6.3 1143 TABLE 7: DEVICE GEOMETRY INFORMATION Address 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H Data 0016H 0001H 0000H 0000H 0000H 0002H 00FFH 0003H 0010H 0000H 003FH 0000H 0000H 0001H FOR SST39VF320 Data Device size = 2N Bytes (16H = 22; 222 = 4MByte) Flash Device Interface description; 0001H = x16-only asynchronous interface Maximum number of bytes in multi-byte write = 2N (00H = not supported) Number of Erase Sector/Block sizes supported by device Sector Information (y + 1 = Number of sectors; z x 256B = sector size) y = 1023 + 1 = 1024 sectors (03FFH = 1023) z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16) Block Information (y + 1 = Number of blocks; z x 256B = block size) y = 63 + 1 = 64 blocks (0007H = 7) z = 256 x 256 Bytes = 64 KByte/block (0100H = 256) T7.2 1143 ©2003 Silicon Storage Technology, Inc. S71143-02-000 7 11/03 32 Mbit Multi-Purpose Flash SST39VF320 Preliminary Specifications Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD + 0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD + 1.0V Voltage on A9 and A21 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 12.6V Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA 1. Outputs shorted for no more than one second. No more than one output shorted at a time. OPERATING RANGE Range Ambient Temp VDD 0°C to +70°C 2.7-3.6V -40°C to +85°C 2.7-3.6V Commercial Industrial AC CONDITIONS OF TEST Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF See Figures 14 and 15 ©2003 Silicon Storage Technology, Inc. S71143-02-000 8 11/03 32 Mbit Multi-Purpose Flash SST39VF320 Preliminary Specifications TABLE 8: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V1 Limits Symbol Parameter Min IDD Power Supply Current Max Units Test Conditions Address input=VILT/VIHT, at f=5 MHz, VDD=VDD Max Read2 18 mA CE#=VIL, OE#=WE#=VIH, all I/Os open Program and Erase 35 mA CE#=WE#=VIL, OE#=VIH ISB Standby VDD Current 20 µA CE#=VIHC, VDD=VDD Max IALP Auto Low Power Current 20 µA CE#=VILC, VDD=VDD Max, all inputs=VSS or VDD, WE#=VIHC ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max VIL Input Low Voltage VIH Input High Voltage 0.7VDD V VDD=VDD Max VIHC Input High Voltage (CMOS) VDD-0.3 VOL Output Low Voltage VOH Output High Voltage 0.8 0.2 VDD-0.2 VDD=VDD Min V VDD=VDD Max V IOL=100 µA, VDD=VDD Min V IOH=-100 µA, VDD=VDD Min T8.11 1143 1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C (room temperature), and VDD = 3.0V. Not 100% tested. 2. The IDD current listed is typically less than 2mA/MHz, with OE# at VIH. Typical VDD is 3.0V. TABLE 9: RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol TPU-READ Parameter 1 TPU-WRITE1 Minimum Units Power-up to Read Operation 100 µs Power-up to Program/Erase Operation 100 µs T9.0 1143 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 10: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open) Parameter Description Test Condition Maximum CI/O1 I/O Pin Capacitance VI/O = 0V 12 pF Input Capacitance VIN = 0V 6 pF CIN 1 T10.0 1143 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 11: RELIABILITY CHARACTERISTICS Symbol Parameter Minimum Specification Units Test Method NEND1,2 Endurance 10,000 Cycles JEDEC Standard A117 TDR1 Data Retention 100 Years JEDEC Standard A103 ILTH1 Latch Up 100 + IDD mA JEDEC Standard 78 T11.3 1143 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a higher minimum specification. ©2003 Silicon Storage Technology, Inc. S71143-02-000 9 11/03 32 Mbit Multi-Purpose Flash SST39VF320 Preliminary Specifications AC CHARACTERISTICS TABLE 12: READ CYCLE TIMING PARAMETERS VDD = 2.7-3.6V SST39VF320-70 Min Max SST39VF320-90 Symbol Parameter Max Units TRC Read Cycle Time TCE Chip Enable Access Time 70 90 ns TAA TOE Address Access Time 70 90 ns Output Enable Access Time 35 45 TCLZ1 TOLZ1 TCHZ1 TOHZ1 TOH1 ns CE# Low to Active Output 0 0 ns OE# Low to Active Output 0 0 ns 70 Min 90 ns CE# High to High-Z Output 20 30 ns OE# High to High-Z Output 20 30 ns Output Hold from Address Change 0 0 ns T12.1 1143 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 13: PROGRAM/ERASE CYCLE TIMING PARAMETERS Symbol Parameter TBP Word-Program Time TAS Address Setup Time 0 ns TAH Address Hold Time 30 ns TCS WE# and CE# Setup Time 0 ns TCH WE# and CE# Hold Time 0 ns TOES OE# High Setup Time 0 ns TOEH OE# High Hold Time 10 ns TCP CE# Pulse Width 40 ns TWP WE# Pulse Width 40 ns TWPH1 WE# Pulse Width High 30 ns CE# Pulse Width High 30 ns Data Setup Time 30 ns Data Hold Time 0 TCPH 1 TDS TDH 1 Min Max 10 Units µs ns TIDA1 Software ID Access and Exit Time 150 ns TSE Sector-Erase 25 ms TBE Block-Erase 25 ms TSCE Chip-Erase 50 ms T13.2 1143 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2003 Silicon Storage Technology, Inc. S71143-02-000 10 11/03 32 Mbit Multi-Purpose Flash SST39VF320 Preliminary Specifications TAA TRC ADDRESS A20-0 TCE CE# TOE OE# TOHZ TOLZ VIH WE# HIGH-Z DQ15-0 TCHZ TOH TCLZ HIGH-Z DATA VALID DATA VALID 1143 F03.1 FIGURE 3: READ CYCLE TIMING DIAGRAM INTERNAL PROGRAM OPERATION STARTS TBP 5555 TAH ADDRESS A20-0 2AAA 5555 ADDR TDH TWP WE# TAS TDS TWPH OE# TCH CE# TCS DQ15-0 XXAA XXA0 DATA WORD (ADDR/DATA) X can be VIL or VIH, but no other value SW0 Note: XX55 SW1 SW2 1143 F04.2 FIGURE 4: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM ©2003 Silicon Storage Technology, Inc. S71143-02-000 11 11/03 32 Mbit Multi-Purpose Flash SST39VF320 Preliminary Specifications INTERNAL PROGRAM OPERATION STARTS TBP 5555 TAH ADDRESS A20-0 2AAA 5555 ADDR TDH TCP CE# TAS TDS TCPH OE# TCH WE# TCS DQ15-0 Note: XXAA XX55 XXA0 DATA SW0 SW1 SW2 WORD (ADDR/DATA) 1143 F05.2 X can be VIL or VIH, but no other value FIGURE 5: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM ADDRESS A20-0 TCE CE# TOES TOEH OE# TOE WE# DQ7 DATA DATA# DATA# DATA 1143 F06.1 FIGURE 6: DATA# POLLING TIMING DIAGRAM ©2003 Silicon Storage Technology, Inc. S71143-02-000 12 11/03 32 Mbit Multi-Purpose Flash SST39VF320 Preliminary Specifications ADDRESS A20-0 TCE CE# TOES TOE TOEH OE# WE# DQ6 TWO READ CYCLES WITH SAME OUTPUTS 1143 F07.1 FIGURE 7: TOGGLE BIT TIMING DIAGRAM TSCE SIX-BYTE CODE FOR CHIP-ERASE 5555 ADDRESS A20-0 2AAA 5555 5555 2AAA 5555 CE# OE# TWP WE# DQ15-0 XXAA SW0 XX55 SW1 XX80 XXAA SW2 SW3 XX55 SW4 XX10 SW5 1143 F08.2 Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 13) X can be VIL or VIH, but no other value FIGURE 8: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM ©2003 Silicon Storage Technology, Inc. S71143-02-000 13 11/03 32 Mbit Multi-Purpose Flash SST39VF320 Preliminary Specifications TBE SIX-BYTE CODE FOR BLOCK-ERASE 5555 ADDRESS A20-0 2AAA 5555 5555 2AAA BAX CE# OE# TWP WE# DQ15-0 XXAA SW0 XX55 SW1 XX80 XXAA SW2 XX55 SW3 SW4 XX50 SW5 1143 F17.2 Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 13) BAX = Block Address X can be VIL or VIH, but no other value FIGURE 9: WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM TSE SIX-BYTE CODE FOR SECTOR-ERASE 5555 ADDRESS A20-0 2AAA 5555 5555 2AAA SAX CE# OE# TWP WE# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX30 SW0 SW1 SW2 SW3 SW4 SW5 1143 F18.2 Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 13) SAX = Sector Address X can be VIL or VIH, but no other value FIGURE 10: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM ©2003 Silicon Storage Technology, Inc. S71143-02-000 14 11/03 32 Mbit Multi-Purpose Flash SST39VF320 Preliminary Specifications THREE-BYTE SEQUENCE FOR SOFTWARE ID ENTRY 5555 ADDRESS A14-0 2AAA 5555 0000 0001 CE# OE# TIDA TWP WE# TWPH DQ15-0 XXAA XX55 SW0 TAA 00BF XX90 SW1 SW2 Device ID 1143 F09.2 Device ID = 2783H for SST39VF320 Note: X can be VIL or VIH, but no other value FIGURE 11: SOFTWARE ID ENTRY AND READ THREE-BYTE SEQUENCE FOR CFI QUERY ENTRY 5555 ADDRESS A14-0 2AAA 5555 CE# OE# TIDA TWP WE# TWPH DQ15-0 XXAA SW0 XX55 SW1 TAA XX98 SW2 1143 F20.1 Note: X can be VIL or VIH, but no other value FIGURE 12: CFI QUERY ENTRY AND READ ©2003 Silicon Storage Technology, Inc. S71143-02-000 15 11/03 32 Mbit Multi-Purpose Flash SST39VF320 Preliminary Specifications THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET 5555 ADDRESS A14-0 DQ15-0 XXAA 2AAA 5555 XX55 XXF0 TIDA CE# OE# TWP WE# T WHP SW0 SW1 1143 F10.1 SW2 Note: X can be VIL or VIH, but no other value FIGURE 13: SOFTWARE ID EXIT/CFI EXIT ©2003 Silicon Storage Technology, Inc. S71143-02-000 16 11/03 32 Mbit Multi-Purpose Flash SST39VF320 Preliminary Specifications VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT VILT 1143 F11.0 AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test FIGURE 14: AC INPUT/OUTPUT REFERENCE WAVEFORMS TO TESTER TO DUT CL 1143 F12.0 FIGURE 15: A TEST LOAD EXAMPLE ©2003 Silicon Storage Technology, Inc. S71143-02-000 17 11/03 32 Mbit Multi-Purpose Flash SST39VF320 Preliminary Specifications Start Load data: XXAAH Address: 5555H Load data: XX55H Address: 2AAAH Load data: XXA0H Address: 5555H Load Word Address/Word Data Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed 1143 F13.2 X can be VIL or VIH, but no other value FIGURE 16: WORD-PROGRAM ALGORITHM ©2003 Silicon Storage Technology, Inc. S71143-02-000 18 11/03 32 Mbit Multi-Purpose Flash SST39VF320 Preliminary Specifications Internal Timer Toggle Bit Data# Polling Program/Erase Initiated Program/Erase Initiated Program/Erase Initiated Wait TBP, TSCE, TSE or TBE Read word Read DQ7 Read same word Program/Erase Completed No Is DQ7 = true data? Yes No Does DQ6 match? Program/Erase Completed Yes Program/Erase Completed 1143 F14.0 FIGURE 17: WAIT OPTIONS ©2003 Silicon Storage Technology, Inc. S71143-02-000 19 11/03 32 Mbit Multi-Purpose Flash SST39VF320 Preliminary Specifications CFI Query Entry Command Sequence Software ID Entry Command Sequence Software ID Exit/CFI Exit Command Sequence Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XXF0H Address: XXH Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Wait TIDA Load data: XX98H Address: 5555H Load data: XX90H Address: 5555H Load data: XXF0H Address: 5555H Return to normal operation Wait TIDA Wait TIDA Wait TIDA Read CFI data Read Software ID Return to normal operation 1143 F15.1 X can be VIL or VIH, but no other value FIGURE 18: SOFTWARE ID/CFI COMMAND FLOWCHARTS ©2003 Silicon Storage Technology, Inc. S71143-02-000 20 11/03 32 Mbit Multi-Purpose Flash SST39VF320 Preliminary Specifications Chip-Erase Command Sequence Sector-Erase Command Sequence Block-Erase Command Sequence Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Load data: XX80H Address: 5555H Load data: XX80H Address: 5555H Load data: XX80H Address: 5555H Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Load data: XX10H Address: 5555H Load data: XX30H Address: SAX Load data: XX50H Address: BAX Wait TSCE Wait TSE Wait TBE Chip erased to FFFFH Sector erased to FFFFH Block erased to FFFFH 1143 F16.1 X can be VIL or VIH, but no other value FIGURE 19: ERASE COMMAND SEQUENCE ©2003 Silicon Storage Technology, Inc. S71143-02-000 21 11/03 32 Mbit Multi-Purpose Flash SST39VF320 Preliminary Specifications PRODUCT ORDERING INFORMATION SST 39 XX VF XX 320 XXX - 70 - XXX - 4C XX EK - XXX E X Environmental Attribute E = non-Pb Package Modifier K = 48 balls or leads Package Type B3 = TFBGA (0.8mm pitch, 6mm x 8mm) E = TSOP (type 1, die up, 12mm x 20mm) Temperature Range C = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C Minimum Endurance 4 = 10,000 cycles Read Access Speed 70 = 70 ns 90 = 90 ns Device Density 320 = 32 Mbit Voltage V = 2.7-3.6V Product Series 39 = Multi-Purpose Flash Valid combinations for SST39VF320 SST39VF320-70-4C-EK SST39VF320-70-4C-EKE SST39VF320-90-4C-EK SST39VF320-90-4C-EKE SST39VF320-70-4C-B3K SST39VF320-70-4C-B3KE SST39VF320-90-4C-B3K SST39VF320-90-4C-B3KE SST39VF320-70-4I-EK SST39VF320-70-4I-EKE SST39VF320-90-4I-EK SST39VF320-90-4I-EKE SST39VF320-70-4I-B3K SST39VF320-70-4I-B3KE SST39VF320-90-4I-B3K SST39VF320-90-4I-B3KE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2003 Silicon Storage Technology, Inc. S71143-02-000 22 11/03 32 Mbit Multi-Purpose Flash SST39VF320 Preliminary Specifications PACKAGING DIAGRAMS 1.05 0.95 Pin # 1 Identifier 0.50 BSC 0.27 0.17 12.20 11.80 0.15 0.05 18.50 18.30 DETAIL 1.20 max. 0.70 0.50 20.20 19.80 0˚- 5˚ Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.1 mm 4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 48-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 12MM SST PACKAGE CODE: EK X ©2003 Silicon Storage Technology, Inc. 0.70 0.50 1mm 48-tsop-EK-8 20MM S71143-02-000 23 11/03 32 Mbit Multi-Purpose Flash SST39VF320 Preliminary Specifications TOP VIEW BOTTOM VIEW 8.00 ± 0.20 5.60 0.45 ± 0.05 (48X) 0.80 6 6 5 5 4.00 4 4 6.00 ± 0.20 3 3 2 2 1 1 0.80 A B C D E F G H A1 CORNER SIDE VIEW H G F E D C B A A1 CORNER 1.10 ± 0.10 0.12 SEATING PLANE 1mm 0.35 ± 0.05 Note: 1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent. 2. All linear dimensions are in millimeters. 3. Coplanarity: 0.12 mm 4. Ball opening size is 0.38 mm (± 0.05 mm) 48-tfbga-B3K-6x8-450mic-4 48-BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) 6MM SST PACKAGE CODE: B3K X 8MM TABLE 14: REVISION HISTORY Number 00 • Description Date Initial release Jan 2003 01 • Clarified the Test Conditions for Power Supply Current parameter in Table 8 on page 9 Mar 2003 02 • • • 2004 Data Book Updated the B3K package diagram Added non-Pb MPNs and removed footnote. (See page 22) Nov 2003 Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 www.SuperFlash.com or www.sst.com ©2003 Silicon Storage Technology, Inc. S71143-02-000 24 11/03