1 Mbit (64K x16) Multi-Purpose Flash SST39LF100 / SST39VF100 Data Sheet SST39LF/VF1003.0 & 2.7V 1 Mb (x16) MPF memories FEATURES: • Organized as 64K x16 • Single Voltage Read and Write Operations – 3.0-3.6V for SST39LF100 – 2.7-3.6V for SST39VF100 • Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention • Low Power Consumption – Active Current: 20 mA (typical) – Standby Current: 3 µA (typical) • Sector-Erase Capability – Uniform 2 KWord sectors • Fast Read Access Time – 45 ns for SST39LF100 – 70 ns for SST39VF100 • Latched Address and Data • Fast Erase and Word-Program – Sector-Erase Time: 18 ms (typical) – Chip-Erase Time: 70 ms (typical) – Word-Program Time: 14 µs (typical) – Chip Rewrite Time: 1 second (typical) • Automatic Write Timing – Internal VPP Generation • End-of-Write Detection – Toggle Bit – Data# Polling • CMOS I/O Compatibility • JEDEC Standard Command Sets • Packages Available – 40-lead TSOP (10mm x 14mm) – 48-ball TFBGA (6mm x 8mm) PRODUCT DESCRIPTION The SST39LF/VF100 devices are 64K x16 CMOS MultiPurpose Flash (MPF) manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39LF100 and SST39VF100 write (Program or Erase) with a single voltage power supply of 3.0-3.6V and 2.7-3.6V, respectively. Featuring high performance Word-Program, the SST39LF/ VF100 devices provide a typical Word-Program time of 14 µsec. The devices use Toggle Bit or Data# Polling to detect the completion of the Program or Erase operation. To protect against inadvertent write, the SST39LF/VF100 have on-chip hardware and software data protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, the SST39LF/VF100 are offered with a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. The SST39LF/VF100 devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, the SST39LF/VF100 significantly improve performance and reliability, while lowering power consumption. The SST39LF/VF100 inherently use less energy during Erase and Program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total ©2001 Silicon Storage Technology, Inc. S71129-02-000 6/01 363 1 energy consumed during any Erase or Program operation is less than alternative flash technologies. The SST39LF/ VF100 also improve flexibility while lowering the cost for program, data, and configuration storage applications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. To meet surface mount requirements, the SST39LF/VF100 are offered in 40-lead TSOP and 48-ball TFBGA packages. See Figure 1 for pinout. Device Operation Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 1 Mbit Multi-Purpose Flash SST39LF100 / SST39VF100 Data Sheet Read Chip-Erase Operation The Read operation of the SST39LF/VF100 is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 2). The SST39LF/VF100 provide a Chip-Erase operation, which allows the user to erase the entire memory array to the “1” state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 7 for timing diagram, and Figure 16 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. Word-Program Operation The SST39LF/VF100 are programmed on a word-by-word basis. Before programming, one must ensure that the sector in which the word is programmed is erased. The Program operation consists of three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 20 µs. See Figures 3 and 4 for WE# and CE# controlled Program operation timing diagrams and Figure 13 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored. Write Operation Status Detection The SST39LF/VF100 provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal program or erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Sector-Erase Operation The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The sector architecture is based on uniform sector size of 2 KWord. The SectorErase operation is initiated by executing a six-byte command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The address lines A11-A15 are used to determine the sector address. The sector address is latched on the falling edge of the sixth WE# pulse, while the command (30H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle Bit methods. See Figure 8 for timing waveforms. Any commands issued during the Sector-Erase operation are ignored. Data# Polling (DQ7) When the SST39LF/VF100 are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. The device is then ready for the next operation. During internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 5 for Data# Polling timing diagram and Figure 14 for a flowchart. ©2001 Silicon Storage Technology, Inc. S71129-02-000 6/01 2 363 1 Mbit Multi-Purpose Flash SST39LF100 / SST39VF100 Data Sheet Toggle Bit (DQ6) Table 4 for software operation, Figure 9 for the Software ID Entry and Read timing diagram, and Figure 15 for the Software ID Entry command sequence flowchart. During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating 1s and 0s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector- or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 6 for Toggle Bit timing diagram and Figure 14 for a flowchart. TABLE 1: PRODUCT IDENTIFICATION Manufacturer’s ID Address Data 0000H 00BFH 0001H 2788H Device ID SST39LF/VF100 T1.3 363 Product Identification Mode Exit/ CFI Mode Exit Data Protection The SST39LF/VF100 provide both hardware and software features to protect nonvolatile data from inadvertent writes. In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read mode. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit/ CFI Exit command is ignored during an internal Program or Erase operation. See Table 4 for software command codes, Figure 10 for timing waveform and Figure 15 for a flowchart. Hardware Data Protection Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent Writes during power-up or power-down. Software Data Protection (SDP) The SST39LF/VF100 provide the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence. The SST39LF/VF100 devices are shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode within TRC. The contents of DQ15-DQ8 are “Don’t Care” during any SDP command sequence. Product Identification The Product Identification mode identifies the devices as SST39LF100 and SST39VF100 and manufacturer as SST. This mode may be accessed by software operations. Users may use the Software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see ©2001 Silicon Storage Technology, Inc. S71129-02-000 6/01 3 363 1 Mbit Multi-Purpose Flash SST39LF100 / SST39VF100 Data Sheet FUNCTIONAL BLOCK DIAGRAM SuperFlash Memory X-Decoder A0-A15 Address Buffer & Latches Y-Decoder CE# I/O Buffers and Data Latches Control Logic OE# WE# DQ15 - DQ0 A9 A10 A11 A12 A13 A14 A15 NC WE# VDD NC CE# DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Standard Pinout Top View Die Up SST39LF100/SST39VF100 363 ILL B1.2 VSS A8 A7 A6 A5 A4 A3 A2 A1 A0 OE# DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 VSS 363 ILL F01.3 TOP VIEW (balls facing down) SST39LF/VF100 5 4 3 2 1 A13 A12 A14 A15 A9 NC NC DQ15 VSS A8 A10 A11 DQ7 DQ14 DQ13 DQ6 WE# NC NC NC DQ5 DQ12 VDD DQ4 NC NC NC NC DQ2 DQ10 DQ11 DQ3 A7 NC A6 A5 DQ0 DQ8 DQ9 DQ1 A3 A4 A2 A1 A0 CE# OE# VSS A B C D E F G 363 ILL F02b.1 6 H FIGURE 1: PIN ASSIGNMENTS FOR 40-LEAD TSOP AND 48-BALL TFBGA ©2001 Silicon Storage Technology, Inc. S71129-02-000 6/01 4 363 1 Mbit Multi-Purpose Flash SST39LF100 / SST39VF100 Data Sheet TABLE 2: PIN DESCRIPTION Symbol Pin Name Functions A15-A0 Address Inputs To provide memory addresses. During Sector-Erase A15-A11 address lines will select the sector. DQ15-DQ0 Data Input/output To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. CE# Chip Enable To activate the device when CE# is low. OE# Output Enable To gate the data output buffers. WE# Write Enable To control the Write operations. VDD Power Supply To provide power supply voltage: VSS Ground NC No Connection 3.0-3.6V for SST39LF100 2.7-3.6V for SST39VF100 Unconnected pins. T2.2 363 TABLE 3: OPERATION MODES SELECTION Mode CE# OE# WE# Read Program DQ Address VIL VIL VIL VIH VIH DOUT AIN VIL DIN AIN X1 Sector or Block address, XXH for Chip-Erase High Z X Erase VIL VIH VIL Standby VIH X X X VIL X High Z/ DOUT X X X VIH High Z/ DOUT X VIL VIL VIH Write Inhibit Product Identification Software Mode See Table 4 T3.2 363 1. X can be VIL or VIH, but no other value. ©2001 Silicon Storage Technology, Inc. S71129-02-000 6/01 5 363 1 Mbit Multi-Purpose Flash SST39LF100 / SST39VF100 Data Sheet TABLE 4: SOFTWARE COMMAND SEQUENCE Command Sequence 1st Bus Write Cycle 2nd Bus Write Cycle 3rd Bus Write Cycle 4th Bus Write Cycle 5th Bus Write Cycle Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Word-Program 5555H AAH 2AAAH 55H 5555H A0H WA3 Data Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H Software ID Entry5,6 5555H AAH 2AAAH 55H 5555H 90H 2AAAH 55H 5555H F0H Software ID Exit7 XXH F0H Software ID Exit7 5555H AAH 6th Bus Write Cycle Addr1 Data2 Addr1 Data2 AAH 2AAAH 55H SAX4 30H AAH 2AAAH 55H 5555H 10H T4.4 363 1. 2. 3. 4. 5. 6. Address format A14-A0 (Hex), Addresses A15 can be VIL or VIH, but no other value, for the Command sequence DQ15 - DQ8 can be VIL or VIH, but no other value, for the Command sequence WA = Program word address SAX for Sector-Erase; uses A15-A11 address lines The device does not remain in Software Product ID Mode if powered down. With A15-A1 =0; SST Manufacturer’s ID= 00BFH, is read with A0 = 0, SST39LF100/SST39VF100 Device ID = 2788H, is read with A0 = 1 7. Both Software ID Exit operations are equivalent Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD + 0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD + 1.0V Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA 1. Outputs shorted for no more than one second. No more than one output shorted at a time. OPERATING RANGE: SST39LF100 Range Commercial OPERATING RANGE: SST39VF100 Ambient Temp VDD 0°C to +70°C 3.0-3.6V Range Commercial Industrial AC CONDITIONS OF Ambient Temp VDD 0°C to +70°C 2.7-3.6V -40°C to +85°C 2.7-3.6V TEST Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF for SST39LF100 Output Load . . . . . . . . . . . . . . . . . . . . . CL = 100 pF for SST39VF100 See Figures 11 and 12 ©2001 Silicon Storage Technology, Inc. S71129-02-000 6/01 6 363 1 Mbit Multi-Purpose Flash SST39LF100 / SST39VF100 Data Sheet TABLE 5: DC OPERATING CHARACTERISTICS VDD = 3.0-3.6V FOR SST39LF100 AND 2.7-3.6V FOR SST39VF100 Limits Symbol Parameter IDD Power Supply Current Min Max Units Test Conditions Address input = VIL/VIH, at f=1/TRC Min., VDD=VDD Max. Read 30 mA CE#=OE#=VIL,WE#=VIH, all I/Os open Program and Erase 30 mA CE#=WE#=VIL, OE#=VIH ISB Standby VDD Current 20 µA CE#=VIHC, VDD = VDD Max. ILI Input Leakage Current 1 µA VIN =GND to VDD, VDD = VDD Max. ILO Output Leakage Current 10 µA VOUT =GND to VDD, VDD = VDD Max. VIL Input Low Voltage VIH Input High Voltage 0.7VDD 0.8 VIHC Input High Voltage (CMOS) VDD-0.3 VOL Output Low Voltage VOH Output High Voltage VDD = VDD Min. V 0.2 VDD-0.2 VDD = VDD Max. V VDD = VDD Max. V IOL = 5.8 mA, VDD = VDD Min. V IOH = -100 µA, VDD = VDD Min. T5.5 363 TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol TPU-READ Parameter 1 TPU-WRITE1 Minimum Units Power-up to Read Operation 100 µs Power-up to Program/Erase Operation 100 µs T6.0 363 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 7: CAPACITANCE Parameter CI/O 1 CIN1 (Ta = 25°C, f=1 Mhz, other pins open) Description Test Condition Maximum I/O Pin Capacitance VI/O = 0V 12 pF Input Capacitance VIN = 0V 6 pF T7.0 363 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 8: RELIABILITY CHARACTERISTICS Symbol Parameter NEND1 Endurance TDR1 Data Retention ILTH1 Latch Up Minimum Specification Units Test Method 10,000 Cycles JEDEC Standard A117 100 Years JEDEC Standard A103 100 + IDD mA JEDEC Standard 78 T8.1 363 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2001 Silicon Storage Technology, Inc. S71129-02-000 6/01 7 363 1 Mbit Multi-Purpose Flash SST39LF100 / SST39VF100 Data Sheet AC CHARACTERISTICS TABLE 9: READ CYCLE TIMING PARAMETERS VDD = 3.0-3.6V FOR SST39LF100 AND 2.7-3.6V FOR SST39VF100 SST39LF100-35 Symbol Parameter Min SST39VF100-70 Max Min Max Units TRC Read Cycle Time TCE Chip Enable Access Time 45 70 ns TAA Address Access Time 45 70 ns TOE Output Enable Access Time 20 35 ns TCLZ1 TOLZ1 TCHZ1 TOHZ1 TOH1 CE# Low to Active Output 0 0 ns OE# Low to Active Output 0 0 ns 45 70 ns CE# High to High-Z Output 15 20 ns OE# High to High-Z Output 15 20 ns Output Hold from Address Change 0 0 ns T9.3 363 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 10: PROGRAM/ERASE CYCLE TIMING PARAMETERS Symbol Parameter TBP Word-Program Time TAS Address Setup Time 0 ns TAH Address Hold Time 30 ns TCS WE# and CE# Setup Time 0 ns TCH WE# and CE# Hold Time 0 ns TOES OE# High Setup Time 0 ns TOEH OE# High Hold Time 10 ns TCP CE# Pulse Width 40 ns TWP WE# Pulse Width 40 ns TWPH1 WE# Pulse Width High 30 ns CE# Pulse Width High 30 ns Data Setup Time 30 ns Data Hold Time 0 TCPH 1 TDS TDH 1 Min Max Units 20 µs ns TIDA1 Software ID Access and Exit Time 150 ns TSE Sector-Erase 25 ms TBE Block-Erase 25 ms TSCE Chip-Erase 100 ms T10.1 363 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2001 Silicon Storage Technology, Inc. S71129-02-000 6/01 8 363 1 Mbit Multi-Purpose Flash SST39LF100 / SST39VF100 Data Sheet TAA TRC ADDRESS A15-0 TCE CE# TOE OE# TOHZ TOLZ VIH WE# HIGH-Z DQ15-0 TCHZ TOH TCLZ HIGH-Z DATA VALID DATA VALID 363 ILL F03.1 FIGURE 2: READ CYCLE TIMING DIAGRAM INTERNAL PROGRAM OPERATION STARTS TBP 5555 TAH ADDRESS A15-0 2AAA 5555 ADDR TDH TWP WE# TAS TDS TWPH OE# TCH CE# TCS DQ15-0 XXAA XX55 XXA0 DATA SW0 SW1 SW2 WORD (ADDR/DATA) 363 ILL F04.2 Note: X can be VIL or VIH, but no other value FIGURE 3: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM ©2001 Silicon Storage Technology, Inc. S71129-02-000 6/01 9 363 1 Mbit Multi-Purpose Flash SST39LF100 / SST39VF100 Data Sheet INTERNAL PROGRAM OPERATION STARTS TBP 5555 TAH ADDRESS A15-0 2AAA 5555 ADDR TDH TCP CE# TAS TDS TCPH OE# TCH WE# TCS DQ15-0 XXAA XX55 XXA0 DATA SW0 SW1 SW2 WORD (ADDR/DATA) 363 ILL F05.2 Note: X can be VIL or VIH, but no other value FIGURE 4: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM ADDRESS A15-0 TCE CE# TOES TOEH OE# TOE WE# DQ7 DATA DATA# DATA# DATA 363 ILL F06.1 FIGURE 5: DATA# POLLING TIMING DIAGRAM ©2001 Silicon Storage Technology, Inc. S71129-02-000 6/01 10 363 1 Mbit Multi-Purpose Flash SST39LF100 / SST39VF100 Data Sheet ADDRESS A15-0 TCE CE# TOES TOE TOEH OE# WE# DQ6 TWO READ CYCLES WITH SAME OUTPUTS 363 ILL F07.1 FIGURE 6: TOGGLE BIT TIMING DIAGRAM TSCE SIX-BYTE CODE FOR CHIP-ERASE 5555 ADDRESS A15-0 2AAA 5555 5555 2AAA 5555 CE# OE# TWP WE# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX10 SW0 SW1 SW2 SW3 SW4 SW5 363 ILL F08.4 Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 10) X can be VIL or VIH, but no other value. FIGURE 7: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM ©2001 Silicon Storage Technology, Inc. S71129-02-000 6/01 11 363 1 Mbit Multi-Purpose Flash SST39LF100 / SST39VF100 Data Sheet TSE SIX-BYTE CODE FOR SECTOR-ERASE 5555 ADDRESS A15-0 2AAA 5555 5555 2AAA SAX CE# OE# TWP WE# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX30 SW0 SW1 SW2 SW3 SW4 SW5 363 ILL F18.4 Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 10) SAX = Sector Address X can be VIL or VIH, but no other value. FIGURE 8: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM THREE-BYTE SEQUENCE FOR SOFTWARE ID ENTRY 5555 ADDRESS A14-0 2AAA 5555 0000 0001 CE# OE# TIDA TWP WE# TWPH DQ15-0 TAA XXAA XX55 XX90 SW0 SW1 SW2 00BFH Device ID 363 ILL F09.4 Note: X can be VIL or VIH, but no other value Device ID = 2788H for SST39LF/VF100 FIGURE 9: SOFTWARE ID ENTRY AND READ ©2001 Silicon Storage Technology, Inc. S71129-02-000 6/01 12 363 1 Mbit Multi-Purpose Flash SST39LF100 / SST39VF100 Data Sheet THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET 5555 ADDRESS A14-0 DQ15-0 XXAA 2AAA 5555 XX55 XXF0 TIDA CE# OE# TWP WE# T WHP SW0 SW1 363 ILL F10.1 SW2 Note: X can be VIL or VIH, but no other value. FIGURE 10: SOFTWARE ID EXIT ©2001 Silicon Storage Technology, Inc. S71129-02-000 6/01 13 363 1 Mbit Multi-Purpose Flash SST39LF100 / SST39VF100 Data Sheet VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT VILT 363 ILL F11.1 AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test FIGURE 11: AC INPUT/OUTPUT REFERENCE WAVEFORMS 1.3 V 1N914 TO TESTER 3.3 KΩ TO DUT CL 363 ILL F12.2 FIGURE 12: A TEST LOAD EXAMPLE ©2001 Silicon Storage Technology, Inc. S71129-02-000 6/01 14 363 1 Mbit Multi-Purpose Flash SST39LF100 / SST39VF100 Data Sheet Start Load data: XXAAH Address: 5555H Load data: XX55H Address: 2AAAH Load data: XXA0H Address: 5555H Load Word Address/Word Data Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed 363 ILL F13.3 X can be VIL or VIH but no other value. FIGURE 13: WORD-PROGRAM ALGORITHM ©2001 Silicon Storage Technology, Inc. S71129-02-000 6/01 15 363 1 Mbit Multi-Purpose Flash SST39LF100 / SST39VF100 Data Sheet Internal Timer Toggle Bit Data# Polling Program/Erase Initiated Program/Erase Initiated Program/Erase Initiated Wait TBP, TSCE, TSE or TBE Read word Read DQ7 Read same word Program/Erase Completed No Is DQ7 = true data? Yes No Does DQ6 match? Program/Erase Completed Yes Program/Erase Completed 363 ILL F14.0 FIGURE 14: WAIT OPTIONS ©2001 Silicon Storage Technology, Inc. S71129-02-000 6/01 16 363 1 Mbit Multi-Purpose Flash SST39LF100 / SST39VF100 Data Sheet Software ID Entry Command Sequence Software ID Exit Command Sequence Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XXF0H Address: XXH Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Wait TIDA Load data: XX90H Address: 5555H Load data: XXF0H Address: 5555H Return to normal operation Wait TIDA Wait TIDA Read Software ID Return to normal operation 363 ILL F15.2 X can be VIL or VIH, but no other value. FIGURE 15: SOFTWARE PRODUCT ID COMMAND FLOWCHARTS ©2001 Silicon Storage Technology, Inc. S71129-02-000 6/01 17 363 1 Mbit Multi-Purpose Flash SST39LF100 / SST39VF100 Data Sheet Chip-Erase Command Sequence Sector-Erase Command Sequence Load data: XXAA Address: 5555 Load data: XXAA Address: 5555 Load data: XX55 Address: 2AAA Load data: XX55 Address: 2AAA Load data: XX80 Address: 5555 Load data: XX80 Address: 5555 Load data: XXAA Address: 5555 Load data: XXAA Address: 5555 Load data: XX55 Address: 2AAA Load data: XX55 Address: 2AAA Load data: XX10 Address: 5555 Load data: XX30 Address: SAX Wait TSCE Wait TSE Chip erased to FFFFH Sector erased to FFFFH X can be VIL or VIH, but no other value. 363 ILL F16.3 FIGURE 16: ERASE COMMAND SEQUENCE ©2001 Silicon Storage Technology, Inc. S71129-02-000 6/01 18 363 1 Mbit Multi-Purpose Flash SST39LF100 / SST39VF100 Data Sheet PRODUCT ORDERING INFORMATION Device SST39xF100 Speed - XXX Suffix1 - XX Suffix2 - XX Package Modifier I = 40 leads K = 48 balls Numeric = Die modifier Package Type W = TSOP (10mm x 14mm) B3 = TFBGA (0.8mm pitch, 6mm x 8mm) Temperature Range C = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C Minimum Endurance 4 = 10,000 cycles Read Access Speed 45 = 45 ns 70 = 70 ns Device Density 100 = 1 Megabit Voltage L = 3.0-3.6V V = 2.7-3.6V Valid combinations for SST39LF100 SST39LF100-45-4C-WI SST39LF100-45-4C-B3K Valid combinations for SST39VF100 SST39VF100-70-4C-WI SST39VF100-70-4C-B3K SST39VF100-70-4I-WI SST39VF100-70-4I-B3K Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2001 Silicon Storage Technology, Inc. S71129-02-000 6/01 19 363 1 Mbit Multi-Purpose Flash SST39LF100 / SST39VF100 Data Sheet PACKAGING DIAGRAMS 1.05 0.95 Pin # 1 Identifier .50 BSC .270 .170 10.10 9.90 0.15 0.05 12.50 12.30 0.60 0.40 14.20 13.80 40.TSOP-WI-ILL.4 Note: 1. Complies with JEDEC publication 95 MO-142 CA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (±.05) mm. 4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads. 40-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 10MM SST PACKAGE CODE: WI X ©2001 Silicon Storage Technology, Inc. 14MM S71129-02-000 6/01 20 363 1 Mbit Multi-Purpose Flash SST39LF100 / SST39VF100 Data Sheet BOTTOM VIEW 8.00 ± 0.20 5.60 TOP VIEW 0.80 6 6 5 5 4.00 4 4 6.00 ± 0.20 3 3 2 2 1 1 0.80 H G F E D C B A A B C D E F G H 0.45 ± 0.05 (48X) A1 CORNER A1 CORNER SIDE VIEW 1.10 ± 0.10 0.15 SEATING PLANE 48ba-TFBGA-B3K-6x8-450mic-ILL.0 0.35 ± 0.05 1mm Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (±.05) mm. 4. The actual shape of the corners may be slightly different than as portrayed in the drawing. 48-BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) 6MM SST PACKAGE CODE: B3K ©2001 Silicon Storage Technology, Inc. X 8MM S71129-02-000 6/01 21 363 1 Mbit Multi-Purpose Flash SST39LF100 / SST39VF100 Data Sheet Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 www.SuperFlash.com or www.ssti.com ©2001 Silicon Storage Technology, Inc. S71129-02-000 6/01 22 363