MICROCHIP SST39VF3201B

32 Mbit (x16) Multi-Purpose Flash Plus
SST39VF3201B / SST39VF3202B
SST39VF640xB2.7V 64Mb (x16) MPF+ memories
Data Sheet
FEATURES:
• Organized as 2M x16
• Single Voltage Read and Write Operations
– 2.7-3.6V
• Superior Reliability
– Endurance: 100,000 Cycles (Typical)
– Greater than 100 years Data Retention
• Low Power Consumption (typical values at 5 MHz)
– Active Current: 6 mA (typical)
– Standby Current: 4 µA (typical)
– Auto Low Power Mode: 4 µA (typical)
• Hardware Block-Protection/WP# Input Pin
– Top Block-Protection (top 32 KWord)
for SST39VF3202B
– Bottom Block-Protection (bottom 32 KWord)
for SST39VF3201B
• Sector-Erase Capability
– Uniform 2 KWord sectors
• Block-Erase Capability
– Uniform 32 KWord blocks
• Chip-Erase Capability
• Erase-Suspend/Erase-Resume Capabilities
• Hardware Reset Pin (RST#)
• Security-ID Feature
– SST: 128 bits; User: 128 words
• Fast Read Access Time:
– 70 ns
• Latched Address and Data
• Fast Erase and Word-Program:
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 35 ms (typical)
– Word-Program Time: 7 µs (typical)
• Automatic Write Timing
– Internal VPP Generation
• End-of-Write Detection
– Toggle Bits
– Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pin Assignments
• Packages Available
– 48-lead TSOP (12mm x 20mm)
– 48-ball TFBGA (6mm x 8mm)
• All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST39VF320xB devices are 2M x16 CMOS MultiPurpose Flash Plus (MPF+) manufactured with SST’s proprietary, high-performance CMOS SuperFlash technology.
The split-gate cell design and thick-oxide tunneling injector
attain better reliability and manufacturability compared with
alternate approaches. The SST39VF320xB write (Program or Erase) with a 2.7-3.6V power supply. These
devices conform to JEDEC standard pin assignments for
x16 memories.
Featuring high performance Word-Program, the
SST39VF320xB devices provide a typical Word-Program
time of 7 µsec. These devices use Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, they have on-chip hardware
and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications,
these devices are offered with a guaranteed typical endurance of 100,000 cycles. Data retention is rated at greater
than 100 years.
The SST39VF320xB devices are suited for applications that
require convenient and economical updating of program,
configuration, or data memory. For all system applications,
©2009 Silicon Storage Technology, Inc.
S71384-01-000
1/09
1
they significantly improve performance and reliability, while
lowering power consumption. They inherently use less
energy during Erase and Program than alternative flash
technologies. The total energy consumed is a function of
the applied voltage, current, and time of application. Since
for any given voltage range, the SuperFlash technology
uses less current to program and has a shorter erase time,
the total energy consumed during any Erase or Program
operation is less than alternative flash technologies. These
devices also improve flexibility while lowering the cost for
program, data, and configuration storage applications.
The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Program cycles.
To meet high-density, surface mount requirements, the
SST39VF320xB devices are offered in 48-lead TSOP and
48-ball TFBGA packages. See Figure 2 and Figure 3 for
pin assignments.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
32 Mbit Multi-Purpose Flash Plus
SST39VF3201B / SST39VF3202B
Data Sheet
Device Operation
Any commands issued during the internal Program operation are ignored. During the command sequence, WP#
should be statically held high or low.
Commands are used to initiate the memory operation functions of the device. Commands are written to the device
using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE#
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. The data bus is latched on
the rising edge of WE# or CE#, whichever occurs first.
Sector/Block-Erase Operation
The Sector- (or Block-) Erase operation allows the system
to erase the device on a sector-by-sector (or block-byblock) basis. The SST39VF320xB offer both Sector-Erase
and Block-Erase mode. The sector architecture is based
on uniform sector size of 2 KWord. The Block-Erase mode
is based on uniform block size of 32 KWord. The SectorErase operation is initiated by executing a six-byte command sequence with Sector-Erase command (50H) and
sector address (SA) in the last bus cycle. The Block-Erase
operation is initiated by executing a six-byte command
sequence with Block-Erase command (30H) and block
address (BA) in the last bus cycle. The sector or block
address is latched on the falling edge of the sixth WE#
pulse, while the command (50H or 30H) is latched on the
rising edge of the sixth WE# pulse. The internal Erase
operation begins after the sixth WE# pulse. The End-ofErase operation can be determined using either Data#
Polling or Toggle Bit methods. See Figure 11 and Figure 12
for timing waveforms and Figure 25 for the flowchart. Any
commands issued during the Sector- or Block-Erase operation are ignored. When WP# is low, any attempt to Sector(Block-) Erase the protected block will be ignored. During
the command sequence, WP# should be statically held
high or low.
The SST39VF320xB also have the Auto Low Power
mode which puts the device in a near standby mode after
data has been accessed with a valid Read operation. This
reduces the IDD active read current from typically 9 mA to
typically 4 µA. The Auto Low Power mode reduces the typical IDD active read current to the range of 2 mA/MHz of
Read cycle time. The device exits the Auto Low Power
mode with any address transition or control signal transition
used to initiate another Read cycle, with no access time
penalty. Note that the device does not enter Auto-Low
Power mode after power-up with CE# held steadily low,
until the first address transition or CE# is driven high.
Read
The Read operation of the SST39VF320xB is controlled
by CE# and OE#, both have to be low for the system to
obtain data from the outputs. CE# is used for device
selection. When CE# is high, the chip is deselected and
only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The
data bus is in high impedance state when either CE# or
OE# is high. Refer to the Read cycle timing diagram for
further details (Figure 5).
Erase-Suspend/Erase-Resume Commands
The Erase-Suspend operation temporarily suspends a
Sector- or Block-Erase operation thus allowing data to be
read from any memory location, or program data into any
sector/block that is not suspended for an Erase operation.
The operation is executed by issuing one byte command
sequence with Erase-Suspend command (B0H). The
device automatically enters read mode typically within 10
µs after the Erase-Suspend command had been issued.
Valid data can be read from any sector or block that is not
suspended from an Erase operation. Reading at address
location within erase-suspended sectors/blocks will output
DQ2 toggling and DQ6 at ‘1’. While in Erase-Suspend
mode, a Word-Program operation is allowed except for the
sector or block selected for Erase-Suspend.
Word-Program Operation
The SST39VF320xB are programmed on a word-by-word
basis. Before programming, the sector where the word
exists must be fully erased. The Program operation is
accomplished in three steps. The first step is the three-byte
load sequence for Software Data Protection. The second
step is to load word address and word data. During the
Word-Program operation, the addresses are latched on the
falling edge of either CE# or WE#, whichever occurs last.
The data is latched on the rising edge of either CE# or
WE#, whichever occurs first. The third step is the internal
Program operation which is initiated after the rising edge of
the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 10
µs. See Figure 6 and Figure 7 for WE# and CE# controlled
Program operation timing diagrams and Figure 21 for flowcharts. During the Program operation, the only valid reads
are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks.
To resume Sector-Erase or Block-Erase operation which has
been suspended the system must issue Erase Resume
command. The operation is executed by issuing one byte
command sequence with Erase Resume command (30H)
at any address in the last Byte sequence.
©2009 Silicon Storage Technology, Inc.
S71384-01-000
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1/09
32 Mbit Multi-Purpose Flash Plus
SST39VF3201B / SST39VF3202B
Data Sheet
Chip-Erase Operation
‘1’. The Data# Polling is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector-,
Block- or Chip-Erase, the Data# Polling is valid after the
rising edge of sixth WE# (or CE#) pulse. See Figure 8 for
Data# Polling timing diagram and Figure 22 for a flowchart.
The SST39VF320xB provide a Chip-Erase operation,
which allows the user to erase the entire memory array to
the “1” state. This is useful when the entire device must be
quickly erased.
The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command
(10H) at address 555H in the last byte sequence. The
Erase operation begins with the rising edge of the sixth
WE# or CE#, whichever occurs first. During the Erase
operation, the only valid read is Toggle Bit or Data# Polling.
See Table 6 for the command sequence, Figure 10 for timing diagram, and Figure 25 for the flowchart. Any commands issued during the Chip-Erase operation are
ignored. When WP# is low, any attempt to Chip-Erase will
be ignored. During the command sequence, WP# should
be statically held high or low.
Toggle Bits (DQ6 and DQ2)
Write Operation Status Detection
During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating “1”s
and “0”s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ6 bit will
stop toggling. The device is then ready for the next operation. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ6)
is valid after the rising edge of sixth WE# (or CE#) pulse.
DQ6 will be set to ‘1’ if a Read operation is attempted on an
Erase-Suspended Sector/Block. If Program operation is initiated in a sector/block not selected in Erase-Suspend
mode, DQ6 will toggle.
The SST39VF320xB provide two software means to detect
the completion of a Write (Program or Erase) cycle, in
order to optimize the system write cycle time. The software
detection includes two status bits: Data# Polling (DQ7) and
Toggle Bit (DQ6). The End-of-Write detection mode is
enabled after the rising edge of WE#, which initiates the
internal Program or Erase operation.
An additional Toggle Bit is available on DQ2, which can be
used in conjunction with DQ6 to check whether a particular
sector is being actively erased or erase-suspended. Table 1
shows detailed status bits information. The Toggle Bit
(DQ2) is valid after the rising edge of the last WE# (or CE#)
pulse of Write operation. See Figure 9 for Toggle Bit timing
diagram and Figure 22 for a flowchart.
The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the
completion of the write cycle. If this occurs, the system
may possibly get an erroneous result, i.e., valid data may
appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the
software routine should include a loop to read the
accessed location an additional two (2) times. If both
reads are valid, then the device has completed the Write
cycle, otherwise the rejection is valid.
TABLE 1: Write Operation Status
Status
DQ7
DQ6
DQ2
Normal
Standard
Operation Program
DQ7#
Toggle
No Toggle
Standard
Erase
0
Toggle
Toggle
Read from
Erase-Suspended
Sector/Block
1
1
Toggle
Read from
Non- Erase-Suspended
Sector/Block
Data
Data
Data
Program
DQ7#
Toggle
EraseSuspend
Mode
Data# Polling (DQ7)
N/A
T1.0 1384
When the SST39VF320xB are in the internal Program
operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is
completed, DQ7 will produce true data. Note that even
though DQ7 may have valid data immediately following the
completion of an internal Write operation, the remaining
data outputs may still be invalid: valid data on the entire
data bus will appear in subsequent successive Read
cycles after an interval of 1 µs. During internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the
internal Erase operation is completed, DQ7 will produce a
Note: DQ7, DQ6 and DQ2 require a valid address when reading
status information.
©2009 Silicon Storage Technology, Inc.
S71384-01-000
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1/09
32 Mbit Multi-Purpose Flash Plus
SST39VF3201B / SST39VF3202B
Data Sheet
Data Protection
Hardware Reset (RST#)
The SST39VF320xB provide both hardware and software
features to protect nonvolatile data from inadvertent writes.
The RST# pin provides a hardware method of resetting the
device to read array data. When the RST# pin is held low
for at least TRP, any in-progress operation will terminate and
return to Read mode. When no internal Program/Erase
operation is in progress, a minimum period of TRHR is
required after RST# is driven high before a valid Read can
take place. See Figure 17.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
The Erase or Program operation that has been interrupted
needs to be re-initiated after the device resumes normal
operation mode to ensure data integrity.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down.
Software Data Protection (SDP)
The SST39VF320xB provide the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation
requires the inclusion of the three-byte sequence. The
three-byte load sequence is used to initiate the Program
operation, providing optimal protection from inadvertent
Write operations, e.g., during the system power-up or
power-down. Any Erase operation requires the inclusion of
six-byte sequence. These devices are shipped with the
Software Data Protection permanently enabled. See Table
6 for the specific software command codes. During SDP
command sequence, invalid commands will abort the
device to read mode within TRC. The contents of DQ15-DQ8
can be VIL or VIH, but no other value, during any SDP command sequence.
Hardware Block Protection
The SST39VF3202B support top hardware block protection, which protects the top 32 KWord block of the device.
The SST39VF3201B support bottom hardware block protection, which protects the bottom 32 KWord block of the
device. The Boot Block address ranges are described in
Table 2. Program and Erase operations are prevented on
the 32 KWord when WP# is low. If WP# is left floating, it is
internally held high via a pull-up resistor, and the Boot
Block is unprotected, enabling Program and Erase operations on that block.
TABLE 2: Boot Block Address Ranges
Product
Address Range
Bottom Boot Block
SST39VF3201B
Common Flash Memory Interface (CFI)
000000H-007FFFH
The SST39VF320xB also contain the CFI information to
describe the characteristics of the device. In order to enter
the CFI Query mode, the system must write the three-byte
sequence, same as product ID entry command with 98H
(CFI Query command) to address 555H in the last byte
sequence. The system can also enter the CFI Query
mode, by using the one-byte sequence with 55H on
Address and 98H on Data Bus. Once the device enters
the CFI Query mode, the system can read CFI data at the
addresses given in Tables 7 through 9. The system must
write the CFI Exit command to return to Read mode from
the CFI Query mode.
Top Boot Block
SST39VF3202B
1F8000H-1FFFFFH
T2.0 1384
©2009 Silicon Storage Technology, Inc.
S71384-01-000
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1/09
32 Mbit Multi-Purpose Flash Plus
SST39VF3201B / SST39VF3202B
Data Sheet
Product Identification
Security ID
The Product Identification mode identifies the devices as
the SST39VF3201B and SST39VF3202B, and the manufacturer as SST. This mode may be accessed through
software operations. Users may use the Software Product
Identification operation to identify the part (i.e., using the
device ID) when using multiple manufacturers in the same
socket. For details, see Table 6 for software operation,
Figure 13 for the Software ID Entry and Read timing diagram and Figure 23 for the Software ID Entry command
sequence flowchart.
The SST39VF320xB devices offer a 136 word Security ID
space. The Secure ID space is divided into two segments one factory programmed segment and one user programmed segment. The first segment is programmed and
locked at SST with a random 128-bit number. The 128word user segment is left un-programmed for the customer
to program as desired.
To program the user segment of the Security ID, the user
must use the Security ID Word-Program command. To
detect end-of-write for the SEC ID, read the toggle bits. Do
not use Data# Polling. Once this is complete, the Sec ID
should be locked using the User Sec ID Program Lock-Out.
This disables any future corruption of this space. Note that
regardless of whether or not the Sec ID is locked, neither
Sec ID segment can be erased.
TABLE 3: Product Identification
Address
Data
0000H
BFH
SST39VF3201B
0001H
235DH
SST39VF3202B
0001H
235CH
Manufacturer’s ID
Device ID
The Secure ID space can be queried by executing a threebyte command sequence with Enter Sec ID command
(88H) at address 555H in the last byte sequence. To exit
this mode, the Exit Sec ID command should be executed.
Refer to Table 6 for more details.
T3.0 1384
Product Identification Mode Exit/
CFI Mode Exit
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command
sequence, which returns the device to the Read mode.
This command may also be used to reset the device to the
Read mode after any inadvertent transient condition that
apparently causes the device to behave abnormally, e.g.,
not read correctly. Please note that the Software ID Exit/
CFI Exit command is ignored during an internal Program or
Erase operation. See Table 6 for software command
codes, Figure 15 for timing waveform, and Figure 23 and
Figure 24 for flowcharts.
©2009 Silicon Storage Technology, Inc.
S71384-01-000
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1/09
32 Mbit Multi-Purpose Flash Plus
SST39VF3201B / SST39VF3202B
Data Sheet
X-Decoder
Memory Address
SuperFlash
Memory
Address Buffer & Latches
Y-Decoder
CE#
OE#
WE#
WP#
RESET#
Control Logic
I/O Buffers and Data Latches
DQ15 - DQ0
1384 B1.0
FIGURE 1: Functional Block Diagram
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RST#
NC
WP#
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Standard Pinout
Top View
Die Up
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
1384 48-tsop EK P1.0
FIGURE 2: Pin Assignments for 48-lead TSOP
©2009 Silicon Storage Technology, Inc.
S71384-01-000
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1/09
32 Mbit Multi-Purpose Flash Plus
SST39VF3201B / SST39VF3202B
Data Sheet
TOP VIEW (balls facing down)
6
5
4
3
2
1
A13 A12 A14
A15 A16 NC DQ15 VSS
A8
A10
A11 DQ7 DQ14 DQ13 DQ6
WE# RST#
NC
A19 DQ5 DQ12 VDD DQ4
NC WP# A18
A20 DQ2 DQ10 DQ11 DQ3
A9
A7
A17
A6
A5
DQ0 DQ8 DQ9 DQ1
A3
A4
A2
A1
A0 CE# OE# VSS
A B C D E F G H
1384 4-tfbga B1K P2.0
FIGURE 3: pin assignments for 48-ball TFBGA
TABLE 4: Pin Description
Symbol
Pin Name
Functions
AMS1-A0
Address Inputs
To provide memory addresses.
During Sector-Erase AMS-A11 address lines will select the sector.
During Block-Erase AMS-A15 address lines will select the block.
DQ15-DQ0
Data Input/output
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
WP#
Write Protect
To protect the top/bottom boot block from Erase/Program operation when grounded.
RST#
Reset
To reset and return the device to Read mode.
CE#
Chip Enable
To activate the device when CE# is low.
OE#
Output Enable
To gate the data output buffers.
WE#
Write Enable
To control the Write operations.
To provide power supply voltage: 2.7-3.6V
VDD
Power Supply
VSS
Ground
NC
No Connection
Unconnected pins.
T4.0 1384
1. AMS = Most significant address
AMS = A20 for SST39VF320xB
©2009 Silicon Storage Technology, Inc.
S71384-01-000
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1/09
32 Mbit Multi-Purpose Flash Plus
SST39VF3201B / SST39VF3202B
Data Sheet
TABLE 5: Operation Modes Selection
Mode
CE#
OE#
WE#
DQ
Address
Read
VIL
VIL
VIH
DOUT
AIN
Program
VIL
VIH
VIL
DIN
AIN
Erase
VIL
VIH
VIL
X1
Sector or block address,
XXH for Chip-Erase
Standby
VIH
X
X
High Z
X
X
VIL
X
High Z/ DOUT
X
X
X
VIH
High Z/ DOUT
X
VIL
VIL
VIH
Write Inhibit
Product Identification
Software Mode
See Table 6
T5.0 1384
1. X can be VIL or VIH, but no other value.
©2009 Silicon Storage Technology, Inc.
S71384-01-000
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1/09
32 Mbit Multi-Purpose Flash Plus
SST39VF3201B / SST39VF3202B
Data Sheet
TABLE 6: Software Command Sequence
Command
Sequence
1st Bus
Write Cycle
Addr1
Data2
2nd Bus
Write Cycle
Addr1
Data2
3rd Bus
Write Cycle
Addr1
4th Bus
Write Cycle
Data2
Addr1
Data2
Data
AAH
Word-Program
555H
AAH
2AAH
55H
555H
A0H
WA3
Sector-Erase
555H
AAH
2AAH
55H
555H
80H
555H
5th Bus
Write Cycle
6th Bus
Write Cycle
Addr1
Data2
Addr1
Data2
2AAH
55H
SAX4
50H
4
30H
10H
Block-Erase
555H
AAH
2AAH
55H
555H
80H
555H
AAH
2AAH
55H
BAX
Chip-Erase
555H
AAH
2AAH
55H
555H
80H
555H
AAH
2AAH
55H
555H
Erase-Suspend
XXXXH
B0H
Erase-Resume
XXXXH
30H
ID5
555H
AAH
2AAH
55H
555H
88H
User Security ID
Word-Program
555H
AAH
2AAH
55H
555H
A5H
WA6
Data
User Security ID
Program Lock-Out
555H
AAH
2AAH
55H
555H
85H
XXH6
0000H
Software ID Entry7,8
555H
AAH
2AAH
55H
555H
90H
CFI Query Entry
555H
AAH
2AAH
55H
555H
98H
CFI Query Entry
55H
98H
Software ID Exit9,10
/CFI Exit/Sec ID Exit
555H
AAH
2AAH
55H
555H
F0H
Software ID Exit9,10
/CFI Exit/Sec ID Exit
XXH
F0H
Query Sec
T6.0 1384
1. Address format A10-A0 (Hex).
Addresses A11- A20 can be VIL or VIH, but no other value, for Command sequence for SST39VF320xB.
2. DQ15-DQ8 can be VIL or VIH, but no other value, for Command sequence
3. WA = Program Word address
4. SAX for Sector-Erase; uses AMS-A11 address lines
BAX, for Block-Erase; uses AMS-A15 address lines
AMS = Most significant address
AMS = A20 for SST39VF320xB
5. With AMS-A4 = 0; Sec ID is read with A3-A0,
SST ID is read with A3 = 0 (Address range = 000000H to 000007H),
User ID is read with A3 = 1 (Address range = 000008H to 000087H).
Lock Status is read with A7-A0 = 0000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0.
6. Valid Word-Addresses for Sec ID are from 000000H-000007H and 000008H to 000087H.
7. The device does not remain in Software Product ID Mode if powered down.
8. With AMS-A1 =0; SST Manufacturer ID = 00BFH, is read with A0 = 0,
SST39VF3201B Device ID = 235DH, is read with A0 = 1,
SST39VF3202B Device ID = 235CH, is read with A0 = 1.
AMS = Most significant address
AMS = A20 for SST39VF320xB
9. Both Software ID Exit operations are equivalent
10. If users never lock after programming, Sec ID can be programmed over the previously unprogrammed bits (data=1) using the Sec ID
mode again (the programmed “0” bits cannot be reversed to “1”). Valid Word-Addresses for Sec ID are from 000000H-000007H and
000008H to 000087H.
©2009 Silicon Storage Technology, Inc.
S71384-01-000
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1/09
32 Mbit Multi-Purpose Flash Plus
SST39VF3201B / SST39VF3202B
Data Sheet
TABLE 7: CFI Query Identification String1 for SST39VF320xB
Address
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
Data
0051H
0052H
0059H
0002H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
Data
Query Unique ASCII string “QRY”
Primary OEM command set
Address for Primary Extended Table
Alternate OEM command set (00H = none exists)
Address for Alternate OEM extended Table (00H = none exits)
T7.0 1384
1. Refer to CFI publication 100 for more details.
TABLE 8: System Interface Information for SST39VF320xB
Address
Data
1BH
0027H
VDD Min (Program/Erase)
Data
1CH
0036H
VDD Max (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1DH
0000H
VPP min. (00H = no VPP pin)
1EH
0000H
VPP max. (00H = no VPP pin)
1FH
0003H
Typical time out for Word-Program 2N µs (23 = 8 µs)
20H
0000H
Typical time out for min. size buffer program 2N µs (00H = not supported)
21H
0004H
Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms)
22H
0005H
Typical time out for Chip-Erase 2N ms (25 = 32 ms)
23H
0001H
Maximum time out for Word-Program 2N times typical (21 x 23 = 16 µs)
24H
0000H
Maximum time out for buffer program 2N times typical
25H
0001H
Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32 ms)
26H
0001H
Maximum time out for Chip-Erase 2N times typical (21 x 25 = 64 ms)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
T8.0 1384
TABLE 9: Device Geometry Information for SST39VF320xB
Address
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
Data
0016H
0001H
0000H
0000H
0000H
0002H
00FFH
0003H
0010H
0000H
003FH
0000H
0000H
0001H
Data
Device size = 2N Bytes (16H = 22; 222 = 4MByte)
Flash Device Interface description; 0001H = x16-only asynchronous interface
Maximum number of bytes in multi-byte write = 2N (00H = not supported)
Number of Erase Sector/Block sizes supported by device
Sector Information (y + 1 = Number of sectors; z x 256B = sector size)
y = 1023 + 1 = 1024 sectors (03FFH = 1023)
z = 16 x 256 Bytes = 4 KBytes/sector (0010H = 16)
Block Information (y + 1 = Number of blocks; z x 256B = block size)
y = 63 + 1 = 64 blocks (003FH = 63)
z = 256 x 256 Bytes = 64 KBytes/block (0100H = 256)
T9.0 1384
©2009 Silicon Storage Technology, Inc.
S71384-01-000
10
1/09
32 Mbit Multi-Purpose Flash Plus
SST39VF3201B / SST39VF3202B
Data Sheet
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V
Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
Operating Range
Range
Ambient Temp
VDD
Commercial
Industrial
0°C to +70°C
-40°C to +85°C
2.7-3.6V
2.7-3.6V
AC Conditions of Test
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF
See Figures 19 and 20
Power Up Specifications
All functionalities and DC specifications are specified for a VDD ramp rate of greater than 1V per 100 ms (0V to 3V
in less than 300 ms). If the VDD ramp rate is slower than 1V per 100 ms, a hardware reset is required. The recommended VDD power-up to RESET# high time should be greater than 100 µs to ensure a proper reset.
TPU-READ > 100 µs
VDD min
VDD
0V
VIH
RESET#
TRHR > 50ns
CE#
1384 F24.0
FIGURE 4: Power-Up Diagram
©2009 Silicon Storage Technology, Inc.
S71384-01-000
11
1/09
32 Mbit Multi-Purpose Flash Plus
SST39VF3201B / SST39VF3202B
Data Sheet
TABLE 10: DC Operating Characteristics VDD = 2.7-3.6V1
Limits
Symbol
Parameter
IDD
Power Supply Current
Min
Max
Units
Test Conditions
Address input=VILT/VIHT2, at f=5 MHz,
VDD=VDD Max
Read3
15
mA
CE#=VIL, OE#=WE#=VIH, all I/Os open
Program and Erase
45
mA
CE#=WE#=VIL, OE#=VIH
ISB
Standby VDD Current
20
µA
CE#=VIHC, VDD=VDD Max
IALP
Auto Low Power
20
µA
CE#=VILC, VDD=VDD Max
All inputs=VSS or VDD, WE#=VIHC
ILI
Input Leakage Current
1
µA
VIN=GND to VDD, VDD=VDD Max
ILIW
Input Leakage Current
on WP# pin and RST#
10
µA
WP#=GND to VDD or RST#=GND to VDD
ILO
Output Leakage Current
1
µA
VOUT=GND to VDD, VDD=VDD Max
VIL
Input Low Voltage
0.8
V
VDD=VDD Min
VILC
Input Low Voltage (CMOS)
0.3
V
VDD=VDD Max
VIH
Input High Voltage
0.7VDD
V
VDD=VDD Max
VIHC
Input High Voltage (CMOS)
VDD-0.3
V
VDD=VDD Max
VOL
Output Low Voltage
VOH
Output High Voltage
0.2
VDD-0.2
V
IOL=100 µA, VDD=VDD Min
V
IOH=-100 µA, VDD=VDD Min
T10.0 1384
1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C
(room temperature), and VDD = 3V. Not 100% tested.
2. See Figure 19
3. The IDD current listed is typically less than 2mA/MHz, with OE# at VIH. Typical VDD is 3V.
TABLE 11: Recommended System Power-up Timings
Symbol
Parameter
Minimum
Units
TPU-READ1
Power-up to Read Operation
100
µs
Power-up to Program/Erase Operation
100
µs
TPU-WRITE
1
T11.0 1384
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 12: Capacitance (TA = 25°C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
Maximum
CI/O1
I/O Pin Capacitance
VI/O = 0V
10 pF
Input Capacitance
VIN = 0V
10 pF
CIN
1
T12.0 1384
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 13: Reliability Characteristics
Symbol
NEND
1,2
Parameter
Minimum Specification
Units
Endurance
10,000
Cycles
JEDEC Standard A117
100
Years
JEDEC Standard A103
100 + IDD
mA
JEDEC Standard 78
TDR1
Data Retention
ILTH1
Latch Up
Test Method
T13.0 1384
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a
higher minimum specification.
©2009 Silicon Storage Technology, Inc.
S71384-01-000
12
1/09
32 Mbit Multi-Purpose Flash Plus
SST39VF3201B / SST39VF3202B
Data Sheet
AC CHARACTERISTICS
TABLE 14: Read Cycle Timing Parameters VDD = 2.7-3.6V
Symbol
Parameter
Min
Max
Units
TRC
Read Cycle Time
70
TCE
Chip Enable Access Time
70
ns
TAA
Address Access Time
70
ns
TOE
Output Enable Access Time
35
ns
TCLZ1
TOLZ1
TCHZ1
TOHZ1
TOH1
TRP1
TRHR1
TRY1,2
CE# Low to Active Output
0
ns
OE# Low to Active Output
0
ns
ns
CE# High to High-Z Output
16
ns
OE# High to High-Z Output
16
ns
Output Hold from Address Change
0
ns
RST# Pulse Width
500
ns
RST# High before Read
50
RST# Pin Low to Read Mode
ns
20
µs
T14.0 1384
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. This parameter applies to Sector-Erase, Block-Erase, and Program operations.
This parameter does not apply to Chip-Erase operations.
TABLE 15: Program/Erase Cycle Timing Parameters
Symbol
Parameter
TBP
Word-Program Time
Min
Max
Units
10
µs
TAS
Address Setup Time
0
ns
TAH
Address Hold Time
30
ns
TCS
WE# and CE# Setup Time
0
ns
TCH
WE# and CE# Hold Time
0
ns
TOES
OE# High Setup Time
0
ns
TOEH
OE# High Hold Time
10
ns
TCP
CE# Pulse Width
40
ns
TWP
WE# Pulse Width
40
ns
TWPH
1
WE# Pulse Width High
30
ns
TCPH1
CE# Pulse Width High
30
ns
TDS
Data Setup Time
30
ns
TDH1
Data Hold Time
0
ns
TIDA
1
Software ID Access and Exit Time
150
ns
TSE
Sector-Erase
25
ms
TBE
Block-Erase
25
ms
TSCE
Chip-Erase
50
ms
T15.0 1384
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2009 Silicon Storage Technology, Inc.
S71384-01-000
13
1/09
32 Mbit Multi-Purpose Flash Plus
SST39VF3201B / SST39VF3202B
Data Sheet
TRC
TAA
ADDRESS AMS-0
TCE
CE#
TOE
OE#
TOHZ
TOLZ
VIH
WE#
TCLZ
TOH
HIGH-Z
DQ15-0
DATA VALID
TCHZ
DATA VALID
HIGH-Z
1384 F03.0
Note: AMS = Most significant address
AMS = A20 for SST39VF320xB
FIGURE 5: Read Cycle Timing Diagram
INTERNAL PROGRAM OPERATION STARTS
TBP
555
ADDRESS AMS-0
2AA
555
ADDR
TAH
TDH
TWP
WE#
TAS
TWPH
TDS
OE#
TCH
CE#
TCS
DQ15-0
XXAA
XX55
XXA0
DATA
SW0
SW1
SW2
WORD
(ADDR/DATA)
1384 F04.0
Note: AMS = Most significant address
AMS = A20 for SST39VF320xB
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.
FIGURE 6: WE# Controlled Program Cycle Timing Diagram
©2009 Silicon Storage Technology, Inc.
S71384-01-000
14
1/09
32 Mbit Multi-Purpose Flash Plus
SST39VF3201B / SST39VF3202B
Data Sheet
INTERNAL PROGRAM OPERATION STARTS
TBP
555
ADDRESS AMS-0
2AA
555
ADDR
TAH
TDH
TCP
CE#
TAS
TDS
TCPH
OE#
TCH
WE#
TCS
DQ15-0
XXAA
XX55
XXA0
DATA
SW0
SW1
SW2
WORD
(ADDR/DATA)
1384 F05.0
Note: AMS = Most significant address
AMS = A20 for SST39VF320xB
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.
FIGURE 7: CE# Controlled Program Cycle Timing Diagram
ADDRESS AMS-0
TCE
CE#
TOES
TOEH
OE#
TOE
WE#
DQ7
DATA
DATA#
DATA#
DATA
1384 F06.0
Note: AMS = Most significant address
AMS = A20 for SST39VF320xB
FIGURE 8: Data# Polling Timing Diagram
©2009 Silicon Storage Technology, Inc.
S71384-01-000
15
1/09
32 Mbit Multi-Purpose Flash Plus
SST39VF3201B / SST39VF3202B
Data Sheet
ADDRESS AMS-0
TCE
CE#
TOEH
TOES
TOE
OE#
WE#
DQ6 and DQ2
TWO READ CYCLES
WITH SAME OUTPUTS
1384 F07.0
Note: AMS = Most significant address
AMS = A20 for SST39VF320xB
FIGURE 9: Toggle Bits Timing Diagram
TSCE
SIX-BYTE CODE FOR CHIP-ERASE
ADDRESS AMS-0
555
2AA
555
555
2AA
555
CE#
OE#
TWP
WE#
DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX10
SW0
SW1
SW2
SW3
SW4
SW5
1384 F08.0
Note: This device also supports CE# controlled Chip-Erase operation The WE# and CE# signals are
interchangeable as long as minimum timings are met. (See Table 15)
AMS = Most significant address
AMS = A20 for SST39VF320xB
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.
FIGURE 10: WE# Controlled Chip-Erase Timing Diagram
©2009 Silicon Storage Technology, Inc.
S71384-01-000
16
1/09
32 Mbit Multi-Purpose Flash Plus
SST39VF3201B / SST39VF3202B
Data Sheet
TBE
SIX-BYTE CODE FOR BLOCK-ERASE
ADDRESS AMS-0
555
2AA
555
555
2AA
BAX
CE#
OE#
TWP
WE#
DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX30
SW0
SW1
SW2
SW3
SW4
SW5
Note: This
device also supports CE# controlled Block-Erase operation The WE# and CE# signals are
interchangeable as long as minimum timings are met. (See Table 15)
BAX = Block Address
AMS = Most significant address
AMS = A20 for SST39VF320xB
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
1384 F09.0
FIGURE 11: WE# Controlled Block-Erase Timing Diagram
TSE
SIX-BYTE CODE FOR SECTOR-ERASE
ADDRESS AMS-0
555
2AA
555
555
2AA
SAX
CE#
OE#
TWP
WE#
DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX50
SW0
SW1
SW2
SW3
SW4
SW5
Note: This device also
supports CE# controlled Sector-Erase operation The WE# and CE# signals are
interchangeable as long as minimum timings are met. (See Table 15)
SAX = Sector Address
AMS = Most significant address
AMS = A20 for SST39VF320xB
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
1384 F10.0
FIGURE 12: WE# Controlled Sector-Erase Timing Diagram
©2009 Silicon Storage Technology, Inc.
S71384-01-000
17
1/09
32 Mbit Multi-Purpose Flash Plus
SST39VF3201B / SST39VF3202B
Data Sheet
Three-Byte Sequence for Software ID Entry
ADDRESS A14-0
555
2AA
555
0000
0001
CE#
OE#
TIDA
TWP
WE#
TWPH
DQ15-0
TAA
XXAA
XX55
XX90
SW0
SW1
SW2
00BF
Device ID
1384 F11.0
Note: Device ID = 235DH for SST39VF3201B and 235CH for SST39VF3202B
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.
FIGURE 13: Software ID Entry and Read
Three-Byte Sequence for CFI Query Entry
ADDRESS A14-0
555
2AA
555
CE#
OE#
TIDA
TWP
WE#
TWPH
DQ15-0
TAA
XXAA
XX55
XX98
SW0
SW1
SW2
1384 F12.0
Note: WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.
FIGURE 14: CFI Query Entry and Read
©2009 Silicon Storage Technology, Inc.
S71384-01-000
18
1/09
32 Mbit Multi-Purpose Flash Plus
SST39VF3201B / SST39VF3202B
Data Sheet
THREE-BYTE SEQUENCE FOR
SOFTWARE ID EXIT AND RESET
ADDRESS A14-0
DQ15-0
555
2AA
XXAA
555
XX55
XXF0
TIDA
CE#
OE#
TWP
WE#
TWHP
SW0
SW1
1384 F13.0
SW2
Note: WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.
FIGURE 15: Software ID Exit/CFI Exit
THREE-BYTE SEQUENCE FOR
CFI QUERY ENTRY
ADDRESS AMS-0
555
2AA
555
CE#
OE#
TIDA
TWP
WE#
TWPH
DQ15-0
TAA
XXAA
XX55
XX88
SW0
SW1
SW2
1384 F14.0
Note: AMS = Most significant address
AMS = A20 for SST39VF320xB
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.
FIGURE 16: Sec ID Entry
©2009 Silicon Storage Technology, Inc.
S71384-01-000
19
1/09
32 Mbit Multi-Purpose Flash Plus
SST39VF3201B / SST39VF3202B
Data Sheet
TRP
RST#
CE#/OE#
TRHR
1384 F15.0
FIGURE 17: RST# Timing Diagram (When no internal operation is in progress)
TRP
RST#
TRY
CE#/OE#
End-of-Write Detection
(Toggle-Bit)
1384 F16.0
FIGURE 18: RST# Timing Diagram (During Program or Erase operation)
©2009 Silicon Storage Technology, Inc.
S71384-01-000
20
1/09
32 Mbit Multi-Purpose Flash Plus
SST39VF3201B / SST39VF3202B
Data Sheet
VIHT
INPUT
VIT
REFERENCE POINTS
VOT
OUTPUT
VILT
1384 F17.0
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points
for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.
Note: VIT - VINPUT Test
VOT - VOUTPUT Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test
FIGURE 19: AC Input/Output Reference Waveforms
TO TESTER
TO DUT
CL
1384 F18.0
FIGURE 20: A Test Load Example
©2009 Silicon Storage Technology, Inc.
S71384-01-000
21
1/09
32 Mbit Multi-Purpose Flash Plus
SST39VF3201B / SST39VF3202B
Data Sheet
Start
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XXA0H
Address: 555H
Load Word
Address/Word
Data
Wait for end of
Program (TBP,?
Data# Polling
bit, or Toggle bit
operation)
Program
Completed
X can be VIL or VIH, but no other value
1384 F19.0
FIGURE 21: Word-Program Algorithm
©2009 Silicon Storage Technology, Inc.
S71384-01-000
22
1/09
32 Mbit Multi-Purpose Flash Plus
SST39VF3201B / SST39VF3202B
Data Sheet
Internal Timer
Toggle Bit
Data# Polling
Program/Erase
Initiated
Program/Erase
Initiated
Program/Erase
Initiated
Wait TBP,
TSCE, TSE
or TBE
Read word
Read DQ7
Read same
word
Program/Erase
Completed
No
Is DQ7 =
true data?
Yes
No
Does DQ6
match?
Program/Erase
Completed
Yes
Program/Erase
Completed
1384 F20.0
FIGURE 22: Wait Options
©2009 Silicon Storage Technology, Inc.
S71384-01-000
23
1/09
32 Mbit Multi-Purpose Flash Plus
SST39VF3201B / SST39VF3202B
Data Sheet
CFI Query Entry
Command Sequence
Sec ID Query Entry
Command Sequence
Software Product ID Entry
Command Sequence
Load data: XXAAH
Address: 555H
Load data: XX98H
Address: 55H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Wait TIDA
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX98H
Address: 555H
Read CFI data
Load data: XX88H
Address: 555H
Load data: XX90H
Address: 555H
Wait TIDA
Wait TIDA
Wait TIDA
Read CFI data
Read Sec ID
Read Software ID
X can be VIL or VIH, but no other value
1384 F21.0
FIGURE 23: Software ID/CFI Entry Command Flowcharts
©2009 Silicon Storage Technology, Inc.
S71384-01-000
24
1/09
32 Mbit Multi-Purpose Flash Plus
SST39VF3201B / SST39VF3202B
Data Sheet
Software ID Exit/CFI Exit/Sec ID Exit
Command Sequence
Load data: XXAAH
Address: 555H
Load data: XXF0H
Address: XXH
Load data: XX55H
Address: 2AAH
Wait TIDA
Load data: XXF0H
Address: 555H
Return to normal
operation
Wait TIDA
Return to normal
operation
X can be VIL or VIH, but no other value
1384 F22.0
FIGURE 24: Software ID/CFI Exit Command Flowcharts
©2009 Silicon Storage Technology, Inc.
S71384-01-000
25
1/09
32 Mbit Multi-Purpose Flash Plus
SST39VF3201B / SST39VF3202B
Data Sheet
Chip-Erase
Command Sequence
Sector-Erase
Command Sequence
Block-Erase
Command Sequence
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX80H
Address: 555H
Load data: XX80H
Address: 555H
Load data: XX80H
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX10H
Address: 555H
Load data: XX50H
Address: SAX
Load data: XX30H
Address: BAX
Wait TSCE
Wait TSE
Wait TBE
Chip erased
to FFFFH
Sector erased
to FFFFH
Block erased
to FFFFH
X can be VIL or VIH, but no other value
1384 F23.0
FIGURE 25: Erase Command Sequence
©2009 Silicon Storage Technology, Inc.
S71384-01-000
26
1/09
32 Mbit Multi-Purpose Flash Plus
SST39VF3201B / SST39VF3202B
Data Sheet
PRODUCT ORDERING INFORMATION
SST
39
XX
VF 320 2B
XX XXX XB
-
70
XX
-
4C
XX
-
EK E
XX X
Environmental Attribute
E1 = non-Pb
Package Modifier
K = 48 balls or leads
Package Type
E = TSOP (type1, die up, 12mm x 20mm)
B3 = TFBGA (6mm x 8mm, 0.8mm pitch)
Temperature Range
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
70 = 70 ns
Hardware Block Protection
1 = Bottom Boot-Block
2 = Top Boot-Block
Device Density
320= 32Mbit
Voltage
V = 2.7-3.6V
Product Series
39 = Multi-Purpose Flash Plus
1. Environmental suffix “E” denotes non-Pb solder.
SST non-Pb solder devices are “RoHS Compliant”.
Valid Combinations for SST39VF3201B
SST39VF3201B-70-4C-EKE
SST39VF3201B-70-4I-EKE
SST39VF3201B-70-4C-B3KE
SST39VF3201B-70-4I-B3KE
Valid Combinations for SST39VF3202B
SST39VF3202B-70-4C-EKE
SST39VF3202B-70-4I-EKE
SST39VF3202B-70-4C-B3KE
SST39VF3202B-70-4I-B3KE
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
©2009 Silicon Storage Technology, Inc.
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32 Mbit Multi-Purpose Flash Plus
SST39VF3201B / SST39VF3202B
Data Sheet
PACKAGING DIAGRAMS
1.05
0.95
Pin # 1 Identifier
0.50
BSC
0.27
0.17
12.20
11.80
0.15
0.05
18.50
18.30
DETAIL
1.20
max.
0.70
0.50
20.20
19.80
0°- 5°
Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions,
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (max/min).
3. Coplanarity: 0.1 mm
4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.
0.70
0.50
1mm
48-tsop-EK-8
FIGURE 26: 48-lead Thin Small Outline Package (TSOP) 12mm x 20mm,
SST Package Code: EK
©2009 Silicon Storage Technology, Inc.
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32 Mbit Multi-Purpose Flash Plus
SST39VF3201B / SST39VF3202B
Data Sheet
TOP VIEW
BOTTOM VIEW
8.00 ± 0.20
5.60
0.45 ± 0.05
(48X)
0.80
6
6
5
5
4.00
4
4
6.00 ± 0.20
3
3
2
2
1
1
0.80
A B C D E F G H
A1 CORNER
SIDE VIEW
H G F E D C B A
A1 CORNER
1.10 ± 0.10
0.12
SEATING PLANE
1mm
0.35 ± 0.05
Note:
1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
4. Ball opening size is 0.38 mm (± 0.05 mm)
48-tfbga-B3K-6x8-450mic-4
FIGURE 27: 48-ball Thin-profile, Fine-pitch Ball Grid Array (TFBGA) 6mm x 8mm,
SST Package Code: B3K
TABLE 16: Revision History
Number
Description
Date
00
•
Initial release
Mar 2008
01
•
•
Changed 1V per 100 µs to 1V per 100 ms in Power Up Specifications on page 11
Changed status from Preliminary Specifications to Data Sheet
Jan 2009
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.sst.com
©2009 Silicon Storage Technology, Inc.
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