FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 SST89E/V564 SST89E/VE554 FlashFlex51 MCU Preliminary Specifications FEATURES: • 8-bit 8051 Family Compatible Microcontroller (MCU) with Embedded SuperFlash Memory • SST89E564/SST89E554 is 5V Operation – 0 to 40 MHz Operation at 5V • SST89V564/SST89V554 is 3V Operation – 0 to 25 MHz Operation at 3V • Fully Software and Development Toolset Compatible as well as Pin-For-Pin Package Compatible with Standard 8xC5x Microcontrollers • 1 KByte Register/Data RAM • Dual Block SuperFlash EEPROM – SST89E564/SST89V564: 64 KByte primary block + 8 KByte secondary block (128-Byte sector size) – SST89E554/SST89V554: 32 KByte primary block + 8 KByte secondary block (128-Byte sector size) – Individual Block Security Lock – Concurrent Operation during In-Application Programming (IAP) – Block Address Re-mapping • Support External Address Range up to 64 KByte of Program and Data Memory • Three High-Current Drive Pins (16 mA each) • Three 16-bit Timers/Counters • Full-Duplex Enhanced UART – Framing error detection – Automatic address recognition • Eight Interrupt Sources at 4 Priority Levels • Watchdog Timer (WDT) • Four 8-bit I/O Ports (32 I/O Pins) • Second DPTR register • Reduce EMI Mode (Inhibit ALE through AUXR SFR) • SPI Serial Interface • TTL- and CMOS-Compatible Logic Levels • Brown-out Detection • Extended Power-Saving Modes – Idle Mode – Power Down Mode with External Interrupt Wake-up – Standby (Stop Clock) Mode • PDIP-40, PLCC-44 and TQFP-44 Packages • Temperature Ranges: – Commercial (0°C to +70°C) – Industrial (-40°C to +85°C) PRODUCT DESCRIPTION device can be configured as a slave to an external host for source code storage or as a master to an external host for In-Application Programming (IAP) operation. The device is designed to be programmed “In-System” and “In-Application” on the printed circuit board for maximum flexibility. The device is pre-programmed with an example of bootstrap loader in the memory, demonstrating the initial user program code loading or subsequent user code updating via the “IAP” operation. An example of bootstrap loader is for the user’s reference and convenience only. SST does not guarantee the functionality or the usefulness of the sample bootstrap loader. Chip-Erase or Block-Erase operations will erase the pre-programmed sample code. SST89E564, SST89V564, SST89E554, and SST89V554 are members of the FlashFlex51 family of 8-bit microcontrollers. The FlashFlex51 is a family of microcontroller products designed and manufactured on the state-of-the-art SuperFlash CMOS semiconductor process technology. The device uses the same powerful instruction set and is pin-forpin compatible with standard 8xC5x microcontroller devices. The device comes with 72/40 KByte of on-chip flash EEPROM program memory using SST’s patented and proprietary CMOS SuperFlash EEPROM technology with the SST’s field-enhancing, tunneling injector, split-gate memory cells. The SuperFlash memory is partitioned into 2 independent program memory blocks. The primary SuperFlash Block 0 occupies 64/32 KByte of internal program memory space and the secondary SuperFlash Block 1 occupies 8 KByte of internal program memory space. The 8-KByte secondary SuperFlash block can be mapped to the lowest location of the 64/32 KByte address space; it can also be hidden from the program counter and used as an independent EEPROM-like data memory. The flash memory blocks can be programmed via a standard 87C5x OTP EPROM programmer fitted with a special adapter and firmware for SST’s device. During the power-on reset, the ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 384 1 In addition to 72/40 KByte of SuperFlash EEPROM program memory on-chip, the device can address up to 64 KByte of external program memory. In addition to 1024 x 8 bits of on-chip RAM, up to 64 KByte of external RAM can be addressed. SST’s highly reliable, patented SuperFlash technology and memory cell architecture have a number of important advantages for designing and manufacturing flash EEPROMs. These advantages translate into significant cost and reliability benefits for our customers. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. FlashFlex, In-Application Programming, IAP, and SoftLock are trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice. FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications TABLE OF CONTENTS PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 LIST OF FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 LIST OF TABLES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.0 FUNCTIONAL BLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.0 PIN ASSIGNMENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.0 MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 Program Memory Block Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2.1 Reset Configuration of Program Memory Block Switching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 Dual Data Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.5 Special Function Registers (SFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.0 FLASH MEMORY PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1 External Host Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1.1 Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.2 Arming Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.3 Detail Explanation of the External Host Mode Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.4 External Host Mode Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.5 Flash Operation Status Detection Via External Host Handshake . . . . . . . . . . . . . . . . . . . . . . . . 4.1.6 Step-by-step instructions to perform External Host Mode commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.7 Flash Memory Programming Timing Diagrams with External Host Mode . . . . . . . . . . . . . . . . . . 26 26 26 27 27 27 28 4.2 In-Application Programming Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 In-Application Programming Mode Clock Source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Bank Selection for In-Application Programming Mode. . . . . . . . . . . . . . . . . . . . . . . . . . IAP Enable Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . In-Application Programming Mode Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Polling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 33 33 33 34 34 5.0 TIMERS/COUNTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.0 SERIAL I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1 Enhanced Universal Aysnchronous Receiver/Transmitter (UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1.1 Framing Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1.2 Automatic Address Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.2 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 2 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications 7.0 WATCHDOG TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.0 SECURITY LOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.1 Hard Lock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.2 SoftLock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.3 Security Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.0 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.1 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.2 Software Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.3 Brown-out Detection Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.4 Interrupt Priority and Polling Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.5 Power-Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.5.1 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.5.2 Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.5.3 Standby Mode (Stop Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.6 Clock Input Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.7 Recommended Capacitor Values for Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.0 ELECTRICAL SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Absolute Maximum Stress Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.1 Operation Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.2 Reliability Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.3 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10.4 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.5 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.0 PRODUCT ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.1 Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 12.0 PACKAGING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 3 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications LIST OF FIGURES FIGURE 2-1: Pin Assignments for 40-pin PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 FIGURE 2-2: Pin Assignments for 44-lead TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 FIGURE 2-3: Pin Assignments for 44-lead PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 FIGURE 3-1: Program Memory Organization for SST89E564 and SST89V564 . . . . . . . . . . . . . . . . . . . . . 10 FIGURE 3-2: Program Memory Organization for SST89E554 and SST89V554 . . . . . . . . . . . . . . . . . . . . . 11 FIGURE 4-1: I/O Pin Assignments for External Host Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 FIGURE 4-2: Read-ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 FIGURE 4-3: Select-Block1 / Select-Block0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 FIGURE 4-4: Chip-Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 FIGURE 4-5: Block-Erase for SST89E564/SST89V564 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 FIGURE 4-6: Block-Erase for SST89E554/SST89V554 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 FIGURE 4-7: Sector-Erase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 FIGURE 4-8: Byte-Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 FIGURE 4-9: Prog-SB1 / Prog-SB2 / Prog-SB3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 FIGURE 4-10: Prog-SC0 / Prog-SC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 FIGURE 4-11: Byte-Verify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 FIGURE 6-1: SPI Master-slave Interconnection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 FIGURE 6-2: SPI Transfer Format with CPHA = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 FIGURE 6-3: SPI Transfer Format with CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 FIGURE 7-1: Block Diagram of Programmable Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 FIGURE 8-1: Security Lock Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 FIGURE 9-1: Power-on Reset Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 FIGURE 9-2: Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 FIGURE 10-1: IDD Test Condition, Active Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 FIGURE 10-2: IDD Test Condition, Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 FIGURE 10-3: IDD Test Condition, Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 FIGURE 10-4: IDD Test Condition, Standby (Stop Clock) Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 FIGURE 10-5: AC Testing Input/Output, Float Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 FIGURE 10-6: External Program Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 FIGURE 10-7: External Data Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 FIGURE 10-8: External Data Memory Write Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 FIGURE 10-9: External Clock Drive Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 FIGURE 10-10: Shift Register Mode Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 4 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications LIST OF TABLES TABLE 2-1: Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 TABLE 3-1: SFCF Values for Program Memory Block Switching for SST89E564/SST89V564 . . . . . . . . 11 TABLE 3-2: SFCF Values for Program Memory Block Switching for SST89E554/SST89V554 . . . . . . . . 12 TABLE 3-3: SFCF Values Under Different Reset Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 TABLE 3-4: FlashFlex51 SFR Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 TABLE 3-5: CPU related SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 TABLE 3-6: Flash Memory Programming SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 TABLE 3-7: Watchdog Timer SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 TABLE 3-8: Timer/Counters SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 TABLE 3-9: Interface SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 TABLE 4-1: External Host Mode Commands for SST89E564/SST89V564. . . . . . . . . . . . . . . . . . . . . . . . 24 TABLE 4-2: External Host Mode Commands for SST89E554/SST89V554. . . . . . . . . . . . . . . . . . . . . . . . 25 TABLE 4-3: Signature Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 TABLE 4-4: IAP Address Resolution for SST89E564/SST89V564 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 TABLE 4-5: In-Application Programming Mode Commands for SST89E564/SST89V564 . . . . . . . . . . . . 35 TABLE 4-6: In-Application Programming Mode Commands for SST89E554/SST89V554 . . . . . . . . . . . . 35 TABLE 4-7: Flash Memory Programming/Verification Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 TABLE 8-1: Security Lock Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 TABLE 8-2: Security Lock Access Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 TABLE 9-1: Interrupt Polling Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 TABLE 9-2: Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 TABLE 10-1: Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 TABLE 10-2: Reliability Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 TABLE 10-3: DC Electrical Characteristics: 40MHz devices; 4.5-5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 TABLE 10-4: DC Electrical Characteristics: 25MHz devices; 2.7-3.6V . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 TABLE 10-5: AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 TABLE 10-6: External Clock Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 TABLE 10-7: Serial Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 5 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications 1.0 FUNCTIONAL BLOCKS FUNCTIONAL BLOCK DIAGRAM Interrupt Control Watchdog Timer 8 Interrupts 8051 CPU Core SuperFlash EEPROM Primary Block 32K/64K x81 RAM 1K x8 Secondary Block 8K x8 I/O I/O Port 0 8 I/O I/O Port 1 Security Lock 8 I/O I/O Port 2 8 Timer 0 (16-bits) I/O Port 3 Timer 1 (16-bits) SPI Timer 2 (16-bits) 8-bit Enhanced UART I/O 384 ILL B1.4 1. 64K x8 for SST89E564 and SST89V564 32K x8 for SST89E554 and SST89V554 ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 6 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications 2.0 PIN ASSIGNMENTS P0.2 (AD2) (SS#) P1.4 5 36 P0.3 (AD3) (MOSI) P1.5 6 35 P0.4 (AD4) (MOSI) P1.5 1 33 P0.4 (AD4) (MISO) P1.6 7 34 40-pin PDIP 8 Top View 33 32 9 P0.5 (AD5) (MISO) P1.6 2 32 P0.5 (AD5) P0.6 (AD6) (SCK) P1.7 3 31 P0.6 (AD6) P0.7 (AD7) RST 4 30 P0.7 (AD7) (RXD) P3.0 5 29 EA# Reserved 6 28 Reserved (TXD) P3.1 7 27 ALE/PROG# (INT0#) P3.2 8 26 PSEN# 9 25 P2.7 (A15) (SCK) P1.7 RST (RXD) P3.0 10 31 P1.2 P0.3 (AD3) 37 P0.2 (AD2) 4 P0.1 (AD1) P0.1 (AD1) P1.3 P0.0 (AD0) 38 VDD 3 Reserved P0.0 (AD0) P1.2 P1.0 (T2) VDD 39 P1.1 (T2 Ex) 40 2 P1.3 1 P1.4 (SS#) (T2) P1.0 (T2 Ex) P1.1 44 43 42 41 40 39 38 37 36 35 34 EA# 44-lead TQFP Top View P2.7 (A15) (INT1#) P3.3 (T0) P3.4 14 27 P2.6 (A14) (T0) P3.4 10 24 P2.6 (A14) (T1) P3.5 15 26 P2.5 (A13) (T1) P3.5 P2.5 (A13) (WR#) P3.6 16 25 P2.4 (A12) 23 11 12 13 14 15 16 17 18 19 20 21 22 (RD#) P3.7 17 24 P2.3 (A11) XTAL2 18 23 P2.2 (A10) XTAL1 19 22 P2.1 (A9) VSS 20 21 P2.0 (A8) (A12) P2.4 28 (A11) P2.3 13 (A10) P2.2 (INT1#) P3.3 (A9) P2.1 PSEN# (A8) P2.0 29 Reserved 12 VSS (INT0#) P3.2 XTAL1 ALE/PROG# XTAL2 30 (RD#) P3.7 11 (WR#) P3.6 (TXD) P3.1 384 ILL F19.5 384 ILL F18.3 2 1 44 43 42 41 40 VDD P0.3 (AD3) 3 P0.2 (AD2) 4 P0.1 (AD1) P1.0 (T2) 5 P0.0 (AD0) P1.1 (T2 Ex) 6 Reserved P1.2 2-2: PIN ASSIGNMENTS FOR 44-LEAD TQFP P1.3 FIGURE P1.4 (SS#) 2-1: PIN ASSIGNMENTS FOR 40-PIN PDIP (MOSI) P1.5 7 39 P0.4 (AD4) (MISO) P1.6 8 38 P0.5 (AD5) (SCK) P1.7 9 37 P0.6 (AD6) 36 P0.7 (AD7) 35 EA# 34 Reserved ALE/PROG# (RXD) P3.0 11 Reserved 12 (TXD) P3.1 13 33 (INT0#) P3.2 14 32 PSEN# (INT1#) P3.3 15 31 P2.7 (A15) (T0) P3.4 16 30 P2.6 (A14) (T1) P3.5 17 29 18 19 20 21 22 23 24 25 26 27 28 P2.5 (A13) (A11) P2.3 (A10) P2.2 (A9) P2.1 (A8) P2.0 Reserved VSS XTAL1 XTAL2 (RD#) P3.7 44-lead PLCC Top View (A12) P2.4 RST 10 (WR#) P3.6 FIGURE 384 ILL F20.4 FIGURE 2-3: PIN ASSIGNMENTS FOR 44-LEAD PLCC ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 7 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications 2.1 Pin Descriptions TABLE 2-1: PIN DESCRIPTIONS (1 OF 2) Symbol Type1 P0[7:0] I/O P1[7:0] P1[0] Name and Functions Port 0: Port 0 is an 8-bit open drain bi-directional I/O port. As an output port each pin can sink several LS TTL inputs. Port 0 pins float that have “1”s written to them, and in this state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external memory. In this application, it uses strong internal pullups when transitioning to VOH. Port 0 also receives the code bytes during the external host mode programming, and outputs the code bytes during the external host mode verification. External pull-ups are required during program verification. I/O with internal Port 1: Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers pull-ups can drive LS TTL inputs. Port 1 pins are pulled high by the internal pull-ups when “1”s are written to them and can be used as inputs in this state. As inputs, Port 1 pins that are externally pulled low will source current (IIL, see Tables 10-3 and 10-4) because of the internal pullups. P1[5, 6, 7] have high current drive of 16 mA. Port 1 also receives the low-order address bytes during the external host mode programming and verification. I/O T2: External count input to Timer/Counter 2 or Clock-out from Timer/Counter 2 P1[1] I P1[4] I/O SS#: Master Input or Slave Output for SPI P1[5] I/O MOSI: Master Output line, Slave Input line for SPI P1[6] I/O MISO: Master Input line, Slave Output line for SPI I/O SCK: Master clock output, slave clock input line for SPI P1[7] T2EX: Timer/Counter 2 capture/reload trigger and direction control P2[7:0] I/O with internal Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins are pulled pull-ups high by the internal pull-ups when “1”s are written to them and can be used as inputs in this state. As inputs, Port 2 pins that are externally pulled low will source current (IIL, see Tables 10-3 and 10-4) because of the internal pull-ups. Port 2 sends the high-order address byte during fetches from external Program memory and during accesses to external Data Memory that use 16-bit address (MOVX@DPTR). In this application, it uses strong internal pull-ups when transitioning to VOH. Port 2 also receives some control signals and a partial of highorder address bits during the external host mode programming and verification. P3[7:0] I/O with internal Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers pull-ups can drive LS TTL inputs. Port 3 pins are pulled high by the internal pull-ups when “1”s are written to them and can be used as inputs in this state. As inputs, Port 3 pins that are externally pulled low will source current (IIL, see Tables 10-3 and 10-4) because of the internal pullups. Port 3 also receives some control signals and a partial of high-order address bits during the external host mode programming and verification. P3[0] I RXD: Serial input line P3[1] O TXD: Serial output line P3[2] I INT0#: External Interrupt 0 Input P3[3] I INT1#: External Interrupt 1 Input P3[4] I T0: External count input to Timer/Counter 0 P3[5] I T1: External count input to Timer/Counter 1 P3[6] O WR#: External Data Memory Write strobe P3[7] O RD#: External Data Memory Read strobe PSEN# I/O Program Store Enable: PSEN# is the Read strobe to External Program Store. When the device is executing from Internal Program Memory, PSEN# is inactive (VOH). When the device is executing code from External Program Memory, PSEN# is activated twice each machine cycle, except when access to External Data Memory while one PSEN# activation is skipped in each machine cycle. A forced high-to-low input transition on the PSEN# pin while the RST input is continually held high for more than ten machine cycles will cause the device to enter External Host mode for programming. ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 8 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications TABLE 2-1: PIN DESCRIPTIONS (CONTINUED) (2 OF 2) Symbol Type1 RST I Reset: While the oscillator is running, a high logic state on this pin for two machine cycles will reset the device. After a reset, if the PSEN# pin is driven by a high-to-low input transition while the RST input pin is held high, the device will enter the External Host mode, otherwise the device will enter the Normal operation mode. EA# I External Access Enable: EA# must be driven to VIL in order to enable the device to fetch code from the External Program Memory. EA# must be driven to VIH for internal program execution. However, Security lock level 4 will disable EA#, and program execution is only possible from internal program memory. The EA# pin can tolerate a high voltage2 of 12V (see “Absolute Maximum Stress Ratings” on page 47). ALE/PROG# I/O Address Latch Enable: ALE is the output signal for latching the low byte of the address during accesses to external memory. This pin is also the programming pulse input (PROG#) for the external host mode. ALE is activated twice each machine cycle, except when access to External Data Memory, one ALE activation is skipped in the second machine cycle. However, if AO is set to 1, ALE is disabled. (see “Auxiliary Register (AUXR)” on page 20) XTAL1 XTAL2 I O Oscillator: Input and output to the inverting oscillator amplifier. XTAL1 is input to internal clock generation circuits from an external clock source. VDD I Power Supply: Supply voltage during normal, Idle, Power Down, and Standby Mode operations. Vss I Ground: Circuit ground. (0V reference) Name and Functions T2-1.6 384 1. I = Input; O = Output 2. It is not necessary to receive a 12V programming supply voltage during flash programming. ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 9 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications 3.0 MEMORY ORGANIZATION The device has separate address spaces for program and data memory. Bank Selection. Please refer to Figure 3-1 and Figure 3-2 for the program memory configurations. Program Bank Select is described in the next section. 3.1 Program Memory The 64K/32K x8 primary SuperFlash block is organized as 512/256 sectors, each sector consists of 128 Bytes. There are two internal flash memory blocks in the device. The primary flash memory block (Block 0) has 64/32 KByte. The secondary flash memory block (Block 1) has 8 KByte. Since the total program address space is limited to 64/32 KByte, the SFCF[1:0] bit are used to control Program The 8K x8 secondary SuperFlash block is organized as 64 sectors, each sector consists also of 128 Bytes. For both blocks, the 7 least significant program address bits select the byte within the sector. The remainder of the program address bits select the sector within the block. EA# = 1 SFCF[1:0] = 00 EA# = 0 FFFFH FFFFH EA# = 1 SFCF[1:0] = 01, 10, 11 FFFFH 56 KByte Block 0 64 KByte Block 0 External 64 KByte 2000H 1FFFH 8 KByte Block 1 0000H 0000H 0000H 384 ILL F48.5 FIGURE 3-1: PROGRAM MEMORY ORGANIZATION FOR ©2001 Silicon Storage Technology, Inc. SST89E564 AND SST89V564 S71181-03-000 9/01 10 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications FFFFH FFFFH FFFFH EA# = 1 SFCF[1:0] = 01 EA# = 1 SFCF[1:0] = 00 EA# = 0 8 KByte Block 1 8 KByte Block 1 E000H DFFFH E000H External 32 KByte DFFFH External 24 KByte External 64 KByte EA# = 1 SFCF[1:0] = 10, 11 FFFFH External 24 KByte 8000H 7FFFH 8000H 7FFFH 8000H 7FFFH 24 KByte Block 0 2000H 32 KByte Block 0 32 KByte Block 0 1FFFH 8 KByte Block 1 0000H 0000H 0000H 0000H 384 ILL F48b.3 FIGURE 3-2: PROGRAM MEMORY ORGANIZATION FOR SST89E554 AND SST89V554 3.2 Program Memory Block Switching The program memory block switching feature of the device allows either Block 1 or the lowest 8 KByte of Block 0 to be used for the lowest 8 KByte of the program address space. SFCF[1:0] controls program memory block switching. TABLE 3-1: SFCF VALUES FOR PROGRAM MEMORY BLOCK SWITCHING FOR SST89E564/SST89V564 SFCF[1:0] Program Memory Block Switching 01, 10, 11 Block 1 is not visible to the PC; Block 1 is reachable only via In-Application Programming from 000H - 1FFFH. 00 Block 1 is overlaid onto the low 8K of the program address space; occupying address locations 0000H - 1FFFH. When the PC falls within 0000H - 1FFFH, the instruction will be fetched from Block 1 instead of Block 0. Outside of 0000H - 1FFFH, Block 0 is used. Locations 0000H - 1FFFH of Block 0 are reachable through In-Application Programming. T3-1.0 384 ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 11 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications TABLE 3-2: SFCF VALUES SFCF[1:0] 10, 11 FOR PROGRAM MEMORY BLOCK SWITCHING FOR SST89E554/SST89V554 Program Memory Block Switching Block 1 is not visible to the PC; Block 1 is reachable only via In-Application Programming from E000H - FFFFH. 01 Both Block 0 and Block 1 are visible to the PC. Block 0 is occupied from 0000H - 7FFFH. Block 1 is occupied from E000H - FFFFH. 00 Block 1 is overlaid onto the low 8K of the program address space; occupying address locations 0000H - 1FFFH. When the PC falls within 0000H - 1FFFH, the instruction will be fetched from Block 1 instead of Block 0. Outside of 0000H - 1FFFH, Block 0 is used. Locations 0000H - 1FFFH of Block 0 are reachable through In-Application Programming. T3-2.2 384 3.3 Data Memory 3.2.1 Reset Configuration of Program Memory Block Switching The device has 1024 x 8 bits of on-chip RAM and can address up to 64 KByte of external data memory. Program memory block switching is initialized after reset according to the state of the Start-up Configuration bit SC0. The SC0 bit is programmed via an External Host Mode command or an IAP Mode command. See Table 4-2 and Table 4-6. The device has four sections of internal data memory: 1. The lower 128 Bytes of RAM (00H to 7FH) are directly and indirectly addressable. Once out of reset, the SFCF[0] bit can be changed dynamically by the program for desired effects. Changing SFCF[0] will not change the SC0 bit. 2. The higher 128 Bytes of RAM (80H to FFH) are indirectly addressable. 3. The Special Function Registers (SFRs, 80H to FFH) are directly addressable only. Caution must be taken when dynamically changing the SFCF[0] bit. Since this will cause different physical memory to be mapped to the logical program address space. The user must avoid executing block switching instructions within the address range 0000H to 1FFFH. TABLE 4. The expanded RAM of 768 Bytes (00H to 2FFH) is indirectly addressable by the move external instruction (MOVX) and clearing the EXTRAM bit. (See “Auxiliary Register (AUXR)” on page 20) 3-3: SFCF VALUES UNDER DIFFERENT RESET CONDITIONS 3.4 Dual Data Pointers The device has two 16-bit data pointers. The DPTR Select (DPS) bit in AUXR1 determines which of the two data pointers is accessed. When DPS=0, DPTR0 is selected; when DPS=1, DPTR1 is selected. Quickly switching between the two data pointers can be accomplished by a single INC instruction on AUXR1. State of SFCF[1:0] after: Power-on or External Reset WDT Reset or Brown-out Reset Software Reset SC11 SC0 1 1 00 (default) x0 10 1 0 01 x1 11 0 1 10 10 10 0 0 11 11 3.5 Special Function Registers (SFR) Most of the unique features of the FlashFlex51 microcontroller family are controlled by bits in special function registers (SFRs) located in the SFR Memory Map shown in Table 3-4. Individual descriptions of each SFR are provided and Reset values indicated in Tables 3-5 to 3-9. 11 T3-3.2 384 1. SC1 only applies to SST89E554 and SST89V554. ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 12 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications TABLE 3-4: FLASHFLEX51 SFR MEMORY MAP 8 BYTES F8H IPA1 FFH F0H B1 E8H IEA1 EFH E0H ACC1 E7H IPAH D8H F7H DFH D0H PSW1 C8H T2CON1 C0H WDTC1 B8H IP1 B0H P31 SFCF SFCM A8H IE1 SADDR SPSR A0H P21 98H SCON1 90H P11 88H TCON1 TMOD TL0 TL1 80H P01 SP DPL DPH T2MOD RCAP2L RCAP2H TL2 SPCR D7H TH2 CFH C7H SADEN BFH SFAL SFAH SFDT SFST IPH B7H AFH AUXR1 A7H SBUF 9FH 97H TH0 TH1 AUXR WDTD SPDR 8FH PCON 87H T3-4.3 384 1. SFRs are bit addressable. ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 13 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications TABLE 3-5: CPU RELATED Symbol Description SFRS Direct Address Bit Address, Symbol, or Alternative Port Function MSB LSB RESET Value ACC1 Accumulator B1 B Register F0H PSW1 Program Status Word D0H SP Stack Pointer 81H SP[7:0] 07H DPL Data Pointer Low 82H DPL[7:0] 00H DPH Data Pointer High 83H DPH[7:0] 00H IE1 Interrupt Enable A8H EA - ET2 ES0 ET1 EX1 ET0 EX0 40H IEA1 Interrupt Enable A E8H - - - - EBO - - - xxxx0xxxb IP1 Interrupt Priority Reg B8H - - PT2 PS PT1 PX1 PT0 PX0 xx000000b IPH Interrupt Priority Reg High B7H - - PT2H PSH PT1H PX1H PT0H PX0H xx000000b IPA1 Interrupt Priority Reg A F8H - - - - PBO - - - xxxx0xxxb IPAH Interrupt Priority Reg A High F7H - - - - PBO H - - - xxxx0xxxb PCON Power Control 87H BOF POF GF1 GF0 PD IDL 00010000b AUXR Auxiliary Reg 8EH - - - - - - EXTRAM AO xxxxxxx00b AUXR1 Auxiliary Reg 1 A2H - - - - GF2 0 - DPS xxxx00x0b E0H ACC[7:0] 00H B[7:0] CY AC SMOD1 SMOD0 F0 RS1 00H RS0 OV F1 P 00H T3-5.10 384 1. Bit Addressable SFRs TABLE 3-6: FLASH MEMORY PROGRAMMING SFRS Symbol Description Bit Address, Symbol, or Alternative Port Function Direct Address MSB LSB RESET Value SFST SuperFlash Status B6H SECD1 SECD2 SECD3 - - FLASH_BUSY - - xxxxx0xxb SFCF SuperFlash Configuration B1H - IAPEN - - - - SWR BSEL x0xxxxxxb SFCM SuperFlash Command B2H FIE SFDT SuperFlash Data B5H SuperFlash Data Register 00H SFAL SuperFlash Address Low B3H SuperFlash Low Order Byte Address Register - A7 toA0 (SFAL) 00H SFAH SuperFlash Address High B4H SuperFlash High Order Byte Address Register - A15 toA8 (SFAH) 00H FCM 00H T3-6.6 384 ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 14 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications TABLE 3-7: WATCHDOG TIMER SFRS Direct Address Symbol Description WDTC1 Watchdog Timer Control C0H WDTD Watchdog Timer Data/Reload 85H Bit Address, Symbol, or Alternative Port Function MSB - - - WDOUT WDRE WDTS WDT LSB RESET Value SWDT xxx00x00b Watchdog Timer Data/Reload 00H T3-7.3 384 1. Bit Addressable SFRs TABLE 3-8: TIMER/COUNTERS SFRS Direct Address Bit Address, Symbol, or Alternative Port Function MSB LSB RESET Value Symbol Description TMOD Timer/Counter Mode Control 89H TCON1 Timer/Counter Control 88H TH0 Timer 0 MSB 8CH TL0 Timer 0 LSB 8AH TL0[7:0] 00H TH1 Timer 1 MSB 8DH TH1[7:0] 00H TL1 Timer 1 LSB Timer 1 Timer 0 00H GATE C/T# M1 M0 GATE C/T# M1 M0 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 TH0[7:0] 8BH 00H TL1[7:0] T2CON1 Timer / Counter 2 Control C8H TF2 T2MOD# Timer2 Mode Control C9H - EXF2 RCLK TCLK EXEN2 - - - - 00H 00H TR2 - C/T2# CP/RL2# T2OE DCEN 00H xxxxxx00b TH2 Timer 2 MSB CDH TH2[7:0] 00H TL2 Timer 2 LSB CCH TL2[7:0] 00H RCAP2H Timer 2 Capture MSB CBH RCAP2H[7:0] 00H RCAP2L Timer 2 Capture LSB CAH RCAP2L[7:0] 00H T3-8.3 384 1. Bit Addressable SFRs ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 15 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications TABLE 3-9: INTERFACE SFRS Symbol Description SBUF Serial Data Buffer SCON1 Serial Port Control Direct Address Bit Address, Symbol, or Alternative Port Function MSB LSB 99H 98H SBUF[7:0] SM0/FE SM1 SM2 REN RESET Value Indeterminate TB8 RB8 TI RI 00H SADDR Slave Address A9H SADDR#[7:0] 00H SADEN Slave Address Mask B9H SADEN#[7:0] 00H SPCR SPI Control Register D5H SPIE SPE SPSR SPI Status Register AAH SPIF WCOL SPDR SPI Data Register 86H SPD7 SPD6 SPD5 P01 Port 0 80H P11 Port 1 90H - - - - P21 Port 2 A0H P31 Port 3 B0H RD# WR# T1 T0 DORD MSTR CPOL CPHA SPR1 SPR0 04H 00H SPD4 SPD3 SPD2 SPD1 SPD0 00H T2EX T2 FFH TXD RXD P0[7:0] FFH - - P2[7:0] INT1# INT0# FFH FFH T3-9.4 384 1. Bit Addressable SFRs ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 16 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications SuperFlash Status Register (SFST) (Read Only Register) Location 7 6 5 4 3 2 1 0 Reset Value 0B6H SECD1 SECD2 SECD3 - - FLASH_BUSY - - xxxxx0xxb Symbol Function SECD1 Security bit 1. SECD2 Security bit 2. SECD3 Security bit 3. Please refer to Table 4-6 for security lock options. FLASH_BUSYFlash operation completion polling bit. 1: Device is busy with flash operation. 0: Device has fully completed the last command. SuperFlash Configuration Register (SFCF) Location 7 6 5 4 3 2 1 0 Reset Value 0B1H - IAPEN - - - - SWR BSEL x0xxxxxxb Symbol Function IAPEN Enable IAP operation 0: IAP commands are disabled 1: IAP commands are enabled SWR Software Reset See “9.2 Software Reset” on page 43 BSEL Program memory block switching bit See Figures 3-1 and 3-2. SuperFlash Command Register (SFCM) Location 7 6 5 4 3 2 1 0 Reset Value 0B2H FIE FCM6 FCM5 FCM4 FCM3 FCM2 FCM1 FCM0 00000000b Symbol Function FIE Flash Interrupt Enable. 0: INT1# is not reassigned. 1: INT1# is re-assigned to signal IAP operation completion. External INT1# interrupts are ignored. FCM[6:0] Flash operation command 000_1011b Sector-Erase 000_1101b Block-Erase 000_1100b Byte-Verify1 000_1110b Byte-Program 000_1111b Prog-SB1 000_0011b Prog-SB2 000_0101b Prog-SB3 000_1001b Prog-SC0 All other combinations are not implemented, and reserved for future use. 1. Byte-Verify has a single machine cycle latency and will not generate any INT1# interrupt regardless of FIE. ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 17 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications SuperFlash Data Register (SFDT) Location 7 6 5 0B5H 4 3 2 1 0 Reset Value SuperFlash Data Register 00000000b Symbol Function SFDT Mailbox register for interfacing with flash memory block. (Data register). SuperFlash Address Registers (SFAL) Location 7 6 0B3H 5 4 3 2 1 0 Reset Value SuperFlash Low Order Byte Address Register 00000000b Symbol Function SFAL Mailbox register for interfacing with flash memory block. (Low order address register). SuperFlash Address Registers (SFAH) Location 7 6 0B4H 5 4 3 2 1 0 Reset Value SuperFlash High Order Byte Address Register 00000000b Symbol Function SFAH Mailbox register for interfacing with flash memory block. (High order address register). Interrupt Enable (IE) Location 7 6 5 4 3 2 1 0 Reset Value A8H EA - ET2 ES ET1 EX1 ET0 EX0 00H Symbol Function EA Global Interrupt Enable. 0 = Disable 1 = Enable ET2 Timer 2 Interrupt Enable. ES Serial Interrupt Enable. ET1 Timer 1 Interrupt Enable. EX1 External 1 Interrupt Enable. ET0 Timer 0 Interrupt Enable. EX0 External 0 Interrupt Enable. Interrupt Enable A (IEA) Location 7 6 5 4 3 2 1 0 Reset Value E8H - - - - EBO - - - xxxx0xxxb Symbol Function EBO Brown-out Interrupt Enable. 1 = Enable the interrupt 0 = Disable the interrupt ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 18 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications Interrupt Priority (IP) Location 7 6 5 4 3 2 1 0 Reset Value B8H - - PT2 PS PT1 PX1 PT0 PX0 xx000000b Symbol Function PT2 Timer 2 interrupt priority bit. PS Serial Port interrupt priority bit. PT1 Timer 1 interrupt priority bit. PX1 External interrupt 1 priority bit. PT0 Timer 0 interrupt priority bit. PX0 External interrupt 0 priority bit. Interrupt Priority High (IPH) Location 7 6 5 4 3 2 1 0 Reset Value B7H - - PT2H PSH PT1H PX1H PT0H PX0H xx000000b Symbol Function PT2H Timer 2 interrupt priority bit high. PSH Serial Port interrupt priority bit high. PT1H Timer 1 interrupt priority bit high. PX1H External interrupt 1 priority bit high. PT0H Timer 0 interrupt priority bit high. PX0H External interrupt 0 priority bit high. Interrupt Priority A (IPA) Location 7 6 5 4 3 2 1 0 Reset Value F8H - - - - PBO - - - xxxx0xxxb Symbol Function PBO Brown-out interrupt priority bit. Interrupt Priority A High (IPAH) Location 7 6 5 4 3 2 1 0 Reset Value F7H - - - - PBOH - - - xxxx0xxxb Symbol Function PBOH Brown-out Interrupt priority bit high. ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 19 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications Auxiliary Register (AUXR) Location 7 6 5 4 3 2 1 0 Reset Value 8EH - - - - - - EXTRAM AO xxxxxx00b Symbol Function EXTRAM 0: Internal Expanded RAM access. For details, refer to “Data Memory” on page 12. 1: External data memory access. AO 0: Normal ALE 1: ALE is normally off. ALE is active only during a MOVX or MOVC instruction. This will reduce EMI. Auxiliary Register 1 (AUXR1) Location 7 6 5 4 3 2 1 0 Reset Value A2H - - - - GF2 0 - DPS xxxx00x0b Symbol Function GF2 General purpose user-defined flag. DPS DPTR registers select bit. 0: DPTR0 is selected. 1: DPTR1 is selected. Watchdog Timer Control Register (WDTC) Location 7 6 5 4 3 2 1 0 Reset Value 0C0H - - - WDOUT WDRE WDTS WDT SWDT xxx00x00b Symbol Function WDOUT Watchdog output enable. 0: Watchdog reset will not be exported on Reset pin. 1: Watchdog reset if enabled by WDRE, will assert Reset pin for 32 clocks. WDRE Watchdog timer reset enable. 0: Disable watchdog timer reset. 1: Enable watchdog timer reset. WDTS Watchdog timer reset flag. 0: External hardware reset clears the flag. Flag can also be cleared by writing a 1. Flag survives if chip reset happened because of watchdog timer overflow. 1: Hardware sets the flag on watchdog overflow. WDT Watchdog timer refresh. 0: Hardware resets the bit when refresh is done. 1: Software sets the bit to force a watchdog timer refresh. SWDT Start watchdog timer. 0: Stop WDT. 1: Start WDT. ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 20 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications Watchdog Timer Data/Reload Register (WDTD) Location 7 6 5 085H 4 3 2 1 0 Reset Value Watchdog Timer Data/Reload 00000000b Symbol Function WDTD Initial/Reload value in Watchdog Timer. New value won’t be effective until WDT is set. SPI Control Register (SPCR) Location 7 6 5 4 3 2 1 0 Reset Value D5H SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 00000100b Symbol Function SPIE If both SPIE and ES are set to one, SPI interrupts are enabled. SPE SPI enable bit. 0: Disables SPI. 1: Enables SPI and connects SS#, MOSI, MISO, and SCK to pins P1[4], P1[5], P1[6], P1[7]. DORD Data Transmission Order. 0: MSB first in data transmission. 1: LSB first in data transmission. MSTR Master/Slave select. 0: Selects Slave mode. 1: Selects Master mode. CPOL Clock Polarity 0: SCK is low when idle (Active High). 1: SCK is high when idle (Active Low). CPHA Clock Phase control bit. 0: Shift triggered on the leading edge of the clock. 1: Shift triggered on the trailing edge of the clock. SPR1, SPR0 SPI Clock Rate Select bits. These two bits control the SCK rate of the device configured as master. SPR1 and SPR0 have no effect on the slave. The relationship between SCK and the oscillator frequency, fOSC, is as follows: SPR1 SPR0 SCK = fOSC divided by 0 0 1 1 0 1 0 1 4 16 64 128 ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 21 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications SPI Status Register (SPSR) Location 7 6 5 4 3 2 1 0 Reset Value AAH SPIF WCOL - - - - - - 00xxxxxxb Symbol Function SPIF Upon completion of data transfer, this bit is set to 1. If SPIE =1 and ES =1, an interrupt is then generated. To clear, read SPSR and then access SPDR. WCOL Set if the SPI data register is written to during data transfer. To clear, read SPSR and then access SPDR. SPI Data Register (SPDR) Location 7 6 5 4 3 2 1 0 Reset Value 86H SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0 00H Power Control Register (PCON) Location 7 6 5 4 3 2 1 0 Reset Value 87H SMOD1 SMOD0 BOF POF GF1 GF0 PD IDL 00010000b Symbol Function SMOD1 Double Baud rate bit. If SMOD1 = 1, Timer 1 is used to generate the baud rate. SMOD0 FE/SM0 Selection bit. 0: SCON[7] = SM0 1: SCON[7] = FE, BOF Brown-out detection status bit, this bit will not be affected by any other reset. BOF should be cleared by software. Power-on reset will also clear the BOF bit. 0: No Brown-out. 1: Brown-out occurred POF Power-on reset status bit, this bit will not be affected by any other reset. POF should be cleared by software. 0: No Power-on reset. 1: Power-on reset occurred GF1 General-purpose flag bit. GF0 General-purpose flag bit. PD Power-down bit. 0: Power-down mode is not activated. 1: Activates Power-down mode. IDL Idle mode bit. 0: Idle mode is not activated. 1: Activates Idle mode. ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 22 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications Serial Port Control Register (SCON) Location 7 6 5 4 3 2 1 0 Reset Value 98H SM0/FE SM1 SM2 REN TB8 RB8 TI RI 00000000b Symbol Function FE Set SMOD0 = 1 to access FE bit. 0: No framing error 1: Framing Error. Set by receiver when an invalid stop bit is detected. This bit needs to be cleared by software. SM0 SMOD0 = 0 to access SM0 bit. Serial Port Mode Bit 0 SM1 Serial Port Mode Bit 1 SM0 0 SM1 0 Mode 0 Description Shift Register 0 1 1 0 1 2 8-bit UART 9-bit UART 1 1 3 9-bit UART Baud Rate1 fOSC/6 (6 clock mode) or fOSC/ 12 (12 clock mode) Variable fOSC/32 or fOSC/16 (6 clock mode) or fOSC/64 or fOSC/32 (12 clock mode) Variable 1. fOSC = oscillator frequency SM2 Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then RI will not be set unless the received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or broadcast Address. In Mode 1, if SM2 = 1 then RI will not be activated unless a valid stop bit was received, and the received byte is a Given or Broadcast Address. In Mode 0, SM2 should be 0. REN Enables serial reception. 0: to disable reception. 1: to enable reception. TB8 The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. RB8 In Modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 - 0, RB8 is the stop bit that was received. In Mode 0, RB8 is not used. TI Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission, Must be cleared by software. RI Receive interrupt flag. Set by hardware at the end of the8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by software. ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 23 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications 4.0 FLASH MEMORY PROGRAMMING The device internal flash memory can be programmed or erased using the following two methods: • • logic high to a logic low while RST input is being held continuously high. The device will stay in External Host Mode as long as RST = 1 and PSEN# = 0. External Host Mode In-Application Programming (IAP) Mode A Read-ID operation is necessary to “arm” the device in External Host Mode, and no other External Host Mode commands can be enabled until a Read-ID is performed. In External Host Mode, the internal flash memory blocks are accessed through the re-assigned I/O port pins (see Figure 4-1 for details) by an external host, such as a MCU programmer, a PCB tester or a PC-controlled development board. 4.1 External Host Programming Mode External Host Programming Mode allows the user to program the flash memory directly without using the CPU. External Host Mode is entered by forcing PSEN# from a TABLE 4-1: EXTERNAL HOST MODE COMMANDS FOR P3[7] P3[6] P2[7] P2[6] P0[7:0] P3[5:4] P2[5:0] P1[7:0] VIH VIL VIL VIL VIL DO AH AL VIH VIH VIL VIL VIL X X X ⇓ VIH VIH VIH VIL VIH X X X ⇓ VIH VIH VIL VIH VIH X AH AL VIL ⇓ VIH VIH VIH VIH VIL DI AH AL VIL VIH VIH VIH VIH VIL VIL DO AH AL RST PSEN# PROG#/ ALE EA# Read-ID VIH1 VIL VIH Chip-Erase VIH1 VIL ⇓ Block-Erase VIH1 VIL Sector-Erase VIH1 VIL Byte-Program VIH1 Byte-Verify (Read) VIH1 Operation SST89E564/SST89V564 Select-Block0 VIH1 VIL ⇓ VIH VIH VIl VIl VIH X 55H X Select-Block1 VIH1 VIL ⇓ VIH VIH VIl VIl VIH X A5H X Prog-SC0 VIH1 VIL ⇓ VIH VIH VIL VIL VIH X 5AH X Prog-SB1 VIH1 VIL ⇓ VIH VIH VIH VIH VIH X X X Prog-SB2 VIH1 VIL ⇓ VIH VIL VIL VIH VIH X X X Prog-SB3 VIH1 VIL ⇓ VIH VIL VIH VIL VIH X X X T4-1.4 384 Note: Symbol ⇓ signifies a negative pulse and the command is asserted during the low state of PROG#/ALE input. All other combinations of the above input pins are invalid and may result in unexpected behaviors. Note: VIL = Input Low Voltage; VIH = Input High Voltage; VIH1 = Input High Voltage (XTAL, RST); X = Don’t care; AL = Address low order byte; AH = Address high order byte; DI = Data Input; DO = Data Output ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 24 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications TABLE 4-2: EXTERNAL HOST MODE COMMANDS FOR SST89E554/SST89V554 Operation RST PSEN# PROG#/ ALE EA# P3[7] P3[6] P2[7] P2[6] P0[7:0] P3[5:4] P2[5:0] P1[7:0] Read-ID VIH1 VIL VIH VIH VIL VIL VIL VIL DO AH AL Chip-Erase VIH1 VIL ⇓ VIH VIH VIL VIL VIL X X X Block-Erase VIH1 VIL ⇓ VIH VIH VIH VIL VIH X A[15:13] X Sector-Erase VIH1 VIL ⇓ VIH VIH VIL VIH VIH X AH AL Byte-Program VIH1 VIL ⇓ VIH VIH VIH VIH VIL DI AH AL Byte-Verify (Read) VIH1 VIL VIH VIH VIH VIH VIL VIL DO AH AL Prog-SC0 VIH1 VIL ⇓ VIH VIH VIL VIL VIH X 5AH X Prog-SC1 VIH1 VIL ⇓ VIH VIH VIL VIL VIH X AAH X Prog-SB1 VIH1 VIL ⇓ VIH VIH VIH VIH VIH X X X Prog-SB2 VIH1 VIL ⇓ VIH VIL VIL VIH VIH X X X Prog-SB3 VIH1 VIL ⇓ VIH VIL VIH VIL VIH X X X T4-2.0 384 Note: Symbol ⇓ signifies a negative pulse and the command is asserted during the low state of PROG#/ALE input. All other combinations of the above input pins are invalid and may result in unexpected behaviors. Note: VIL = Input Low Voltage; VIH = Input High Voltage; VIH1 = Input High Voltage (XTAL, RST); X = Don’t care; AL = Address low order byte; AH = Address high order byte; DI = Data Input; DO = Data Output; A[15:13] = 0xxb for Block 0 and A[15:13] = 111b for Block 1 VSS VDD RST 0 XTAL1 Port 0 XTAL2 6 7 Input/ Output Data Bus 0 0 1 1 2 2 3 Ready/Busy# 3 A14 4 A15 5 Address Bus A15-A14 Flash Control Signals Port 2 Address Bus A13-A8 4 Port 3 5 6 7 6 Flash Control Signals 0 7 Port 1 6 Address Bus A7-A0 7 EA# ALE / PSEN# PROG# 384 ILL F01.1 FIGURE 4-1: I/O PIN ASSIGNMENTS FOR EXTERNAL HOST MODE ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 25 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications 4.1.1 Product Identification Following is a detailed description of the External Host Mode commands: The Read-ID command accesses the Signature Bytes that identify the device and the manufacturer as SST. External programmers primarily use these Signature Bytes in the selection of programming algorithms. The Read-ID command is selected by the command code of 0H on P3[7:6] and P2[7:6]. See Figure 4-2 for timing waveforms. TABLE The Select-Block0 command enables Block 0 to be programmed in External Host Mode. Once this command is executed, all subsequent External Host Commands will be directed at Block 0. See Figure 4-3 for timing waveforms. This command applies to SST89E564/SST89V564 only. The Select-Block1 command enables Block 1 (8 KByte Block) to be programmed. Once this command is executed, all subsequent External Host Commands that are directed to the address range below 2000H will be directed at Block 1. The Select-Block1 command only affects the lowest 8 KByte of the program address space. For addresses greater than or equal to 2000H, Block 0 is accessed by default. Upon entering External Host Mode, Block 1 is selected by default. See Figure 4-3 for timing waveforms. This command applies to SST89E564/ SST89V564 only. 4-3: SIGNATURE BYTES Address Data 30H BFH SST89E564 31H 93H SST89V564 31H 92H SST89E554 31H 9BH SST89V554 31H Manufacturer’s ID Device ID 9AH T4-3.4 384 The Chip-Erase, Block-Erase, and Sector-Erase commands are used for erasing all or part of the memory array. Erased data bytes in the memory array will be erased to FFH. Memory locations that are to be programmed must be in the erased state prior to programming. 4.1.2 Arming Command An arming command sequence must take place before any External Host Mode sequence command is recognized by the device. This prevents accidental triggering of External Host Mode Commands due to noise or programmer error. The arming command is as follows: The Chip-Erase command erases all bytes in both memory blocks, regardless of any previous Select-Block0 or SelectBlock1 commands. Chip-Erase ignores the Security Lock status and will erase the Security Lock, returning the device to its Unlocked state. The Chip-Erase command will also erase the SC0 bit. Upon completion of Chip-Erase command, Block 1 will be the selected block. See Figure 4-4 for timing waveforms. 1. PSEN# goes low while RST is high. This will get the machine in External Host Mode, re-configuring the pins, and turning on the on-chip oscillator. 2. A Read-ID command is issued, and after 1 ms the External Host Mode commands can be issued. After the above sequence, all other External Host Mode commands are enabled. Before the Read-ID command is received, all other External Host Mode commands received are ignored. The Block-Erase command erases all bytes in the selected memory blocks. This command will not be executed if the security lock is enabled. The selection of the memory block to be erased is determined by the prior execution SelectBlock0 or Select-Block1 command. See Figure 4-6 for the timing waveforms. 4.1.3 Detail Explanation of the External Host Mode Commands The External Host Mode commands are Read-ID, ChipErase, Block-Erase, Sector-Erase, Byte-Program, ByteVerify, Prog-SB1, Prog-SB2, Prog-SB3, Prog-SC0, ProgSC1, Select-Block0, Select-Block1. See Tables 4-1 and 4-2 for all signal logic assignments, Figure 4-1 for I/O pin assignments, and Table 4-7 for the timing parameters. The critical timing for all Erase and Program commands is generated by an on-chip flash memory controller. The high-tolow transition of the PROG# signal initiates the Erase or Program commands, which are synchronized internally. The Read commands are asynchronous reads, independent of the PROG# signal level. The Sector-Erase command erases all of the bytes in a sector. The sector size for the flash memory is 128 Bytes. This command will not be executed if the Security lock is enabled. See Figure 4-7 for timing waveforms. The Byte-Program command is used for programming new data into the memory array. Programming will not take place if any security locks are enabled. See Figure 4-8 for timing waveforms. ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 26 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications The Byte-Verify command allows the user to verify that the device correctly performed an Erase or Program command. This command will be disabled if any security locks are enabled. See Figure 4-11 for timing waveforms. 4.1.5.2 Data# Polling (P0[3]) During a Program operation, any attempts to read (ByteVerify), while the device is busy, will receive the complement of the data of the last byte loaded (logic low, i.e. “0” for an erase) on P0[3] with the rest of the bits “0”. During a Program operation, the Byte-Verify command is reading the data of the last byte loaded, not the data at the address specified. The Prog-SB1, Prog-SB2, Prog-SB3 commands program the security bits, the functions of these bits are described in the Security Lock section and also in Table 8-1. Once programmed, these bits can only be erased through a ChipErase command. See Figure 4-9 for timing waveforms. 4.1.6 Step-by-step instructions to perform External Host Mode commands Prog-SC0 command programs SC0 bit, which determines the state of SFCF[0] out of reset. Once programmed, SC0 can only be restored to an erased state via a Chip-Erase command. See Figure 4-10 for timing waveforms. To program data into the memory array, apply power supply voltage (VDD) to VDD and RST pins, and perform the following steps: Prog-SC1 command programs SC1 bit, which determines the state of SFCF[1] out of reset. Once programmed, SC1 can only be restored to an erased state via a Chip-Erase command. See Figure 4-10 for timing waveforms. ProgSC1 is for SST89E554/SST89V554 only. 1. Maintain RST high and set PSEN# from logic high to low, in sequence according to the appropriate timing diagram. 2. Raise EA# High (VIH). 3. Issue Read-ID command to enable the External Host Mode. 4.1.4 External Host Mode Clock Source In External Host Mode, an internal oscillator will provide clocking for the device. The on-chip oscillator will be turned on as the device enters External Host Mode; i.e. when PSEN# goes low while RST is high. During External Host Mode, the CPU core is held in reset. Upon exit from External Host Mode, the internal oscillator is turned off. 4. Verify that the memory blocks or sectors for programming is in the erased state, FFH. If they are not erased, then erase them using the appropriate Erase command. 5. Select the memory location using the address lines (P3[5:4], P2[5:0], P1[7:0]). 4.1.5 Flash Operation Status Detection Via External Host Handshake 6. Present the data in on P0[7:0]. 7. Pulse ALE/PROG#, observing minimum pulse width. The device provides two methods for an external host to detect the completion of a flash memory operation to optimize the Program or Erase time. The end of a flash memory operation cycle can be detected by: 8. Wait for low to high transition on READY/BUSY# (P3[3]). 1. monitoring the Ready/Busy# bit at P3[3]; 9. Repeat steps 5 - 8 until programming is finished. 2. monitoring the Data# Polling bit at P0[3]. 10. Verify the flash memory contents. 4.1.5.1 Ready/Busy# (P3[3]) The progress of the flash memory programming can be monitored by the Ready/Busy# output signal. P3[3] is driven low, some time after ALE/PROG# goes low during a flash memory operation to indicate the Busy# status of the Flash Control Unit (FCU). P3[3] is driven high when the flash programming operation is completed to indicate the Ready status. ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 27 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications 4.1.7 Flash Memory Programming Timing Diagrams with External Host Mode TSU RST TES PSEN# ALE/PROG# EA# P2[7:6] ,P3[7:6] TRD 0000b TRD 0000b P3[5:4] ,P2[5:0] ,P1 0030H 0031H P0 BFH Device ID 384 ILL F02.3 Device ID = 93H for SST89E564 92H for SST89V564 9BH for SST89E554 9AH for SST89V554 FIGURE 4-2: READ-ID Reads chip signature and identification registers at the addressed location. TSU RST TES PSEN# TADS ALE/PROG# TDH TPROG EA# P3[3] TPSB P3[5:4], P2[5:0] A5H/55H P3[7:6], P2[7:6] 1001b 384 ILL F56.1 FIGURE 4-3: SELECT-BLOCK1 / SELECT-BLOCK0 Enables the selection of either of the flash memory blocks prior to issuing a Byte-Verify, Block-Erase, SectorErase, or Byte-Program. These commands apply to SST89E564/SST89V564 only. ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 28 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications TSU RST TES PSEN# TADS ALE/PROG# TDH TPROG EA# TCE P3[3] P3[7:6], P2[7:6] 0001b 384 ILL F03.1 FIGURE 4-4: CHIP-ERASE Erases both flash memory blocks. Security lock is ignored and the security bits are erased too. TSU RST PSEN# TES TADS ALE/PROG# TDH TPROG EA# TBE P3[3] P3[7:6], P2[7:6] 1101b 384 ILL F04.2 FIGURE 4-5: BLOCK-ERASE FOR SST89E564/SST89V564 Erases one of the flash memory blocks, if the security lock is not activated on that flash memory block. ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 29 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications TSU RST TES PSEN# TADS ALE/PROG# TDH TPROG EA# TBE P3[3] P3[7:6], P2[7:6] 1101b P3[5:4], P2[5:0] AH 384 ILL F21.1 FIGURE 4-6: BLOCK-ERASE FOR SST89E554/SST89V554 Erases one of the flash memory blocks, if the security lock is not activated on that flash memory block. TSU RST PSEN# TES TADS ALE/PROG# TDH TPROG EA# P3[3] TSE P3[7:6], P2[7:6] 1011b P3[5:4], P2[5:0] AH P1 AL 384 ILL F05.1 FIGURE 4-7: SECTOR-ERASE Erases the addressed sector if the security lock is not activated on that flash memory block. ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 30 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications TSU RST TES PSEN# TADS ALE/PROG# TDH TPROG EA# P3[3] TPS P3[5:4], P2[5:0] AH P1 AL P0 DI P3[7:6], P2[7:6] 1110b 384 ILL F06.2 FIGURE 4-8: BYTE-PROGRAM Programs the addressed code byte if the byte location has been successfully erased and not yet programmed. Byte-Program operation is only allowed when the security lock is not activated on that flash memory block. TSU RST TES PSEN# TADS ALE/PROG# TPROG TDH EA# P3[3] TPS P3[7:6], P2[7:6] 1111b / 0011b / 0101b 384 ILL F49.2 FIGURE 4-9: PROG-SB1 / PROG-SB2 / PROG-SB3 Programs the Security bits SB1, SB2 and SB3 respectively. Only a Chip-Erase will erase a programmed security bit. ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 31 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications TSU RST TES PSEN# TADS ALE/PROG# TPROG TDH EA# P3[3] TPS P3[5:4], P2[5:0] 5AH / AAH P3[7:6], P2[7:6] 1001b 384 ILL F52.5 FIGURE 4-10: PROG-SC0 / PROG-SC1 Programs the start-up configuration bit SC0/SC1. Only a Chip-Erase will erase a programmed SC0/SC1 bit. Prog-SC1 applies to SST89E554/SST89V554 only. TSU RST TES PSEN# ALE/PROG# EA# TOA P3[7:6], P2[7:6] 1100b TAHA P0 DO TALA P1 AL P3[5:4], P2[5:0] AH 384 ILL F08.1 FIGURE 4-11: BYTE-VERIFY Reads the code byte from the addressed flash memory location if the security lock is not activated on that flash memory block. ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 32 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications 4.2 In-Application Programming Mode as a source to program another address. However, a block that is not “visible” may be programmed by code from the other block through mailbox registers. The device offers either 72 or 40 KByte of In-Application Programmable flash memory. During In-Application Programming, the CPU of the microcontroller enters IAP Mode. The two blocks of flash memory allow the CPU to execute user code from one block, while the other is being erased or reprogrammed concurrently. The CPU may also fetch code from an external memory while all internal flash is being reprogrammed. The mailbox registers (SFST, SFCM, SFAL, SFAH, SFDT and SFCF) located in the Special Function Register (SFR), control and monitor the device’s erase and program process. The device allows IAP code in one block of memory to program the other block of memory, but may not program any location in the same block. If an IAP operation originates physically from Block 0, the target of this operation is implicitly defined to be in Block 1. If the IAP operation originates physically from Block 1, then the target address is implicitly defined to be in Block 0. If the IAP operation originates from External program space, then, the target will depend on the address and the state of Bank Select. Table 4-6 outlines the commands and their associated mailbox register settings. 4.2.3 IAP Enable Bit The IAP Enable Bit, SFCF[6], enables In-Application Programming mode. Until this bit is set all flash programming IAP commands will be ignored. 4.2.1 In-Application Programming Mode Clock Source During IAP Mode, both the CPU core and the flash controller unit are driven off the external clock. However, an internal oscillator will provide timing references for Program and Erase operations. The internal oscillator is only turned on when required, and is turned off as soon as the flash operation is completed. 4.2.4 In-Application Programming Mode Commands All of the following commands can only be initiated in the IAP Mode. In all situations, writing the control byte to the SFCM register will initiate all of the operations. All commands will not be enabled if the security locks are enabled on the selected memory block. 4.2.2 Memory Bank Selection for In-Application Programming Mode The Program command is for programming new data into the memory array. The portion of the memory array to be programmed should be in the erased state, FFH. If the memory is not erased, it should first be erased with an appropriate Erase command. Warning: Do not attempt to write (program or erase) to a block that the code is currently fetching from. This will cause unpredictable program behavior and may corrupt program data. With the addressing range limited to 16 bit, only 64 KByte of program address space is “visible” at any one time. As shown in Table 4-4, Bank Selection (the configuration of EA# and SFCF[1:0]), allows Block 1 memory to be overlaid on the lowest 8 KByte of Block 0 memory, making Block 1 reachable. The same concept is employed to allow both Block 0 and Block 1 flash to be accessible to IAP operations. Code from a block that is not visible may not be used 4-4: IAP ADDRESS RESOLUTION TABLE FOR The Block-Erase command erases all bytes in one of the two memory blocks. The selection of the memory block to be erased is determined by the source of Block-Erase Command, as defined in Table 4-4. SST89E564/SST89V564 EA# SFCF[1:0] Address of IAP Inst. Target Address 1 00 >= 2000H (Block 0) >= 2000H (Block 0) Block Being Programmed 1 00 >= 2000H (Block 0) < 2000H (Block 1) Block 1 1 00 < 2000H (Block 1) Any (Block 0) Block 0 1 01, 10, 11 Any (Block 0) >= 2000H (Block 0) None1 1 01, 10, 11 Any (Block 0) < 2000H (Block 1) Block 1 0 00 From external >= 2000H (Block 0) Block 0 0 00 From external < 2000H (Block 1) Block 1 0 01, 10, 11 From external Any (Block 0) Block 0 None1 T4-4.5 384 1. No operation is performed because code from one block may not program the same originating block ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 33 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications The Sector-Erase command erases all of the bytes in a sector. The sector size for the flash memory Blocks is 128 Bytes. The selection of the sector to be erased is determined by the contents of SFAH and SFAL. Prog-SC1 command is used to program the SC1 bit. This command only changes the SC1 bit and has no effect on BSEL bit until after a reset cycle. SC1 bit previously in un-programmed state can be programmed by this command. The Prog-SC1 command should reside only in Block 1. The Byte-Program command programs data into a single byte. The address is determined by the contents of SFAH and SFAL. The data byte is in SFDT. There are no IAP counterparts for the External Host commands Select-Block0 and Select-Block1. The Byte-Verify command allows the user to verify that the device has correctly performed an Erase or Program command. 4.2.5 Polling A command that uses the polling method to detect flash operation completion should poll on the FLASH_BUSY bit (SFST[2]). When FLASH_BUSY de-asserts (logic 0), the device is ready for the next operation. Byte-Verify command returns the data byte in SFDT if the command is successful. The user is required to check that the previous flash operation has fully completed before issuing a Byte-Verify. Byte-Verify command execution time is short enough that there is no need to poll for command completion and no interrupt is generated. MOVC instruction may also be used for verification of the Programming and Erase operation of the flash memory. MOVC instruction will fail if it is directed at a flash block that is still busy. Prog-SB3, Prog-SB2, Prog-SB1 commands are used to program the Security bits (see Table 8-1). Completion of any of these commands, the security options will be updated immediately. 4.2.6 Interrupt Termination If interrupt termination is selected, (SFCM[7] is set), then an interrupt (INT1) will be generated to indicate flash operation completion. Under this condition, the INT1 becomes an internal interrupt source. The INT1# pin can now be used as a general purpose port pin and it cannot be the source of External Interrupt 1 during In-Application Programming. Security bits previously in un-programmed state can be programmed by these commands. Prog-SB3, Prog-SB2 and Prog-SB1 commands should only reside in Block 1. Prog-SC0 command is used to program the SC0 bit. This command only changes the SC0 bit and has no effect on BSEL bit until after a reset cycle. In order to use an interrupt to signal flash operation termination. EX1 and EA bits of IE register must be set. The IT1 bit of TCON register must also be set for edge trigger detection. SC0 bit previously in un-programmed state can be programmed by this command. The Prog-SC0 command should reside only in Block 1. . ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 34 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications TABLE 4-5: IN-APPLICATION PROGRAMMING MODE COMMANDS1 FOR SST89E564/SST89V564 SFCM [6:0]2 Operation SFDT [7:0] SFAH [7:0] 0DH 55H X4 X 0BH X AH5 AL6 0EH DI7 AH AL 0CH DO8 AH AL Prog-SB19 0FH AAH X X Prog-SB29 03H AAH X X Prog-SB39 05H AAH X X Prog-SC09 09H AAH 5AH X Block-Erase3 Sector-Erase3 Byte-Program3 Byte-Verify (Read)3 SFAL [7:0] T4-5.8 384 1. SFCF[6]=1 enables IAP commands; SFCF[6]=0 disables IAP commands. 2. Interrupt/Polling enable for flash operation completion SFCM[7] =1: Interrupt enable for flash operation completion 0: polling enable for flash operation completion 3. Refer to Table 4-4 for address resolution 4. X can be VIL or VIH, but no other value. 5. AH = Address high order byte 6. AL = Address low order byte 7. DI = Data Input 8. DO = Data Output All other values are in hex 9. Instruction must be located in Block 1 . TABLE 4-6: IN-APPLICATION PROGRAMMING MODE COMMANDS1 FOR SST89E554/SST89V554 Operation Block-Erase3 SFCM [6:0]2 SFDT [7:0] SFAH [7:0] SFAL [7:0] 0DH 55H AH4 X5 AL7 Sector-Erase3 0BH X AH6 Byte-Program3 0EH DI8 AH AL 0CH DO9 AH AL Prog-SB110 0FH AAH X X Prog-SB210 03H AAH X X Prog-SB310 05H AAH X X Prog-SC010 09H AAH 5AH X Prog-SC110 09H AAH AAH X Byte-Verify (Read)3 T4-6.0 384 1. SFCF[6]=1 enables IAP commands; SFCF[6]=0 disables IAP commands. 2. Interrupt/Polling enable for flash operation completion SFCM[7] =1: Interrupt enable for flash operation completion 0: polling enable for flash operation completion 3. Refer to Table 4-4 for address resolution 4. SFAH[7]=0: Selects Block 0; SFAH[7:5] = 111b selects Block 1 5. X can be VIL or VIH, but no other value. 6. AH = Address high order byte 7. AL = Address low order byte 8. DI = Data Input 9. DO = Data Output All other values are in hex 10. Instruction must be located in Block 1 ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 35 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications TABLE 4-7: FLASH MEMORY PROGRAMMING/VERIFICATION PARAMETERS Parameter1,2 Symbol Min Reset Setup Time TSU 3 µs Read-ID Command Width TRD 1 µs PSEN# Setup Time TES 1.125 µs Address, Command, Data Setup Time TADS 0 Chip-Erase Time TCE 125 Block-Erase Time TBE 100 ms Sector-Erase Time TSE 30 ms Program Setup Time Address, Command, Data Hold Max Units ns ms TPROG 1.2 µs TDH 0 ns Byte-Program Time3 TPB 50 µs Select-Block Program Time TPSB 500 ns Security bit Program Time TPS 80 µs Verify Command Delay Time TOA 50 ns Verify High Order Address Delay Time TAHA 50 ns Verify Low Order Address Delay Time TALA 50 ns T4-7.5 384 1. Program and Erase times will scale inversely proportional to programming clock frequency. 2. All timing measurements are from the 50% of the input to 50% of the output. 3. Each byte must be erased before programming. 5.0 TIMERS/COUNTERS that uses the SBUF register as a destination register. Reception is initiated in mode 0 when the Receive Interrupt (RI) flag bit of the Serial Port Control (SCON) SFR is cleared and the Reception Enable/ Disable (REN) bit of the SCON register is set. Reception is initiated in the other modes by the incoming start bit if the REN bit of the SCON register is set. The device has three 16-bit registers that can be used as either timers or event counters. The three Timers/Counters are denoted Timer 0 (T0), Timer 1 (T1), and Timer 2 (T2). Each is designated a pair of 8-bit registers in the SFRs. The pair consists of a most significant (high) byte and least significant (low) byte. The respective registers are TL0, TH0, TL1, TH1, TL2, and TH2. 6.1.1 Framing Error Detection Framing Error Detection allows the serial port to automatically check for valid stop bits in Modes 1, 2 or 3. If a stop bit is missing the Framing Error bit (FE) will be set. The software can then check this bit after a reception to detect communication errors. The FE bit must be cleared by software. 6.0 SERIAL I/O 6.1 Enhanced Universal Aysnchronous Receiver/Transmitter (UART) The device Serial I/O port is a full duplex port that allows data to be transmitted and received simultaneously in hardware by the transmit and receive registers, respectively, while the software is performing other tasks. The transmit and receive registers are both located in the Serial Data Buffer (SBUF) special function register. Writing to the SBUF register loads the transmit register, and reading from the SBUF register obtains the contents of the receive register. The FE bit is located in SCON and shares the same bit address as SM0. The SMOD0 bit located in the PCON register determines which of these two bits is accessed. When SMOD0 = 0, SCON[7] will act as SM0. When SMOD0 = 1, SCON[7] will act as FE. 6.1.2 Automatic Address Recognition Automatic Address Recognition (AAR) reduces the CPU time required to service the serial port in a multiprocessor environment. When using AAR, the serial port hardware will only generate an interrupt when it receives its own address, thus eliminating the software overhead required to compare addresses. The UART has four modes of operation which are selected by the Serial Port Mode Specifier (SM0 and SM1) bits of the Serial Port Control (SCON) special function register. In all four modes, transmission is initiated by any instruction ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 36 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications AAR is only available when using the serial port in either mode 2 or 3. Setting the SM2 bit in SCON enables AAR. Each slave must have its SM2 bit set when waiting for an address (9th bit = 1). The Receive Interrupt (RI) flag will only be set when the received byte matches either the Given or Broadcast Address. The slave then clears its SM2 bit to enable reception of data bytes (9th bit = 0) from the master. Slave 2 will not respond to an address that has bit 0 set to 0 while Slave 1 will. Both slaves will respond to an address of 1111 0x01b so this is the Broadcast Address. The Broadcast Addresses is formed by the logical OR of SADDR and SADEN with 0s treated as don’t-care bits. The master can selectively communicate with groups of slaves by sending the Given Address. Addressing all slaves is also possible by sending the Broadcast address. The SADDR and SADEN special function registers define these addresses for each slave. The device SPI allows for high-speed full-duplex synchronous data transfer between the device and other compatible SPI devices. 6.2 Serial Peripheral Interface (SPI) Figure 6-1 shows the correspondence between master and slave SPI devices. The SCK pin is the clock output and input for the master and slave modes, respectively. The SPI clock generator will start following a write to the master devices SPI data register. The written data is then shifted out of the MOSI pin on the master device into the MOSI pin of the slave device. Following a complete transmission of one byte of data, the SPI clock generator is stopped and the SPIF flag is set. An SPI interrupt request will be generated if the SPI interrupt enable bit (SPIE) and the serial port interrupt enable bit (ES) are both set. SADDR specifies a slaves individual address and SADEN is a mask byte that defines don’t-care bits to form the Given address when combined with SADDR. The following is an example: UART Slave 1 SADDR = 1111 0001 SADEN = 1111 1010 GIVEN = 1111 0x0x An external master drives the Slave Select input pin, SS#/ P1[4], low to select the SPI module as a slave. If SS#/P1[4] has not been driven low, then the slave SPI unit is not active and the MOSI/P1[5] port can also be used as an input port pin. UART Slave 2 SADDR = 1111 0011 SADEN = 1111 1001 GIVEN = 1111 0xx1 CPHA and CPOL control the phase and polarity of the SPI clock. Figures 6-2 and 6-3 show the four possible combinations of these two bits. In this example Slave 1 can be distinguished from Slave 2 by using bits 0 and 1. Slave 1 will not respond to an address that has bit 1 set to 1 while Slave 2 will. Similarly, MSB MASTER LSB MISO MISO 8-bit Shift Register MSB SLAVE LSB 8-bit Shift Register MOSI MOSI SPI Clock Generator SCK SS# SCK SS# VIH 384 ILL F53.1 FIGURE 6-1: SPI MASTER-SLAVE INTERCONNECTION ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 37 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications SCK Cycle # (for reference) 1 2 3 4 5 6 7 8 SCK (CPOL=0) SCK (CPOL=1) MOSI (from Master) MSB MISO (from Slave) MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB * SS# (to Slave) 384 ILL F54.1 * Not defined, but normally MSB of next received byte FIGURE 6-2: SPI TRANSFER FORMAT SCK Cycle # (for reference) 1 WITH 2 CPHA = 0 3 4 5 6 7 8 SCK (CPOL=0) SCK (CPOL=1) MOSI (from Master) MISO (from Slave) * MSB 6 5 4 3 2 1 MSB 6 5 4 3 2 1 LSB LSB SS# (to Slave) 384 ILL F55.1 * Not defined but normally LSB of previously transmitted character FIGURE 6-3: SPI TRANSFER FORMAT WITH CPHA = 1 ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 38 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications 7.0 WATCHDOG TIMER The device offers a programmable Watchdog Timer (WDT) for fail safe protection against software deadlock and automatic recovery. The WDTS flag bit is set by WDT overflow and is not changed by WDT reset. User software can clear WDTS by writing “1” to it. To protect the system against software deadlock, the user software must refresh the WDT within a user-defined time period. If the software fails to do this periodical refresh, an internal hardware reset will be initiated if enabled (WDRE= 1). The software can be designed such that the WDT times out if the program does not work properly. Figure 7-1 provides a block diagram of the WDT. Two SFRs (WDTC and WDTD) control watchdog timer operation. During idle mode, WDT operation is temporarily suspended, and resumes upon an interrupt exit from idle. The time-out period of the WDT is calculated as follows: Period = (255 - WDT) * 344064 * 1/fOSC The WDT in the device uses the system clock (XTAL1) as its time base. So strictly speaking, it is a watchdog counter rather than a watchdog timer. The WDT register will increment every 344064 crystal clocks. The upper 8-bits of the time base register (WDTD) are used as the reload register of the WDT. CLK (XTAL1) where WDT is the value loaded into the WDT register and fOSC is the oscillator frequency. 344064 clks Counter WDT Reset WDT Upper Byte Internal Reset Ext. RST WDTC WDTD 384 ILL F10.2 FIGURE 7-1: BLOCK DIAGRAM OF PROGRAMMABLE WATCHDOG TIMER ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 39 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications 8.0 SECURITY LOCK mand mailbox register, SFCM, executed from a Locked (Hard Locked or SoftLocked) block, can be operated on a SoftLocked block: Block-Erase, Sector-Erase, Byte-Program and Byte-Verify. The Security Lock protects against software piracy and prevents the contents of the flash from being read by unauthorized parties. It also protects against code corruption resulting from accidental erasing and programming to the internal flash memory. There are two different types of security locks in the device security lock system: Hard Lock and SoftLock. In External Host Mode, SoftLock behaves the same as a Hard Lock. 8.3 Security Lock Status The three bits that indicate the device security lock status are located in SFST[7:5]. As shown in Figure 81 and Table 8-1, the three security lock bits control the lock status of the primary and secondary blocks of memory. There are four distinct levels of security lock status. In the first level, none of the security lock bits are programmed and both blocks are unlocked. In the second level, although both blocks are now locked and cannot be programmed, they are available for read operation via Byte-Verify. In the third level, three different options are available: Block 1 Hard Lock / Block 0 SoftLock, SoftLock on both blocks, and Hard Lock on both blocks. Locking both blocks is the same as Level 2 except read operation isn’t available. The fourth level of security is the most secure level. It doesn’t allow read/program of internal memory or boot from external memory. Please note that for unused combinations of the security lock bits, the chip will default to Level 4 status. For details on how to program the security lock bits refer to the External Host Mode and In-Application Programming Section. 8.1 Hard Lock When Hard Lock is activated, MOVC or IAP instructions executed from an unlocked or SoftLocked program address space, are disabled from reading code bytes in Hard Locked memory blocks (See Table 8-2). Hard Lock can either lock both flash memory blocks or just lock the 8 KByte flash memory block (Block 1). All External Host and IAP commands except for Chip-Erase are ignored for memory blocks that are Hard Locked. 8.2 SoftLock SoftLock allows flash contents to be altered under a secure environment. This lock option allows the user to update program code in the SoftLocked memory block through InApplication Programming Mode under a predetermined secure environment. For example, if Block 1 (8K) memory block is locked (Hard Locked or SoftLocked), and Block 0 (64K for SST89E564/SST89V564) memory block is SoftLocked, code residing in Block 1 can program Block 0. The following IAP mode commands issued through the com- UUU/NN Level 1 PUU/SS Level 2 UPU/SS UUP/LS Level 3 UPP/LL PPU/LS PUP/LL UPP/LL Level 4 PPP/LL 384 ILL F38.2 FIGURE 8-1: SECURITY LOCK LEVELS Notes: P = Programmed (Cell logic state = 0), U = Unprogrammed (Cell logic state = 1), N = Not Locked, L = Hard Locked, S = SoftLocked. ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 40 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications TABLE 8-1: SECURITY LOCK OPTIONS Security Lock Bits1,2 Security Status of: Level SFST[7:5] SB1 SB21 1 000 U U U Unlock Unlock No Security Features are Enabled. 2 100 P U U SoftLock SoftLock MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA# is sampled and latched on Reset, and further programming of the flash is disabled. 3 011 101 U P P U P P Hard Lock Hard Lock Level 2 plus Verify disabled, both blocks locked. 010 U P U SoftLock SoftLock Level 2 plus Verify disabled. Code in Block 1 may program Block 0 and vice versa. 110 001 P U P U U P Hard Lock SoftLock Level 2 plus Verify disabled. Code in Block 1 may program Block 0. 111 P P P Hard Lock Hard Lock Same as Level 3 Hardlock/Hardlock, but MCU will start code execution from the internal memory regardless of EA#. 4 SB31 Block 1 Block 0 Security Type T8-1.7 384 1. P = Programmed (Cell logic state = 0), U = Unprogrammed (Cell logic state = 1). 2. SFST[7:5] = Security Lock Decoding Bits (SECD) ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 41 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications TABLE Level 8-2: SECURITY LOCK ACCESS TABLE SFST[7:5] Source Target Address Address1 Block 0/1 4 111b (Hard Lock on both blocks) External Block 0/1 011b/101b (Hard Lock on both blocks) External Block 0/1 N N Y Y External N/A N N N Block 0/1 N N N N External N/A N N N Block 0/1 N N Y Y External N N N Y Block 0/1 N N N N External N/A N Y Y Block 0 N N Y Y Block 1 N N N N External N/A N N Y Block 0 N Y Y Y Block 1 N N Y Y External N/A N N Y Block 0/1 N N N N External N/A N Y Y Block 0 N N Y Y Block 1 N Y Y Y External N/A N N Y Block 0 N Y Y Y Block 1 N N Y Y External N/A N N Y Block 0/1 N N N N External N/A N Y Y Block 0 Y N Y Y Block 1 Y Y Y Y External N/A N N Y Block 0 Y Y Y Y Block 1 Y N Y Y External N/A N N Y Block 0/1 Y N N N External N/A N Y Y Block 0 Y N Y Y Block 1 Y Y Y Y External N/A N N Y Block 0 Y Y Y Y Block 1 Y N Y Y External N/A N N Y Y Block 0 001b/110b (Block 0 = SoftLock, Block 1 = Hard Lock) Block 1 3 External Block 0 010b (SoftLock on both blocks) Block 1 External Block 0 2 100b (SoftLock on both blocks) Block 1 External Block 0 1 000b (Unlock) Block 1 External External Host IAP MOVC MOVC Byte-Verify Byte-Verify Allowed Allowed Allowed2 Allowed on 564 on 554 Block 0/1 Y Y N External N/A N Y Y T8-2.1 384 1. Location of MOVC instruction 2. External Host Byte-Verify access does not depend on a source address. ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 42 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications 9.0 RESET A system reset initializes the MCU and begins program execution at program memory location 0000H. The reset input for the device is the RST pin. In order to reset the device, a logic level high must be applied to the RST pin for at least two machine cycles (24 clocks), after the oscillator becomes stable. ALE, PSEN# are weakly pulled high during reset. During reset, ALE and PSEN# output a high level in order to perform a proper reset. This level must not be affected by external element. A system reset will not affect the 1 KByte of on-chip RAM while the device is running, however, the contents of the on-chip RAM during power up are indeterminate. Following reset, all Special Function Registers (SFR) return to their reset values outlined in Tables 3-5 to 3-9. VDD + 10µF VDD RST 8.2K SST89E5x4/V5x4 C2 XTAL2 XTAL1 C1 384 ILL F31.2 9.1 Power-On Reset FIGURE At initial power up, the port pins will be in a random state until the oscillator has started and the internal reset algorithm has weakly pulled all pins high. Powering up the device without a valid reset could cause the MCU to start executing instructions from an indeterminate location. Such undefined states may inadvertently corrupt the code in the flash. 9-1: POWER-ON RESET CIRCUIT 9.2 Software Reset The software reset is executed by changing SFCF[1] (SWR) from “0” to “1”. A software reset will reset the program counter to address 0000H. All SFR registers will be set to their reset values, except SFCF[1] (SWR), WDTC[2] (WDTS), and RAM data will not be altered. When power is applied to the device, the RST pin must be held high long enough for the oscillator to start up (usually several milliseconds for a low frequency crystal), in addition to two machine cycles for a valid Power-On Reset. An example of a method to extend the RST signal is to implement a RC circuit by connecting the RST pin to VDD through a 10 µF capacitor and to VSS through an 8.2KΩ resistor as shown in Figure 9-1. Note that if an RC circuit is being used, provisions should be made to ensure the VDD rise time does not exceed 1 millisecond and the oscillator start-up time does not exceed 10 milliseconds. 9.3 Brown-out Detection Reset The device includes a Brown-out detection circuit to protect the system from severe VDD fluctuations. For Brown-out voltage parameters, please refer to Tables 10-3 and 10-4. Brown-out interrupt can be enabled by setting the EBO bit in IEA register (address E8H, bit 3). If EBO bit is set and a Brown-out condition occurs, a Brown-out interrupt will be generated to execute the program at location 004BH. It is required that the EBO bit be cleared by software after the Brown-out interrupt is serviced. Clearing EBO bit when the Brown-out condition is active will properly reset the device. For a low frequency oscillator with slow start-up time the reset signal must be extended in order to account for the slow start-up time. This method maintains the necessary relationship between VDD and RST to avoid programming at an indeterminate location, which may cause corruption in the code of the flash. For more information on system level design techniques, please review Design Considerations for the SST FlashFlex51 Family Microcontroller Application Note. If Brown-out interrupt is not enabled, a Brown-out condition will reset the program to resume execution at location 0000H. 9.4 Interrupt Priority and Polling Sequence The device supports eight interrupt sources under a four level priority scheme. Table 9-1 summarizes the polling sequence of the supported interrupts. Note that the SPI serial interface and the UART share the same interrupt vector. ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 43 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications TABLE 9-1: INTERRUPT POLLING SEQUENCE Interrupt Flag Vector Address Interrupt Enable Interrupt Priority Arbitration Ranking Wake-Up Power Down Ext. Int0 IE0 0003H EX0 PX0/H 1(highest) yes Brown-out BOF 004BH EBO PBO/H 2 no T0 TF0 000BH ET0 PT0/H 3 no Description Ext. Int1 IE1 0013H EX1 PX1/H 4 yes T1 TF1 001BH ET1 PT1/H 5 no UART/SPI TI/RI/SPIF 0023H ES PS/H 6 no T2 TF2, EXF2 002BH ET2 PT2/H 7 no T9-1.2 384 9.5 Power-Saving Modes The device exits Power Down mode through either an enabled external level sensitive interrupt or a hardware reset. The start of the interrupt clears the PD bit and exits Power Down. Holding the external interrupt pin low restarts the oscillator, the signal must hold low at least 1024 clock cycles before bringing back high to complete the exit. After exit the interrupt service routine program execution resumes beginning at the instruction immediately following the instruction which invoked Power Down mode. A hardware reset starts the device similar to power-on reset. The device provides three power saving modes of operation for applications where power consumption is critical. The three power saving modes are: Idle, Power Down and Standby (Stop Clock). 9.5.1 Idle Mode Idle mode is entered setting the IDL bit in the PCON register. In Idle mode, the program counter (PC) is stopped. The system clock continues to run and all interrupts and peripherals remain active. The on-chip RAM and the special function registers hold their data during this mode. To exit properly out of Power Down, the reset or external interrupt should not be executed before the VDD line is restored to its normal operating voltage. Be sure to hold VDD voltage long enough at its normal operating level for the oscillator to restart and stabilize (normally less than 10 ms). The device exits Idle mode through either a system interrupt or a hardware reset. Exiting Idle mode via system interrupt, the start of the interrupt clears the IDL bit and exits Idle mode. After exit the Interrupt Service Routine, the interrupted program resumes execution beginning at the instruction immediately following the instruction which invoked the Idle mode. A hardware reset starts the device similar to a power-on reset. 9.5.3 Standby Mode (Stop Clock) Standby mode is similar to Power Down mode, except that Power Down mode is initiated by a software command and Standby mode is initiated by external hardware gating off the external clock to the device.The on-chip SRAM and SFR data are maintained in Standby mode. The device resumes operation at the next instruction when the clock is reapplied to the part. 9.5.2 Power Down Mode The Power Down mode is entered by setting the PD bit in the PCON register. In the Power Down mode, the clock is stopped and external interrupts are active for level sensitive interrupts only. To retain the on-chip RAM and all of the special function registers’ values, the minimum VDD level is 2.0V. Table 9-2 outlines the different power-saving modes, including entry and exit procedures and MCU functionality. ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 44 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications TABLE 9-2: POWER SAVING MODES Mode Initiated by State of MCU Exited by Idle Mode Software (Set IDL bit in PCON) CLK is running. Interrupts, serial port and timers/counters are active. Program Counter is stopped. ALE and PSEN# signals at a HIGH level during Idle. All registers remain unchanged. Enabled interrupt or hardware reset. Start of interrupt clears IDL bit and exits Idle mode, after the ISR RETI instruction, program resumes execution beginning at the instruction following the one that invoked Idle mode. A user could consider placing two or three NOP instructions after the instruction that invokes idle mode to eliminate any problems. A hardware reset restarts the device similar to a power-on reset. Power Down Mode Software (Set PD bit in PCON) CLK is stopped. On-chip SRAM and SFR data is maintained. ALE and PSEN# signals at a LOW level during Power Down. External Interrupts are only active for level sensitive interrupts, if enabled. Enabled external level sensitive interrupt or hardware reset. Start of interrupt clears PD bit and exits Power Down mode, after the ISR RETI instruction program resumes execution beginning at the instruction following the one that invoked Power Down mode. A user could consider placing two or three NOP instructions after the instruction that invokes Power Down mode to eliminate any problems. A hardware reset restarts the device similar to a power-on reset. CLK is frozen. On-chip SRAM and SFR data is maintained. ALE and PSEN# are maintained at the levels prior to the clock being frozen. Gate ON external clock. Program execution resumes at the instruction following the one during which the clock was gated off. Standby (Stop Clock) Mode External hardware gates OFF the external clock input to the MCU. This gating should be synchronized with an input clock transition (low-to-high or high-to-low). T9-2.6 384 ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 45 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications 9.6 Clock Input Options 9.7 Recommended Capacitor Values for Crystal Oscillator Shown in Figure 9-2 are the input and output of an internal inverting amplifier (XTAL1, XTAL2), which can be configured for use as an on-chip oscillator. Crystal manufacturer, supply voltage, and other factors may cause circuit performance to differ from one application to another. C1 and C2 should be adjusted appropriately for each design. The table below, shows the typical values for C1 and C2 at a given frequency. If following the satisfactory selection of all external components, the circuit is still over driven, a series resistor, Rs, may be added. When driving the device from an external clock source, XTAL2 should be left disconnected and XTAL1 should be driven. At start-up, the external oscillator may encounter a higher capacitive load at XTAL1 due to interaction between the amplifier and its feedback capacitance. However, the capacitance will not exceed 15 pF once the external signal meets the VIL and VIH specifications. RECOMMENDED VALUES FOR CRYSTAL OSCILLATOR Frequency C1 and C2 RS (Optional) < 8MHz 90-110pF 100Ω 8-12MHz 18-22pF 200Ω >12MHz 18-22pF 200Ω More specific information about on-chip oscillator design can be found in FlashFlex 51 Oscillator Circuit Design Considerations Application Note. RS XTAL2 C2 NC EXTERNAL OSCILLATOR SIGNAL C1 XTAL1 XTAL1 Vss Vss External Clock Drive Using the On-Chip Oscillator FIGURE XTAL2 384 ILL F12.0 9-2: OSCILLATOR CHARACTERISTICS ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 46 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications 10.0 ELECTRICAL SPECIFICATION Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Ambient Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to + 150°C Voltage on EA# Pin to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +14.0V Transient Voltage (<20ns) on Any Other Pin to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +6.5V Maximum IOL per I/O Pins P1.5, P1.6, P1.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Maximum IOL per I/O for All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15mA Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5W Through Hole Lead Soldering Temperature (10 Seconds). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA 1. Outputs shorted for no more than one second. No more than one output shorted at a time. (Based on package heat transfer limitations, not device power consumption. Note: This specification contains preliminary information on new products in production. The specifications are subject to change without notice. 10.1 Operation Range TABLE 10-1: OPERATING RANGE Symbol Description Min. Max Unit Ta Ambient Temperature Under Bias Standard 0 +70 Industrial -40 +85 °C °C VDD Supply Voltage 2.7 5.5 V fOSC Oscillator Frequency For In-Application Programming 0 40 MHz 0.25 40 MHz T10-1.1 384 10.2 Reliability Characteristics TABLE 10-2: RELIABILITY CHARACTERISTICS Symbol NEND 1 Parameter Minimum Specification Units Endurance 10,000 Cycles JEDEC Standard A117 100 Years JEDEC Standard A103 100 + IDD mA TDR1 Data Retention ILTH1 Latch Up Test Method JEDEC Standard 78 T10-2.0 384 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 47 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications 10.3 DC Electrical Characteristics TABLE 10-3: DC ELECTRICAL CHARACTERISTICS Tamb = 0°C TO +70°C OR -40°C TO +85°C, 40MHZ DEVICES; 4.5-5.5V; VSS = 0V Symbol Parameter Test Conditions Min Max Units VIL Input Low Voltage 4.5 < VDD < 5.5 -0.5 0.2VDD - 0.1 V VIH Input High Voltage 4.5 < VDD < 5.5 0.2VDD + 0.9 VDD + 0.5 V VIH1 Input High Voltage (XTAL1, RST) 4.5 < VDD < 5.5 0.7VDD VDD + 0.5 V VOL Output Low Voltage (Ports 1.5, 1.6, 1.7) 1.0 V VOL Output Low Voltage (Ports 1, 2, 3)1 VDD = 4.5V IOL = 16mA VOL1 VOH VOH1 VDD = 4.5V Output Low Voltage (Port 0, ALE, PSEN#)1,3 Brown-out Detection Voltage IIL Logical 0 Input Current (Ports 1, 2, 3) ITL Logical 1-to-0 Transition Current (Ports 1, 2, 3)5 ILI Input Leakage Current (Port 0) RRST RST Pulldown Resistor CIO Pin Capacitance6 IDD Power Supply Current7 V 0.45 V IOL = 3.5mA2 1.0 V IOL = 200µA2 0.3 V IOL = 3.2mA2 0.45 V VDD = 4.5V Mode)4 VBOD 0.3 IOL = 1.6mA2 VDD = 4.5V Output High Voltage (Ports 1, 2, 3, ALE, PSEN#)4 Output High Voltage (Port 0 in External Bus IOL = 100µA2 IOH = -10µA VDD - 0.3 V IOH = -30µA VDD - 0.7 V IOH = -60µA VDD - 1.5 V IOH = -200µA VDD - 0.3 V IOH = -3.2mA VDD - 0.7 VDD = 4.5V 3.85 VIN = 0.4V -1 VIN = 2V 0.45 < VIN < VDD-0.3 V 4.15 V -75 µA -650 µA ±10 µA 225 kΩ 15 pF @ 20 MHz 70 mA @ 40 MHz 88 mA @ 20 MHz 25 mA @ 40 MHz 45 mA 9.5 mA 40 @ 1 MHz, 25°C In-Application Mode Active Mode Idle Mode @ 20 MHz @ 40 MHz Standby (Stop Clock) Mode Power Down Mode 20 mA Tamb = 0°C to +70°C 100 µA Tamb = -40°C to +85°C 125 µA Tamb = 0°C to +70°C 40 µA Tamb = -40°C to +85°C 50 Minimum VDD = 2V µA T10-3.4 384 ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 48 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications TABLE 10-4: DC ELECTRICAL CHARACTERISTICS Tamb = 0°C TO +70°C OR -40°C TO +85°C, 25MHZ DEVICES; 2.7-3.6V; VSS = 0V Symbol Parameter Test Conditions Min Max Units VIL Input Low Voltage 2.7 < VDD < 3.3 -0.5 0.7 V VIH Input High Voltage 2.7 < VDD < 3.3 0.2VDD + 0.9 VDD + 0.5 V VIH1 Input High Voltage (XTAL1, RST) 2.7 < VDD < 3.3 0.7VDD VDD + 0.5 V VOL Output Low Voltage (Ports 1.5, 1.6, 1.7) 1.0 V IOL = 100µA2 0.3 V 1.6mA2 0.45 V IOL = 3.5mA2 1.0 V IOL = 200µA2 0.3 V 3.2mA2 0.45 V VDD = 2.7V IOL = 16mA VOL Output Low Voltage (Ports 1, 2, 3)1 VDD = 2.7V IOL = VOL1 Output Low Voltage (Port 0, ALE, PSEN#)1,3 VDD = 2.7V IOL = VOH VOH1 Output High Voltage (Ports 1, 2, 3, ALE, PSEN#)4 Output High Voltage (Port 0 in External Bus Mode)4 VBOD Brown-out Detection Voltage IIL Logical 0 Input Current (Ports 1, 2, 3) ITL Logical 1-to-0 Transition Current (Ports 1, 2, 3)5 ILI Input Leakage Current (Port 0) RRST RST Pulldown Resistor CIO Pin Capacitance6 IDD VDD = 2.7V Power Supply IOH = -10µA VDD - 0.3 V IOH = -30µA VDD - 0.7 V IOH = -60µA VDD - 1.5 V IOH = -200µA VDD - 0.3 V IOH = -3.2mA VDD - 0.7 V VDD = 2.7V VIN = 0.4V 2.25 2.55 V -1 -75 µA VIN = 2V -650 µA 0.45 < VIN < VDD-0.3 ±10 µA 225 kΩ 15 pF 70 mA @ 1 MHz, 25°C Current7 In-Application Mode Active Mode 22 mA Idle Mode 6.5 mA Standby (Stop Clock) Mode Power Down Mode Tamb = 0°C to +70°C 70 µA Tamb = -40°C to +85°C 88 µA Tamb = 0°C to +70°C 40 µA Tamb = -40°C to +85°C 50 Minimum VDD = 2V µA T10-4.4 384 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows: 15mA Maximum IOL per port pin: 26mA Maximum IOL per 8-bit port: Maximum IOL total for all outputs: 71mA If IOL exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Capacitive loading on Ports 0 & 2 may cause spurious noise to be superimposed on the VOLs of ALE and Ports 1 & 3. The noise due to external bus capacitance discharging into the Port 0 & 2 pins when the pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. 3. Load capacitance for Port 0, ALE & PSEN#= 100pF, load capacitance for all other outputs = 80pF. ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 49 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications 4. Capacitive loading on Ports 0 & 2 may cause the VOH on ALE and PSEN# to momentarily fall below the VDD - 0.7 specification when the address bits are stabilizing. 5. Pins of Ports 1, 2 & 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when Vin is approximately 2V. 6. Pin capacitance is characterized but not tested. EA# is 25pF (max). 7. See Figures 10-1, 10-2, 10-3 and 10-4 for test conditions. Minimum VDD for Power Down is 2.0V. VDD VDD IDD VDD VDD RST RST EA# (NC) XTAL2 XTAL1 VSS (NC) EA# XTAL2 XTAL1 VSS 384 ILL F25.2 384 ILL F26.2 All other pins disconnected All other pins disconnected FIGURE 10-3: IDD TEST CONDITION, POWER-DOWN MODE FIGURE 10-1: IDD TEST CONDITION, ACTIVE MODE VDD VDD IDD VDD VDD (NC) IDD VDD P0 RST EA# EA# 89x564 89x564 CLOCK SIGNAL VDD VDD = 5V P0 RST VDD 89x564 89x564 CLOCK SIGNAL IDD P0 P0 VDD VDD VDD = 2V (NC) XTAL2 XTAL1 VSS XTAL2 XTAL1 VSS 384 ILL F33.2 384 ILL F24.2 All other pins disconnected All other pins disconnected FIGURE 10-2: IDD TEST CONDITION, IDLE MODE FIGURE 10-4: IDD TEST CONDITION, STANDBY (STOP CLOCK) MODE ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 50 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications 10.4 AC Electrical Characteristics AC Characteristics: (Over Operating Conditions: Load Capacitance for Port 0, ALE#, and PSEN# = 100pF; Load Capacitance for All Other Outputs = 80pF) TABLE 10-5: AC ELECTRICAL CHARACTERISTICS (1 OF 2) Tamb = 0°C TO +70°C OR -40°C TO +85°C, VDD = 2.7-3.6 @25MHZ, 4.5-5.5 @ 40MHZ, VSS = 0 Oscillator 25MHz Symbol Parameter 1/TCLCL TLHLL TAVLL Oscillator Frequency ALE Pulse Width Address Valid to ALE Low Min Max 65 40MHz Min Max 35 15 10 TLLAX Address Hold After ALE Low 15 10 TLLIV ALE Low to Valid Instr In Variable Min Max Units 0 40 MHz 2TCLCL - 15 ns TCLCL - 25 (3V) ns TCLCL - 15 (5V) ns TCLCL - 25 (3V) ns TCLCL - 15 (5V) ns 95 4TCLCL - 65 (3V) 4TCLCL - 45 (5V) 55 TLLPL ALE Low to PSEN# Low TPLPH PSEN# Pulse Width TPLIV PSEN# Low to Valid Instr In 15 ns 10 TCLCL - 15 (5V) ns 3TCLCL - 25 (3V) 3TCLCL - 15 (5V) ns 60 95 65 Input Instr Hold After PSEN# Input Instr Float After PSEN# 3TCLCL - 55 (3V) 3TCLCL - 50 (5V) 0 35 10 TAVIV Address to Valid Instr In 120 65 TPLAZ TRLRH TWLWH PSEN# Low to Address Float RD# Pulse Width Write Pulse Width (WE#) TRLDV RD# Low to Valid Data In TRHDX TRHDZ Data Hold After RD# Data Float After RD# 10 10 200 0 Address to RD# or WR# Low 145 90 85 70 TQVWX Data Valid to WR# High to Low Transition TWHQX Data Hold After WR# ns 5TCLCL - 50 (5V) 270 60 TAVWL 10 0 230 95 ns 5TCLCL - 90 (3V) 150 ALE Low to RD# or WR# Low ns 5TCLCL - 60 (5V) ns 150 TLLWL 5TCLCL - 80 (3V) 6TCLCL - 40 (3V) 6TCLCL - 30 (5V) 55 Address to Valid Data In ns ns 120 38 TAVDV TCLCL - 5 (3V) TCLCL - 15 (5V) ns 110 ALE Low to Valid Data In ns ns 120 75 TLLDV ns 6TCLCL - 40 (3V) 6TCLCL - 30 (5V) 200 0 ns TCLCL - 25 (3V) 25 TPXIX TPXIZ ns 0 3TCLCL - 25 (3V) 3TCLCL - 15 (5V) 5 ©2001 Silicon Storage Technology, Inc. ns ns 2TCLCL - 25 (3V) ns 2TCLCL - 12 (5V) ns 8TCLCL - 90 (3V) ns 8TCLCL - 50 (5V) ns 9TCLCL - 90 (3V) ns 9TCLCL - 75 (5V) ns 3TCLCL + 25 (3V) 3TCLCL + 15 (5V) ns 4TCLCL - 75 (3V) ns 4TCLCL - 30 (5V) ns 0 13 ns 0 ns TCLCL - 27 (3V) ns TCLCL - 20 (5V) ns S71181-03-000 9/01 51 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications TABLE 10-5: AC ELECTRICAL CHARACTERISTICS (CONTINUED) (2 OF 2) Tamb = 0°C TO +70°C OR -40°C TO +85°C, VDD = 2.7-3.6 @25MHZ, 4.5-5.5 @ 40MHZ, VSS = 0 Oscillator 25MHz Symbol Parameter Min TQVWH Data Valid to WR# High 433 Max 40MHz Min Variable Max Min 125 TRLAZ TWHLH RD# Low to Address Float RD# to WR# High to ALE High 0 43 Max ns 7TCLCL - 50 (5V) ns 0 123 10 40 Units 7TCLCL - 70 (3V) 0 ns TCLCL - 25 (3V) TCLCL + 25 (3V) ns TCLCL - 15 (5V) TCLCL + 15 (5V) ns T10-5.5 384 10.5 AC Characteristics Explanation of Symbols Each timing symbol has 5 characters. The first character is always a ‘T’ (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. A: C: D: H: I: L: P: Address Clock Input data Logic level HIGH Instruction (program memory contents) Logic level LOW or ALE PSEN# Q: R: T: V: W: X: Z: Output data RD# signal Time Valid WR# signal No longer a valid logic level High Impedance (Float) For example: TAVLL = Time from Address Valid to ALE Low TLLPL = Time from ALE Low to PSEN# Low VIHT VILT VLOAD +0.1V VHT VLOAD VLT VLOAD -0.1V 384 ILL F28a.2 Timing Reference Points VOH -0.1V VOL +0.1V 384 ILL F28b.0 AC Inputs during testing are driven at VIHT (VDD -0.5V) for Logic "1" and VILT (0.45V) for a Logic "0". Measurement reference points for inputs and outputs are at VHT (0.2VDD + 0.9) and VLT (0.2VDD - 0.1) For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH = ± 20mA. Note: VHT- VHIGH Test VLT- VLOW Test VIHT-VINPUT HIGH Test VILT- VINPUT LOW Test FIGURE 10-5: AC TESTING INPUT/OUTPUT, FLOAT WAVEFORM ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 52 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications TLHLL ALE TAVLL TLLIV TLLPL TPLPH TPLIV PSEN# TPLAZ TPXIZ TLLAX PORT 0 TPXIX A7 - A0 A7 - A0 INSTR IN TAVIV PORT 2 A15 - A8 A15 - A8 384 ILL F13.0 FIGURE 10-6: EXTERNAL PROGRAM MEMORY READ CYCLE TLHLL ALE TWHLH PSEN# TLLDV TRLRH TLLWL RD# TLLAX TAVLL PORT 0 TRLDV TRLAZ TRHDZ TRHDX A7-A0 FROM RI or DPL DATA IN A7-A0 FROM PCL INSTR IN TAVWL TAVDV PORT 2 P2[7:0] or A15-A8 FROM DPH A15-A8 FROM PCH 384 ILL F14.0 FIGURE 10-7: EXTERNAL DATA MEMORY READ CYCLE ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 53 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications TLHLL ALE TWHLH PSEN# TWLWH TLLWL WR# TLLAX TQVWX TAVLL TWHQX TQVWH PORT 0 A7-A0 FROM RI or DPL DATA OUT A7-A0 FROM PCL INSTR IN TAVWL PORT 2 P2[7:0] or A15-A8 FROM DPH A15-A8 FROM PCH 384 ILL F15.0 FIGURE 10-8: EXTERNAL DATA MEMORY WRITE CYCLE TABLE 10-6: EXTERNAL CLOCK DRIVE Oscillator 25MHz Symbol 1/TCLCL TCHCX TCLCX TCLCH TCHCL Parameter Oscillator Frequency High Time Low Time Rise Time Fall Time Min 40MHz Max Min 20 20 Max Variable Min 0 0.35TCLCL 0.35TCLCL Max 40 0.65TCLCL 0.65TCLCL 10 10 Units MHz ns ns ns ns T10-6.2 384 VDD = -0.5 0.45 V 0.7 VDD TCHCX 0.2 VDD -0.1 TCLCX TCLCH TCLCL TCHCL 384 ILL F30.0 FIGURE 10-9: EXTERNAL CLOCK DRIVE WAVEFORM ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 54 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications TABLE 10-7: SERIAL PORT TIMING Oscillator 25MHz Symbol Parameter Min 40MHz Max Min Variable Max Min Max Units TXLXL Serial Port Clock Cycle Time 0 0.36 12TCLCL ms TQVXH Output Data Setup to Clock Rising Edge 700 117 10TCLCL - 133 ns TXHQX Output Data Hold After Clock Rising Edge 50 2TCLCL - 117 ns 2TCLCL - 50 ns 0 TXHDX Input Data Hold After Clock Rising Edge TXHDV Clock Rising Edge to Input Data Valid 0 0 700 0 ns 117 10TCLCL - 133 ns T10-7.2 384 INSTRUCTION 0 1 2 3 4 5 6 7 8 ALE TXLXL CLOCK OUTPUT DATA WRITE TO SBUF INPUT DATA TQVXH TXHQX 0 1 2 TXHDV VALID 3 4 5 6 TXHDX VALID 7 SET TI VALID VALID VALID VALID VALID VALID SET R I CLEAR RI 384 ILL F29.0 FIGURE 10-10: SHIFT REGISTER MODE TIMING WAVEFORMS ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 55 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications 11.0 PRODUCT ORDERING INFORMATION Device SST89x5x4 Speed - XX Suffix1 - X Suffix2 - XX Package Modifier I = 40 pins J = 44 pins Package Type P = PDIP N = PLCC TQ = TQFP Operation Temperature C = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C Operating Frequency 25 = 0-25MHz 40 = 0-40MHz Feature Set and Flash Memory Size 564 = C52 feature set + 64(72)* KByte 554 = C52 feature set + 32(40)* KByte * = 8K additional flash can be enabled Voltage Range E = 4.5-5.5V V = 2.7-3.6V Device Family 89 = C51 Core 11.1 Valid Combinations Valid combinations for SST89E564 SST89E564-40-C-PI SST89E564-40-C-NJ SST89E564-40-C-TQJ SST89E564-40-I-PI SST89E564-40-I-NJ SST89E564-40-I-TQJ Valid combinations for SST89V564 SST89V564-25-C-PI SST89V564-25-C-NJ SST89V564-25-C-TQJ SST89V564-25-I-PI SST89V564-25-I-NJ SST89V564-25-I-TQJ Valid combinations for SST89E554 SST89E554-40-C-PI SST89E554-40-C-NJ SST89E554-40-C-TQJ SST89E554-40-I-PI SST89E554-40-I-NJ SST89E554-40-I-TQJ Valid combinations for SST89V554 SST89V554-25-C-PI SST89V554-25-C-NJ SST89V554-25-C-TQJ SST89V554-25-I-PI SST89V554-25-I-NJ SST89V554-25-I-TQJ Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 56 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications 12.0 PACKAGING DIAGRAMS 40 CL .600 .625 1 Pin #1 Identifier .530 .557 2.020 2.070 .065 .075 12˚ 4 places .220 Max. Base Plane Seating Plane .015 Min. .063 .090 Note: .045 .055 .015 .022 .100 † .200 .100 BSC 0˚ 15˚ .008 .012 .600 BSC 1. Complies with JEDEC publication 95 MS-011 AC dimensions (except as noted), although some dimensions may be more stringent. † = JEDEC min is .115; SST min is less stringent 2. All linear dimensions are in inches (min/max). 40.pdipPI-ILL.7 3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches. 40-PIN PLASTIC DUAL IN-LINE PINS (PDIP) SST PACKAGE CODE: PI TOP VIEW .685 .695 .646 † .656 Optional Pin #1 Identifier .042 .048 1 44 SIDE VIEW .020 R. MAX. .042 x45˚ .056 .147 .158 .025 R. .045 .013 .021 .042 .048 .685 .695 BOTTOM VIEW .646 † .656 .500 REF. .026 .032 .590 .630 .050 BSC. .100 .112 .050 BSC. .165 .180 Note: .020 Min. .026 .032 44.PLCC.NJ-ILL.7 1. Complies with JEDEC publication 95 MS-018 AC dimensions (except as noted), although some dimensions may be more stringent. † = JEDEC min is .650; SST min is less stringent 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. 4. Coplanarity: 4 mils. 44-LEAD PLASTIC LEAD CHIP CARRIER (PLCC) SST PACKAGE CODE: NJ ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 57 384 FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 Preliminary Specifications Pin #1 Identifier 34 44 33 1 .30 .45 10.00 BSC 12.00 BSC 11 .80 BSC 23 12 10.00 BSC 12.00 BSC .09 .20 22 .95 1.05 .05 .15 1.2 max. .45 .75 0˚- 7˚ 1.00 ref 44.tqfp-TQJ-ILL.6 Note: 1. Complies with JEDEC publication 95 MS-026 ACB dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (±0.05) mm. 4. Package body dimensions do not include mold flash. Maximum allowable mold flash is .25mm. 44-LEAD THIN QUAD FLAT PACK (TQFP) SST PACKAGE CODE: TQJ Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 www.SuperFlash.com or www.ssti.com ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 58 384