ETC ST72E251G2D0

ST72251
8-BIT MCU WITH 4 TO 8K ROM/OTP/EPROM,
256 BYTES RAM, ADC, WDG, SPI, I2C AND 2 TIMERS
DATASHEET
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User Program Memory (ROM/OTP/EPROM):
4 to 8K bytes
Data RAM: 256 bytes, including 64 bytes of
stack
Master Reset and Power-On Reset
Run, Wait, Slow and Halt modes
22 multifunctional bidirectional I/O lines:
– 22 programmable interrupt inputs
– 8 high sink outputs
– 6 Analog alternate inputs
– 16 Alternate Functions
– EMI filtering
Programmable watchdog (WDG)
Two 16-bit Timers, each featuring:
– 2 Input Captures
– 2 Output Compares
– External Clock input (on Timer A only)
– PWM and Pulse Generator modes
Synchronous Serial Peripheral Interface (SPI)
Full I2C multiple Master/Slave interface
8-bit Analog-to-Digital converter (6 channels)
8-bit Data Manipulation
63 Basic Instructions
17 main Addressing Modes
8 x 8 Unsigned Multiply Instruction
True Bit Manipulation
Complete Development Support on PC/DOSWINDOWSTM Real-Time Emulator
Full Software Package on DOS/WINDOWSTM
(C-Compiler, Cross-Assembler, Debugger)
PSDIP32
CSDIP32W
SO28
(See ordering information at the end of datasheet)
Device Summary
Features
Program Memory
- bytes
RAM (stack) - bytes
Peripherals
Operating Supply
CPU Frequency
Temperature Range
Package
ST72251G1
ST72251G2
4K
8K
256 (64)
Watchdog, Timers, SPI, I2C, ADC
3 to 5.5 V
8MHz max (16MHz oscillator)
4MHz max over 85°C
- 40°C to + 125°C
SO28 - SDIP32
Rev. 1.9
June 2001
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1
Table of Contents
ST72251 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 EXTERNAL CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 CLOCKS, RESET, INTERRUPTS & POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.2 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.3 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.4 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
16
16
16
16
16
17
17
4.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.2 Slow Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.3 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.4 Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 MISCELLANEOUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
20
20
20
21
22
5 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.3 I/O Port Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
23
24
27
29
5.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
...
29
29
30
30
30
30
31
31
5.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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5.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.6 Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4 I2C BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.8 Application Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
43
43
43
44
49
49
49
49
51
55
55
56
61
64
5.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64
64
64
66
73
73
74
77
5.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
77
77
78
78
78
79
80
80
6.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.7 Relative Mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
81
81
81
81
81
82
82
83
7 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
7.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
7.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
7.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
7.4 RESET CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
7.5 OSCILLATOR CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
7.6 A/D CONVERTER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
7.7 SPI CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
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7.8 I2C CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
8 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
8.1 EPROM ERASURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
8.2 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
8.3 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
8.3.1 Transfer Of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
9 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
95
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ST72251
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST72251 HCMOS Microcontroller Unit is a
member of the ST7 family of Microcontrollers. The
device is based on an industry-standard 8-bit core
and features an enhanced instruction set. The device normally operates at a 16MHz oscillator frequency. Under software control, the ST72251 may
be placed in either WAIT, SLOW or HALT modes,
thus reducing power consumption. The enhanced
instruction set and addressing modes afford real
programming potential. In addition to standard 8bit data management, the ST72251 features true
bit manipulation, 8x8 unsigned multiplication and
indirect addressing modes on the whole memory.
The device includes an on-chip oscillator, CPU,
program memory (ROM/OTP/EPROM versions),
RAM, 22 I/O lines and the following on-chip peripherals: Analog-to-Digital converter (ADC) with 6
multiplexed analog inputs, industry standard synchronous SPI serial interface, I2C multiple Master/
Slave interface, digital Watchdog, two independent 16-bit Timers, one featuring an External Clock
Input, and both featuring Pulse Generator capabilities, 2 Input Captures and 2 Output Compares.
Figure 1. ST72251 Block Diagram
OSCIN
I2C
Internal
CLOCK
OSC
OSCOUT
RESET
PORT A
RAM
(256 Bytes)
VSS
POWER
SUPPLY
PORT B
ADDRESS AND DATA BUS
PROGRAM
MEMORY
(4 - 8K Bytes)
VDD
SPI
CONTROL
8-BIT CORE
ALU
PA0 -> PA7
(8 bits)
PB0 -> PB7
(8 bits)
TIMER A
PORT C
PC0 -> PC5
(6 bits)
8-BIT ADC
TIMER B
WATCHDOG
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ST72251
1.2 PIN DESCRIPTION
Figure 2. ST72251 Pinout (SDIP32)
RESET
OSCIN
OSCOUT
SS/PB7
SCK/PB6
MISO/PB5
MOSI/PB4
NC
NC
OCMP2_A/PB3
ICAP2_A/PB2
OCMP1_A/PB1
ICAP1_A/PB0
AIN5/EXTCLK_A/PC5
AIN4/OCMP2_B/PC4
AIN3/ICAP2_B/PC3
1
32
2
31
3
30
4
29
5
28
6
27
7
26
8
25
9
24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
VDD
VSS
TEST/VPP1)
PA0
PA1
PA2
PA3
NC
NC
PA4/SCL
PA5
PA6/SDA
PA7
PC0/ICAP1_B/AIN0
PC1/OCMP1_B/AIN1
PC2/CLKOUT/AIN2
1) V
on EPROM/OTP only
PP
Figure 3. ST72251 Pinout (SO28)
RESET
OSCIN
OSCOUT
SS/PB7
SCK/PB6
MISO/PB5
MOSI/PB4
OCMP2_A/PB3
ICAP2_A/PB2
OCMP1_A/PB1
ICAP1_A/PB0
AIN5/EXTCLK_A/PC5
AIN4/OCMP2_B/PC4
AIN3/ICAP2_B/PC3
1) V
on EPROM/OTP only
PP
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5
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
VDD
VSS
TEST/VPP1)
PA0
PA1
PA2
PA3
PA4/SCL
PA5
PA6/SDA
PA7
PC0/ICAP1_B/AIN0
PC1/OCMP1_B/AIN1
PC2/CLKOUT/AIN2
ST72251
Table 1. ST72251 Pin Configuration
Pin n° Pin n°
SDIP32 SO28
Pin Name
Type
Description
Remarks
1
1
RESET
I/O Bidirectional. Active low. Top priority non maskable interrupt.
2
2
OSCIN
I
3
3
OSCOUT
O
4
4
PB7/SS
I/O
Port B7 or SPI Slave Select (active low)
External Interrupt: EI1
5
5
PB6/SCK
I/O
Port B6 or SPI Serial Clock
External Interrupt: EI1
6
6
PB5/MISO
I/O
Port B5 or SPI Master In/ Slave Out Data
External Interrupt: EI1
7
7
PB4/MOSI
I/O
Port B4 or SPI Master Out / Slave In Data
External Interrupt: EI1
Input/Output Oscillator pin. These pins connect a parallel-resonant crystal,
or an external source to the on-chip oscillator.
8
NC
Not Connected
9
NC
Not Connected
10
8
PB3/OCMP2_A
I/O
Port B3 or TimerA Output Compare 2
External Interrupt: EI1
11
9
PB2/ICAP2_A
I/O
Port B2 or TimerA Input Capture 2
External Interrupt: EI1
12
10
PB1/OCMP1_A
I/O
Port B1 or TimerA Output Compare 1
External Interrupt: EI1
13
11
PB0/ICAP1_A
I/O
Port B0 or TimerA Input Capture 1
External Interrupt: EI1
14
12
PC5/EXTCLK_A/AIN5
I/O
Port C5 or TimerA Input Clock or ADC Analog Input 5 External Interrupt: EI1
15
13
PC4/OCMP2_B/AIN4
I/O
16
14
PC3/ICAP2_B/AIN3
I/O
17
15
PC2/CLKOUT/AIN2
I/O
18
16
PC1/OCMP1_B/AIN1
I/O
19
17
PC0/ICAP1_B/AIN0
I/O
20
18
PA7
I/O
Port A7, High Sink
External Interrupt: EI0
21
19
PA6/SDA
I/O
Port A6 or I2 C Data, High Sink
External Interrupt: EI0
22
20
PA5
I/O
Port A5, High Sink
External Interrupt: EI0
23
21
PA4/SCL
I/O
Port C4 or TimerB Output Compare 2 or ADC
Analog Input 4
Port C3 or TimerB Input Capture 2 or ADC Analog
Input 3
Port C2 or Internal Clock Frequency output or ADC
Analog Input 2. Clockout is driven by the MCO bit
of the miscellaneous register.
Port C1 or TimerB Output Compare 1 or ADC
Analog Input 1
Port C0 or TimerB Input Capture 1 or ADC Analog
Input 0
Port A4 or
I2 C
Clock, High Sink
24
NC
Not Connected
25
NC
Not Connected
External Interrupt: EI1
External Interrupt: EI1
External Interrupt: EI1
External Interrupt: EI1
External Interrupt: EI1
External Interrupt: EI0
26
22
PA3
I/O Port A3, High Sink
External Interrupt: EI0
27
23
PA2
I/O Port A2, High Sink
External Interrupt: EI0
28
24
PA1
I/O
Port A1, High Sink
External Interrupt: EI0
29
25
PA0
I/O
Port A0, High Sink
External Interrupt: EI0
30
26
TEST/VPP
I/S
Test mode pin (should be tied low in user mode). In the EPROM programming mode, this pin acts as the programming voltage input VPP.
31
27
VSS
S
Ground
32
28
VDD
S
Main power supply
7/100
6
ST72251
1.3 EXTERNAL CONNECTIONS
The following figure shows the recommended external connections for the device.
The VPP pin is only used for programming OTP
and EPROM devices and must be tied to ground in
user mode.
The 10 nF and 0.1 µF decoupling capacitors on
the power supply lines are a suggested EMC performance/cost tradeoff.
The external reset network is intended to protect
the device against parasitic resets, especially in
noisy environments.
Unused I/Os should be tied high to avoid any unnecessary power consumption on floating lines.
An alternative solution is to program the unused
ports as inputs with pull-up.
Figure 4. Recommended External Connections
VPP
VDD
10nF
VDD
+
0.1µF
VSS
V DD
4.7K
0.1µF
RESET
EXTERNAL RESET CIRCUIT
0.1µF
See
Clocks
Section
OSCIN
OSCOUT
Or configure unused I/O ports
by software as input with pull-up
VDD
8/100
7
10K
Unused I/O
ST72251
1.4 MEMORY MAP
Figure 5. Memory Map
0000h
0080h
HW Registers
Short Addressing
(see Table 3)
007Fh
RAM (zero page)
0080h
00FFh
0100h
16-bit Addressing
256 Bytes RAM
RAM
013Fh
017Fh
0140h
64 Bytes Stack/
0180h
16-bit Addressing RAM
017Fh
Reserved
DFFFh
E000h
8K Bytes
Program Memory
F000h
4K Bytes
FFDFh
Program
Memory
FFE 0h
Interrupt & Reset Vectors
(see Table 2)
FFF Fh
Table 2. Interrupt Vector Map
Vector Address
Description
Remarks
FFE0-FFE1h
FFE2-FFE3h
FFE4-FFE5h
Not Used
Not Used
I2C Interrupt Vector
Internal Interrupt
FFE6-FFE7h
FFE8-FFE9h
FFEA-FFEBh
Not Used
Not Used
Not Used
FFEC-FFEDh
FFEE-FFEFh
FFF0-FFF1h
Not Used
TIMER B Interrupt Vector
Not Used
Internal Interrupt
FFF2-FFF3h
FFF4-FFF5h
TIMER A Interrupt Vector
SPI Interrupt Vector
Internal Interrupt
Internal Interrupt
FFF6-FFF7h
FFF8-FFF9h
FFFA-FF FBh
Not Used
External Interrupt Vector EI1
External Interrupt Vector EI0
External Interrupt
External Interrupt
FFFC-FFFDh
FFFE-FFFFh
TRAP (software) Interrupt Vector
RESET Vector
CPU Interrupt
9/100
8
ST72251
Table 3. Hardware Register Memory Map
Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
Block
Name
Register Label
Port C
PCDR
PCDDR
PCOR
Port B
PBDR
PBDDR
PBOR
Port A
PADR
PADDR
PAOR
000Bh to
001Fh
0020h
0021h
0022h
0023h
0024h
Data Register
Data Direction Register
Option Register
Reserved Area (1 Byte)
Data Register
Data Direction Register
Option Register
Reserved Area (1 Byte)
Data Register
Data Direction Register
Option Register
Reset Status
Remarks
00h
00h
00h
R/W
R/W
R/W
00h
00h
00h
R/W
R/W
R/W
00h
00h
00h
R/W
R/W
R/W
00h
xxh
0xh
00h
7Fh
R/W
R/W
Read Only
R/W
Reserved Area (21 Bytes)
SPI
WDG
MISCR
SPIDR
SPICR
SPISR
WDGCR
0025h to
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
Register name
Miscellaneous Register
Data I/O Register
Control Register
Status Register
Watchdog Control register
Reserved Area (3 Bytes)
I 2C
I2CCR
I2CSR1
I2CSR2
I2CCCR
I2COAR1
I2COAR2
I2CDR
002Fh
0030h
Control Register
Status Register 1
Status Register 2
Clock Control Register
Own Address Register 1
Own Address Register 2
Data Register
R/W
00h
00h
00h
00h
00h
40h
00h
Read Only
Read Only
R/W
R/W
R/W
R/W
00h
00h
00h
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
Read Only
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
R/W
Reserved Area (2 Bytes)
0031h
0032h
0033h
0034h-0035h
0036h-0037h
0038h-0039h
003Ah-003Bh
003Ch-003Dh
003Eh-003Fh
0040h
Timer A
TACR2
TACR1
TASR
TAIC1HR
TAIC1LR
TAOC1HR
TAOC1LR
TACHR
TACLR
TAACHR
TAACLR
TAIC2HR
TAIC2LR
TAOC2HR
TAOC2LR
Control Register2
Control Register1
Status Register
Input Capture1 High Register
Input Capture1 Low Register
Output Compare1 High Register
Output Compare1 Low Register
Counter High Register
Counter Low Register
Alternate Counter High Register
Alternate Counter Low Register
Input Capture2 High Register
Input Capture2 Low Register
Output Compare2 High Register
Output Compare2 Low Register
Reserved Area (1 Byte)
10/100
9
ST72251
Address
Block
Name
0041h
0042h
0043h
0044h-0045h
0046h-0047h
0048h-0049h
Timer B
004Ah-004Bh
004Ch-004Dh
004Eh-004Fh
Register Label
TBCR2
TBCR1
TBSR
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
TBCHR
TBCLR
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR
0050h to
006Fh
0070h
0071h
0072h to
007Fh
Register name
Control Register2
Control Register1
Status Register
Input Capture1 High Register
Input Capture1 Low Register
Output Compare1 High Register
Output Compare1 Low Register
Counter High Register
Counter Low Register
Alternate Counter High Register
Alternate Counter Low Register
Input Capture2 High Register
Input Capture2 Low Register
Output Compare2 High Register
Output Compare2 Low Register
Reset Status
Remarks
00h
00h
00h
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
Read Only
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
R/W
00h
00h
Read Only
R/W
Reserved Area (32 Bytes)
ADC
ADCDR
ADCCSR
Data Register
Control/Status Register
Reserved Area (14 Bytes)
11/100
10
ST72251
2 CENTRAL PROCESSING UNIT
2.1 INTRODUCTION
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
2.2 MAIN FEATURES
■
■
■
■
■
■
■
■
63 basic instructions
Fast 8-bit by 8-bit multiply
17 main addressing modes
Two 8-bit index registers
16-bit stack pointer
Low power modes
Maskable hardware interrupts
Non-maskable software interrupt
2.3 CPU REGISTERS
The 6 CPU registers shown in Figure 6 are not
present in the memory mapping and are accessed
by specific instructions.
Accumulator (A)
The Accumulator is an 8-bit general purpose register used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.
Index Registers (X and Y)
In indexed addressing modes, these 8-bit registers
are used to create either effective addresses or
temporary storage areas for data manipulation.
(The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)
The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from
the stack).
Program Counter (PC)
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
Figure 6. CPU Registers
7
0
ACCUMULATOR
RESET VALUE = XXh
7
0
X INDEX REGISTER
RESET VALUE = XXh
7
0
Y INDEX REGISTER
RESET VALUE = XXh
15
PCH
8 7
PCL
0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
1 1 1 H I
0
N Z C
CONDITIO N CODE REGISTER
RESET VALUE = 1 1 1 X 1 X X X
15
8
7
0
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value
12/100
11
ST72251
CPU REGISTERS (Cont’d)
CONDITION CODE REGISTER (CC)
Read/Write
Reset Value: 111x1xxx
7
1
0
1
1
H
I
N
Z
because the I bit is set by hardware at the start of
the routine and reset by the IRET instruction at the
end of the routine. If the I bit is cleared by software
in the interrupt routine, pending interrupts are
serviced regardless of the priority level of the current interrupt routine.
C
The 8-bit Condition Code register contains the interrupt mask and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP instructions.
These bits can be individually tested and/or controlled by specific instructions.
Bit 4 = H Half carry.
This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or
ADC instruction. It is reset by hardware during the
same instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.
Bit 3 = I Interrupt mask.
This bit is set by hardware when entering in interrupt or by software to disable all interrupts except
the TRAP software interrupt. This bit is cleared by
software.
0: Interrupts are enabled.
1: Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions.
Note: Interrupts requested while I is set are
latched and can be processed when I is cleared.
By default an interrupt routine is not interruptable
Bit 2 = N Negative.
This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic,
logical or data manipulation. It is a copy of the 7th
bit of the result.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(i.e. the most significant bit is a logic 1).
This bit is accessed by the JRMI and JRPL instructions.
Bit 1 = Z Zero.
This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test
instructions.
Bit 0 = C Carry/borrow.
This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
13/100
12
ST72251
CENTRAL PROCESSING UNIT (Cont’d)
Stack Pointer (SP)
Read/Write
Reset Value: 01 7Fh
15
8
0
0
0
0
0
0
0
7
1
0
0
1
SP5
SP4
SP3
SP2
SP1
SP0
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 7).
Since the stack is 64 bytes deep, the 10 most significant bits are forced by hardware. Following an
MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP5 to SP0 bits are set) which is the stack
higher address.
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD instruction.
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously
stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 7.
– When an interrupt is received, the SP is decremented and the context is pushed on the stack.
– On return from interrupt, the SP is incremented
and the context is popped from the stack.
A subroutine call occupies two locations and an interrupt five locations in the stack area.
Figure 7. Stack Manipulation Example
CALL
Subroutine
PUSH Y
Interrupt
Event
POP Y
RET
or RSP
IRET
@ 0140h
SP
SP
CC
A
X
X
X
PCH
PCH
PCH
PCL
PCL
PCL
PCH
PCH
PCH
PCH
PCH
PCL
PCL
PCL
PCL
PCL
SP
@ 017Fh
Stack Lower Address = 0140h
Stack Higher Address = 017Fh
14/100
13
SP
Y
CC
A
CC
A
SP
SP
ST72251
3 CLOCKS, RESET, INTERRUPTS & POWER SAVING MODES
3.1 CLOCK SYSTEM
3.1.1 General Description
The MCU accepts either a Crystal or Ceramic resonator, or an external clock signal to drive the internal oscillator. The internal clock (fCPU) is derived from the external oscillator frequency (fOSC).
The external Oscillator clock is first divided by 2,
and a division factor of 32 can be applied if Slow
Mode is selected by setting the SMS bit in the Miscellaneous Register. This reduces the frequency
of the fCPU ; the clock signal is also routed to the
on-chip peripherals.
The internal oscillator is designed to operate with
an AT-cut parallel resonant quartz crystal resonator in the frequency range specified for fosc. The
circuit shown in Figure 9 is recommended when
using a crystal, and Table 4 lists the recommended capacitance and feedback resistance values.
The crystal and associated components should be
mounted as close as possible to the input pins in
order to minimize output distortion and start-up
stabilisation time.
Use of an external CMOS oscillator is recommended when crystals outside the specified frequency ranges are to be used.
Figure 8. External Clock Source Connections
OSCIN
OSCOUT
NC
EXTERNAL
CLOCK
Figure 9. Crystal/Ceramic Resonator
OSCIN
OSCOUT
Table 4. .Recommended Values for 16 MHz
Crystal Resonator (C0 < 7pF)
R SMAX
40 Ω
60 Ω
150 Ω
COSCIN
56pF
47pF
22pF
COSCOUT
56pF
47pF
22pF
C0: parasitic shunt capacitance of the quartz crystal.
RSMAX: equivalent serial resistor of the crystal (uper limit, see crystal specification).
COSCOUT , COSCIN: maximum total capacitance on
OSCIN and OSCOUT, including the external capacitance plus the parasitic capacitance of the
board and the device.
COSCIN
C OSCOUT
Figure 10. Clock Prescaler Block Diagram
%2
OSCIN
COSCIN
OSCOUT
% 16
fCPU
to CPU and
Peripherals
COSCOUT
15/100
14
ST72251
3.2 RESET
3.2.1 Introduction
There are three sources of Reset:
– RESET pin (external source)
– Power-On Reset (Internal source)
– WATCHDOG (Internal Source)
The Reset Service Routine vector is located at address FFFEh-FFFFh.
3.2.2 External Reset
The RESET pin is both an input and an open-drain
output with integrated pull-up resistor. When one
of the internal Reset sources is active, the Reset
pin is driven low, for a duration of tRESET, to reset
the whole application.
3.2.3 Reset Operation
The duration of the Reset state is a minimum of
4096 internal CPU Clock cycles. During the Reset
state, all I/Os take their reset value.
A Reset signal originating from an external source
must have a duration of at least tPULSE in order to
be recognised. This detection is asynchronous
and therefore the MCU can enter Reset state even
in Halt mode.
At the end of the Reset cycle, the MCU may be
held in the Reset state by an External Reset signal. The RESET pin may thus be used to ensure
VDD has risen to a point where the MCU can operate correctly before the user program is run. Fol-
lowing a Reset event, or after exiting Halt mode, a
4096 CPU Clock cycle delay period is initiated in
order to allow the oscillator to stabilise and to ensure that recovery has taken place from the Reset
state.
In the high state, the RESET pin is connected internally to a pull-up resistor (RON). This resistor
can be pulled low by external circuitry to reset the
device.
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to use the external connections shown in Figure 4.
3.2.4 Power-on Reset
This circuit detects the ramping up of V DD, and
generates a pulse that is used to reset the application (at approximately VDD= 2V).
Power-On Reset is designed exclusively to cope
with power-up conditions, and should not be used
in order to attempt to detect a drop in the power
supply voltage.
Caution: to re-initialize the Power-On Reset, the
power supply must fall below approximately 0.8V
(Vtn), prior to rising above 2V. If this condition is
not respected, on subsequent power-up the Reset
pulse may not be generated. An external Reset
pulse may be required to correctly reactivate the
circuit.
Figure 11. Reset Block Diagram
INTERNAL
TO ST7
RESET
COUNTER
RESET
OSCILLATOR
SIGNAL
RESET
VDD
RON
POWER-ON RESET
WATCHDOG RESET
16/100
15
ST72251
4 INTERRUPTS
The ST7 core may be interrupted by one of two different methods: maskable hardware interrupts as
listed in the Interrupt Mapping Table and a nonmaskable software interrupt (TRAP). The Interrupt
processing flowchart is shown in Figure 12.
The maskable interrupts must be enabled by
clearing the I bit in order to be serviced. However,
disabled interrupts may be latched and processed
when they are enabled (see external interrupts
subsection).
Note: After reset, all interrupts are disabled.
When an interrupt has to be serviced:
– Normal processing is suspended at the end of
the current instruction execution.
– The PC, X, A and CC registers are saved onto
the stack.
– The I bit of the CC register is set to prevent additional interrupts.
– The PC is then loaded with the interrupt vector of
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
the Interrupt Mapping Table for vector addresses).
The interrupt service routine should finish with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
Note: As a consequence of the IRET instruction,
the I bit will be cleared and the main program will
resume.
Priority Management
By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware entering in interrupt routine.
In the case when several interrupts are simultaneously pending, an hardware priority defines which
one will be serviced first (see the Interrupt Mapping Table).
Interrupts and Low Power Mode
All interrupts allow the processor to leave the
WAIT low power mode. Only external and specifically mentioned interrupts allow the processor to
leave the HALT low power mode (refer to the “Exit
from HALT“ column in the Interrupt Mapping Table).
4.1 NON MASKABLE SOFTWARE INTERRUPT
This interrupt is entered when the TRAP instruction is executed regardless of the state of the I bit.
It will be serviced according to the flowchart on
Figure 12.
4.2 EXTERNAL INTERRUPTS
External interrupt vectors can be loaded into the
PC register if the corresponding external interrupt
occurred and if the I bit is cleared. These interrupts
allow the processor to leave the Halt low power
mode.
The external interrupt polarity is selected through
the miscellaneous register or interrupt register (if
available).
An external interrupt triggered on edge will be
latched and the interrupt request automatically
cleared upon entering the interrupt service routine.
If several input pins, connected to the same interrupt vector, are configured as interrupts, their signals are logically ANDed and inverted before entering the edge/level detection block.
Caution: The type of sensitivity defined in the Miscellaneous or Interrupt register (if available) applies to the ei source. In case of an ANDed source
(as described on the I/O ports section), a low level
on an I/O pin configured as input with interrupt,
masks the interrupt request even in case of risingedge sensitivity.
4.3 PERIPHERAL INTERRUPTS
Different peripheral interrupt flags in the status
register are able to cause an interrupt when they
are active if both:
– The I bit of the CC register is cleared.
– The corresponding enable bit is set in the control
register.
If any of these two conditions is false, the interrupt
is latched and thus remains pending.
Clearing an interrupt request is done by:
– Writing “0” to the corresponding bit in the status
register or
– Access to the status register while the flag is set
followed by a read or write of an associated register.
Note: the clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being enabled) will therefore be lost if the clear sequence is
executed.
17/100
16
ST72251
INTERRUPTS (Cont’d)
Figure 12. Interrupt Processing Flowchart
FROM RESET
I BIT SET?
N
N
Y
Y
FETCH NEXT INSTR UCTION
N
IRET?
Y
STACK PC, X, A, CC
SET I BIT
LOAD PC FROM INTERRUPT VECTO R
EXECU TE INSTRUCTION
RESTORE PC, X, A, CC FROM STACK
THIS CLEARS I BIT BY DEFAULT
18/100
17
INTE RRUPT
PENDING ?
ST72251
Table 5. Interrupt Mapping
Source
Block
RESET
TRAP
EI0
EI1
SPI
TIMER A
TIMER B
Description
Reset
Software
External Interrupt PA0:PA7
External Interrupt PB0:PB7, PC0:PC5
Not Used
Transfer Complete
Mode Fault
Input Capture 1
Output Compare 1
Input Capture 2
Output Compare 2
Timer Overflow
Not Used
Input Capture 1
Output Compare 1
Input Capture 2
Output Compare 2
Timer Overflow
Register
Label
Flag
Exit
from
HALT
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
yes
no
yes
yes
FFFEh-FFF Fh
FFFCh-FFF Dh
FFFAh-FFFBh
FFF8h-FFF 9h
FFF6h-FFF 7h
no
FFF4h-FFF 5h
no
FFF2h-FFF 3h
SPISR
TASR
SPIF
MODF
ICF1_A
OCF1_A
ICF2_A
OCF2_A
TOF_A
I2C Peripheral Interrupts
Not Used
Priority
Order
Highest
Priority
FFF0h-FFF 1h
TBSR
ICF1_B
OCF1_B
ICF2_B
OCF2_B
TOF_B
no
FFEEh-FFEFh
FFECh-FFEDh
FFEAh-FFE Bh
FFE8h-FFE9h
FFE6h-FFE7h
Not Used
I2C
Vector
Address
I2CSR1
I2CSR2
**
no
FFE4h-FFE5h
FFE2h-FFE3h
FFE0h-FFE1h
Lowest
Priority
** Many flags can cause an interrupt, see peripheral interrupt status register description.
19/100
18
ST72251
4.4 POWER SAVING MODES
4.4.1 Introduction
There are three Power Saving modes. Slow Mode
is selected by setting the relevant bits in the Miscellaneous register. Wait and Halt modes may be
entered using the WFI and HALT instructions.
Figure 13. WAIT Flow Chart
WFI INSTRUCTION
4.4.2 Slow Mode
In Slow mode, the oscillator frequency can be divided by a value defined in the Miscellaneous
Register. The CPU and peripherals are clocked at
this lower frequency. Slow mode is used to reduce
power consumption, and enables the user to adapt
clock frequency to available supply voltage.
4.4.3 Wait Mode
Wait mode places the MCU in a low power consumption mode by stopping the CPU. All peripherals remain active. During Wait mode, the I bit (CC
Register) is cleared, so as to enable all interrupts.
All other registers and memory remain unchanged.
The MCU will remain in Wait mode until an Interrupt or Reset occurs, whereupon the Program
Counter branches to the starting address of the Interrupt or Reset Service Routine.
The MCU will remain in Wait mode until a Reset or
an Interrupt occurs, causing it to wake up.
Refer to Figure 13 below.
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
ON
ON
OFF
I-BIT
CLEARED
N
RESET
N
Y
INTERRUPT
Y
ON
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
ON
ON
I-BIT
SET
4096 CPU CLOCK
CYCLES DELAY
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
ON
ON
ON
I-BIT
SET
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note: Before servicing an interrupt, the CC register is
pushed on the stack. The I-Bit is set during the interrupt routine and cleared when the CC register is
popped.
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ST72251
POWER SAVING MODES (Cont’d)
4.4.4 Halt Mode
The Halt mode is the MCU lowest power consumption mode. The Halt mode is entered by executing the HALT instruction. The internal oscillator
is then turned off, causing all internal processing to
be stopped, including the operation of the on-chip
peripherals. The Halt mode cannot be used when
the watchdog is enabled, if the HALT instruction is
executed while the watchdog system is enabled, a
watchdog reset is generated thus resetting the entire MCU.
When entering Halt mode, the I bit in the CC Register is cleared so as to enable External Interrupts.
If an interrupt occurs, the CPU becomes active.
The MCU can exit the Halt mode upon reception of
an interrupt or a reset. Refer to the Interrupt Mapping Table. The oscillator is then turned on and a
stabilization time is provided before releasing CPU
operation. The stabilization time is 4096 CPU clock
cycles.
After the start up delay, the CPU continues operation by servicing the interrupt which wakes it up or
by fetching the reset vector if a reset wakes it up.
Figure 14. HALT Flow Chart
HALT INSTRUCTION
WATCHDOG
Y
WDG
ENABLED?
RESET
N
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
OFF
OFF
OFF
I-BIT
CLEARED
N
RESET
N
EXTERNAL
INTERRUPT1)
Y
Y
OSCILLATOR
PERIPH. CLOCK2)
CPU CLOCK
ON
OFF
ON
I-BIT
SET
4096 CPU CLOCK
CYCLES DELAY
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
ON
ON
ON
I-BIT
SET
FETCH RESET VECTOR
OR SERVICE INTERRUPT
1) or some specific interrupts
2) if reset PERIPH. CLOCK = ON ; if interrupt
PERIPH. CLOCK = OFF
Note: Before servicing an interrupt, the CC register is
pushed on the stack. The I-Bit is set during the interrupt routine and cleared when the CC register is
popped.
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ST72251
4.5 MISCELLANEOUS REGISTER
The Miscellaneous register allows to select the
SLOW operating mode, the polarity of external interrupt requests and to output the internal clock.
Register Address: 0020h — Read/ Write
Reset Value: 0000 0000 (00h)
7
PEI3
0
PEI2
MCO PEI1
PEI0
-
-
SMS
Bit 7:6 = PEI[3:2] External Interrupt EI1 Polarity
Option.
These bits are set and cleared by software. They
determine which event on EI1 causes the external interrupt according to Table 6.
Refer to the Pin Description Table at the beginning of this document for the list of pins connected to EI1.
Table 6. EI1 External Interrupt Polarity Options
MODE
PEI3
PEI2
Falling edge and low level
(Reset state)
0
0
Falling edge only
1
0
Rising edge only
0
1
Rising and falling edge
1
1
Note: Any modification of one of these two bits resets the interrupt request related to this interrupt
vector.
Bit 5 = MCO Main Clock Out
This bit is set and cleared by software. When set, it
enables the output of the Internal Clock on the
PC2 I/O port.
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0 - PC2 is a general purpose I/O port.
1 - MCO alternate function (fCPU is output on PC2
pin).
Bit 4:3 = PEI[1:0] External Interrupt EI0 Polarity
Option.
These bits are set and cleared by software. They
determine which event on EI0 causes the external interrupt according to Table 7.
Refer to the Pin Description Table at the beginning of this document for the list of pins connected to EI0.
Table 7. EI0 External Interrupt Polarity Options
MODE
PEI1
PEI0
Falling edge and low level
(Reset state)
0
0
Falling edge only
1
0
Rising edge only
0
1
Rising and falling edge
1
1
Note:
Any modification of one of these two bits resets the
interrupt request related to this interrupt vector.
Bit 1:2 = Unused, always read at 0.
Warning: Software must write 1 to these bits for
compatibility with future products.
Bit 0 = SMS Slow Mode Select
This bit is set and cleared by software.
0- Normal mode - fCPU = Oscillator frequency / 2
(Reset state)
1- Slow mode - fCPU = Oscillator frequency /32
ST72251
5 ON-CHIP PERIPHERALS
5.1 I/O PORTS
5.1.1 Introduction
The I/O ports offer different functional modes:
– transfer of data through digital inputs and outputs
and for specific pins:
– analog signal input (ADC)
– alternate signal input/output for the on-chip peripherals.
– external interrupt generation
An I/O port is composed of up to 8 pins. Each pin
can be programmed independently as digital input
(with or without interrupt generation) or digital output.
5.1.2 Functional Description
Each port is associated to 2 main registers:
– Data Register (DR)
– Data Direction Register (DDR)
and some of them to an optional register:
– Option Register (OR)
Each I/O pin may be programmed using the corresponding register bits in DDR and OR registers: bit
X corresponding to pin X of the port. The same correspondence is used for the DR register.
The following description takes into account the
OR register, for specific ports which do not provide
this register refer to the I/O Port Implementation
Section 5.1.3. The generic I/O block diagram is
shown on Figure 16.
5.1.2.1 Input Modes
The input configuration is selected by clearing the
corresponding DDR register bit.
In this case, reading the DR register returns the
digital value applied to the external I/O pin.
Different input modes can be selected by software
through the OR register.
Notes:
1. All the inputs are triggered by a Schmitt trigger.
2. When switching from input mode to output
mode, the DR register should be written first to
output the correct value as soon as the port is configured as an output.
Interrupt function
When an I/O is configured in Input with Interrupt,
an event on this I/O can generate an external Interrupt request to the CPU. The interrupt polarity is
given independently according to the description
mentioned in the Miscellaneous register or in the
interrupt register (where available).
Each pin can independently generate an Interrupt
request.
Each external interrupt vector is linked to a dedicated group of I/O port pins (see Interrupts section). If several input pins are configured as inputs
to the same interrupt vector, their signals are logically ANDed before entering the edge/level detection block. For this reason if one of the interrupt
pins is tied low, it masks the other ones.
5.1.2.2 Output Mode
The pin is configured in output mode by setting the
corresponding DDR register bit.
In this mode, writing “0” or “1” to the DR register
applies this digital value to the I/O pin through the
latch. Then reading the DR register returns the
previously stored value.
Note: In this mode, the interrupt function is disabled.
5.1.2.3 Digital Alternate Function
When an on-chip peripheral is configured to use a
pin, the alternate function is automatically selected. This alternate function takes priority over
standard I/O programming. When the signal is
coming from an on-chip peripheral, the I/O pin is
automatically configured in output mode (push-pull
or open drain according to the peripheral).
When the signal is going to an on-chip peripheral,
the I/O pin has to be configured in input mode. In
this case, the pin’s state is also digitally readable
by addressing the DR register.
Notes:
1. Input pull-up configuration can cause an unexpected value at the input of the alternate peripheral input.
2. When the on-chip peripheral uses a pin as input
and output, this pin must be configured as an input
(DDR = 0).
Warning: The alternate function must not be activated as long as the pin is configured as input with
interrupt, in order to avoid generating spurious interrupts.
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ST72251
I/O PORTS (Cont’d)
5.1.2.4 Analog Alternate Function
When the pin is used as an ADC input the I/O must
be configured as input, floating. The analog multiplexer (controlled by the ADC registers) switches
the analog voltage present on the selected pin to
the common analog rail which is connected to the
ADC input.
It is recommended not to change the voltage level
or loading on any port pin while conversion is in
progress. Furthermore it is recommended not to
have clocking pins located close to a selected analog pin.
Warning : The analog input voltage level must be
within the limits stated in the Absolute Maximum
Ratings.
5.1.3 I/O Port Implementation
The hardware implementation on each I/O port depends on the settings in the DDR and OR registers
and specific feature of the I/O port such as ADC Input (see Figure 16) or true open drain. Switching
these I/O ports from one state to another should
be done in a sequence that prevents unwanted
side effects. Recommended safe transitions are illustrated in Figure 15. Other transitions are potentially risky and should be avoided, since they are
likely to present unwanted side-effects such as
spurious interrupt generation.
Figure 15. Recommended I/O State Transition Diagram
INPUT
with interrupt
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INPUT
no interrupt
OUTPUT
OUTPUT
open-drain
push-pull
ST72251
I/O PORTS (Cont’d)
Figure 16. I/O Block Diagram
ALTERNATE ENABLE
ALTERNATE 1
M
OUTPUT
U
X
0
DATA BUS
COMMON ANALOG RAIL
DR
LATCH
VDD
P-BUFFER
(S EE TABLE BELOW)
ALTERNATE
ENABLE
PULL-UP
VDD
DIODE
(SEE TABLE BELOW)
PULL-UP
CONDITIO N
DDR
LATCH
PAD
OR
LATCH
ANALOG ENABLE
(ADC)
(SEE TABLE BELOW)
ANALOG
SWITCH
(SEE N OTE BELOW)
OR SEL
GND
DDR SEL
N-BUFFER
DR SEL
M
U
X
1
ALTERNATE
ENABLE
GND
0
ALTERNATE INPUT
CMOS
EXTERNAL
INTERRUPT
SOURCE (EIx)
POLARITY
SEL
FROM
OTHER
BITS
SCHMITT TRIGGER
Table 8. Port Mode Configuration
Configu ration Mode
Floating
Pull-up
Push-pull
True Open Drain
Open Drain (logic level)
Legend:
0present, not activated
1present and activated
Pull-up
0
1
0
P-buffer
0
0
1
not present
not present
0
0
VDD Diode
1
1
1
not present in OTP
and EPROM devices
1
Notes:
– No OR Register on some ports (see register map).
– ADC Switch on ports with analog alternate functions.
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ST72251
Table 9. Port Configuration
Pin
Name
Port
Input (DDR = 0)
Output (DDR = 1)
OR = 0
OR = 1
OR = 0
OR = 1
Port A
PA0:PA7
Floating*
Floating with Interrupt
True Open Drain,
High Sink Capability
Reserved
Port B
PB0:PB7
Floating*
Pull-up with Interrupt
Open Drain (Logic level)
Push-pull
Port C
PC0:PC5
Floating*
Pull-up with Interrupt
Open Drain (Logic level)
Push-pull
* Reset State
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ST72251
I/O PORTS (Cont’d)
5.1.4 Register Description
5.1.4.1 Data registers
Port A Data Register (PADR)
Port B Data Register (PBDR)
Port C Data Register (PCDR)
Read/Write
Reset Value: 0000 0000 (00h)
5.1.4.3 Option registers
Port A Option Register (PAOR)
Port B Option Register (PBOR)
Port C Option Register (PCOR)
Read/Write
Reset Value: 0000 0000 (00h) (no interrupt)
7
D7
D6
D5
D4
D3
D2
D1
0
7
D0
O7
Bit 7:0 = D7-D0 Data Register 8 bits.
The DR register has a specific behaviour according to the selected input/output configuration. Writing the DR register is always taken in account
even if the pin is configured as an input. Reading
the DR register returns either the DR register latch
content (pin configured as output) or the digital value applied to the I/O pin (pin configured as input).
5.1.4.2 Data direction registers
Port A Data Direction Register (PADDR)
Port B Data Direction Register (PBDDR)
Port C Data Direction Register (PCDDR)
Read/Write
Reset Value: 0000 0000 (00h) (input mode)
7
DD7
0
DD6
DD5
DD4
DD3
DD
2
DD1
DD0
0
O6
O5
O4
O3
O2
O1
O0
Bit 7:0 = O7-O0 Option Register 8 bits.
For specific I/O pins, this register is not implemented. In this case the DDR register is enough to select the I/O pin configuration.
The OR register allow to distinguish: in input mode
if the interrupt capability or the floating configuration is selected, in output mode if the push-pull or
open drain configuration is selected.
Each bit is set and cleared by software.
Input mode:
0: floating input
1: input interrupt with or without pull-up
Output mode (only for PB0:PB7, PC0:PC5):
0: output open drain (with P-Buffer inactivated)
1: output push-pull
Output mode (only for PA0:PA7):
0: output open drain
1: reserved
Bit 7:0 = DD7-DD0 Data Direction Register 8 bits.
The DDR register gives the input/output direction
configuration of the pins. Each bit is set and
cleared by software.
0: Input mode
1: Output mode
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ST72251
I/O PORTS (Cont’d)
Table 10. I/O Port Register Map and Reset Values
Address
(Hex.)
0000h
0001h
0002h
0004h
0005h
0006h
0008h
0009h
000Ah
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Register
Label
PCDR
Reset Value
PCDDR
Reset Value
PCOR
Reset Value
PBDR
Reset Value
PBDDR
Reset Value
PBOR
Reset Value
PADR
Reset Value
PADDR
Reset Value
PAOR
Reset Value
7
6
5
4
3
2
1
0
D7
0
D6
0
D5
0
D4
0
D37
0
D2
0
D1
0
D0
0
DD7
0
DD6
0
DD5
0
DD4
0
DD3
0
DD2
0
DD1
0
DD0
0
O7
0
O6
0
O5
0
O4
0
O3
0
O2
0
O1
0
O0
0
D7
0
D6
0
D5
0
D4
0
D37
0
D2
0
D1
0
D0
0
DD7
0
DD6
0
DD5
0
DD4
0
DD3
0
DD2
0
DD1
0
DD0
0
O7
0
O6
0
O5
0
O4
0
O3
0
O2
0
O1
0
O0
0
D7
0
D6
0
D5
0
D4
0
D37
0
D2
0
D1
0
D0
0
DD7
0
DD6
0
DD5
0
DD4
0
DD3
0
DD2
0
DD1
0
DD0
0
O7
0
O6
0
O5
0
O4
0
O3
0
O2
0
O1
0
O0
0
ST72251
5.2 WATCHDOG TIMER (WDG)
5.2.1 Introduction
The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to
abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter’s contents before the T6 bit becomes cleared.
5.2.2 Main Features
■ Programmable timer (64 increments of 12288
CPU cycles)
■ Programmable reset
■ Reset (if watchdog activated) after a HALT
instruction or when the T6 bit reaches zero
Figure 17. Watchdog Block Diagram
RESET
WATCHDOG CONTROL REGISTER (CR)
WDGA
T6
T5
T4
T3
T2
T1
T0
7-BIT DOWNCOUNTER
fCPU
CLOCK DIVIDER
÷12288
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ST72251
WATCHDOG TIMER (Cont’d)
5.2.3 Functional Description
The counter value stored in the CR register (bits
T6:T0), is decremented every 12,288 machine cycles, and the length of the timeout period can be
programmed by the user in 64 increments.
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T6:T0) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling low the reset pin for typically
500ns.
The application program must write in the CR register at regular intervals during normal operation to
prevent an MCU reset. The value to be stored in
the CR register must be between FFh and C0h
(see Table 11):
– The WDGA bit is set (watchdog enabled)
– The T6 bit is set to prevent generating an immediate reset
– The T5:T0 bits contain the number of increments
which represents the time delay before the
watchdog produces a reset.
5.2.4 Low Power Modes
Mode
WAIT
HALT
Description
No effect on Watchdog.
Immediate reset generation as soon as
the HALT instruction is executed if the
Watchdog is activated (WDGA bit is
set).
5.2.5 Interrupts
None.
5.2.6 Register Description
CONTROL REGISTER (CR)
Read/Write
Reset Value: 0111 1111 (7Fh)
7
WDGA
0
T6
T5
T4
T3
T2
T1
T0
Table 11. Watchdog Timing (fCPU = 8 MHz)
CR Register
initial value
WDG timeout period
(ms)
Max
FFh
98.304
Min
C0h
1.536
Notes: Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except
by a reset.
The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared).
If the watchdog is activated, the HALT instruction
will generate a Reset.
Bit 7 = WDGA Activation bit.
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB).
These bits contain the decremented value. A reset
is produced when it rolls over from 40h to 3Fh (T6
becomes cleared).
Table 12. Watchdog Timer Register Map and Reset Values
Address
(Hex.)
0024h
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Register
Label
7
6
5
4
3
2
1
0
WDGCR
WDGA
T6
T5
T4
T3
T2
T1
T0
Reset Value
0
1
1
1
1
1
1
1
ST72251
5.3 16-BIT TIMER
5.3.1 Introduction
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
It may be used for a variety of purposes, including
measuring the pulse lengths of up to two input signals (input capture) or generating up to two output
waveforms (output compare and PWM).
Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the CPU
clock prescaler.
Some ST7 devices have two on-chip 16-bit timers.
They are completely independent, and do not
share any resources. They are synchronized after
a MCU reset as long as the timer clock frequencies are not modified.
This description covers one or two 16-bit timers. In
ST7 devices with two timers, register names are
prefixed with TA (Timer A) or TB (Timer B).
5.3.2 Main Features
■ Programmable prescaler: fCPU divided by 2, 4 or 8.
■ Overflow status flag and maskable interrupt
■ External clock input (must be at least 4 times
slower than the CPU clock speed) with the choice
of active edge
■ Output compare functions with:
– 2 dedicated 16-bit registers
– 2 dedicated programmable signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
■ Input capture functions with:
– 2 dedicated 16-bit registers
– 2 dedicated active edge selection signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
■ Pulse Width Modulation mode (PWM)
■ One Pulse mode
■ 5 alternate functions on I/O ports (ICAP1, ICAP2,
OCMP1, OCMP2, EXTCLK)*
5.3.3 Functional Description
5.3.3.1 Counter
The main block of the Programmable Timer is a
16-bit free running upcounter and its associated
16-bit registers. The 16-bit registers are made up
of two 8-bit registers called high & low.
Counter Register (CR):
– Counter High Register (CHR) is the most significant byte (MS Byte).
– Counter Low Register (CLR) is the least significant byte (LS Byte).
Alternate Counter Register (ACR)
– Alternate Counter High Register (ACHR) is the
most significant byte (MS Byte).
– Alternate Counter Low Register (ACLR) is the
least significant byte (LS Byte).
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (Timer
overflow flag), located in the Status register (SR).
(See note at the end of paragraph titled 16-bit read
sequence).
Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
Both counters have a reset value of FFFCh (this is
the only value which is reloaded in the 16-bit timer). The reset value of both counters is also
FFFCh in One Pulse mode and PWM mode.
The timer clock depends on the clock control bits
of the CR2 register, as illustrated in Table 13. The
value in the counter register repeats every
131072, 262144 or 524288 CPU clock cycles depending on the CC[1:0] bits.
The timer frequency can be fCPU/2, fCPU /4, fCPU/8
or an external frequency.
The Block Diagram is shown in Figure 18.
*Note: Some timer pins may not be available (not
bonded) in some ST7 devices. Refer to the device
pin out description.
When reading an input signal on a non-bonded
pin, the value will always be ‘1’.
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ST72251
16-BIT TIMER (Cont’d)
Figure 18. Timer Block Diagram
ST7 INTERNAL BUS
fCPU
MCU-PERIPHERAL INTERFACE
8 low
8
8
8
low
low
8
high
8
8
high
EXEDG
8
low
high
8
high
8-bit
buffer
low
8 high
16
1/2
1/4
REGISTER
1/8
OUTPUT
COMPARE
REGISTER
2
OUTPUT
COMPARE
REGISTER
1
COUNTER
ALTERNATE
COUNTER
REGISTER
EXTCLK
pin
INPUT
CAPTURE
REGISTER
1
INPUT
CAPTURE
REGISTER
2
16
16
16
CC[1:0]
TIMER INTERNAL BUS
16 16
OVERFLOW
DETECT
CIRCUIT
OUTPUT COMPARE
CIRCUIT
6
ICF1 OCF1 TOF ICF2 OCF2
0
0
EDGE DETECT
CIRCUIT1
ICAP1
pin
EDGE DETECT
CIRCUIT2
ICAP2
pin
LATCH1
OCMP1
pin
LATCH2
OCMP2
pin
0
(Status Register) SR
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
(Control Register 1) CR1
OC1E OC2E OPM PWM
CC1
CC0 IEDG2 EXEDG
(Control Register 2) CR2
(See note)
TIMER INTERRUPT
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Note: If IC, OC and TO interrupt requests have separate vectors
then the last OR is not present (See device Interrupt Vector Table)
ST72251
16-BIT TIMER (Cont’d)
16-bit Read Sequence: (from either the Counter
Register or the Alternate Counter Register).
Beginning of the sequence
At t0
Read
MS Byte
LS Byte
is buffered
Other
instructions
Read
At t0 +∆t LS Byte
Returns the buffered
LS Byte value at t0
Sequence completed
The user must read the MS Byte first, then the LS
Byte value is buffered automatically.
This buffered value remains unchanged until the
16-bit read sequence is completed, even if the
user reads the MS Byte several times.
After a complete reading sequence, if only the
CLR register or ACLR register are read, they return the LS Byte of the count value at the time of
the read.
Whatever the timer mode used (input capture, output compare, One Pulse mode or PWM mode) an
overflow occurs when the counter rolls over from
FFFFh to 0000h then:
– The TOF bit of the SR register is set.
– A timer interrupt is generated if:
– TOIE bit of the CR1 register is set and
– I bit of the CC register is cleared.
If one of these conditions is false, the interrupt remains pending to be issued as soon as they are
both true.
Clearing the overflow interrupt request is done in
two steps:
1. Reading the SR register while the TOF bit is set.
2. An access (read or write) to the CLR register.
Note: The TOF bit is not cleared by accessing the
ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that
it allows simultaneous use of the overflow function
and reading the free running counter at random
times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously.
The timer is not affected by WAIT mode.
In HALT mode, the counter stops counting until the
mode is exited. Counting then resumes from the
previous count (MCU awakened by an interrupt) or
from the reset count (MCU awakened by a Reset).
5.3.3.2 External Clock
The external clock (where available) is selected if
CC0=1 and CC1=1 in the CR2 register.
The status of the EXEDG bit in the CR2 register
determines the type of level transition on the external clock pin EXTCLK that will trigger the free running counter.
The counter is synchronised with the falling edge
of the internal CPU clock.
A minimum of four falling edges of the CPU clock
must occur between two consecutive active edges
of the external clock; thus the external clock frequency must be less than a quarter of the CPU
clock frequency.
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ST72251
16-BIT TIMER (Cont’d)
Figure 19. Counter Timing Diagram, internal clock divided by 2
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFD FFFE FFFF 0000
COUNTER REGISTER
0001
0002
0003
TIMER OVERFLOW FLAG (TOF)
Figure 20. Counter Timing Diagram, internal clock divided by 4
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
FFFC
FFFD
0000
0001
TIMER OVERFLOW FLAG (TOF)
Figure 21. Counter Timing Diagram, internal clock divided by 8
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
FFFC
FFFD
0000
TIMER OVERFLOW FLAG (TOF)
Note: The MCU is in reset state when the internal reset signal is high. When it is low, the MCU is running.
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ST72251
16-BIT TIMER (Cont’d)
5.3.3.3 Input Capture
In this section, the index, i, may be 1 or 2 because
there are 2 input capture functions in the 16-bit
timer.
The two input capture 16-bit registers (IC1R and
IC2R) are used to latch the value of the free running counter after a transition is detected by the
ICAP i pin (see figure 5).
ICiR
MS Byte
ICiHR
LS Byte
ICiLR
The ICiR register is a read-only register.
The active transition is software programmable
through the IEDGi bit of Control Registers (CRi).
Timing resolution is one count of the free running
counter: (fCPU/CC[1:0]).
Procedure:
To use the input capture function, select the following in the CR2 register:
– Select the timer clock (CC[1:0]) (see Table 13).
– Select the edge of the active transition on the
ICAP2 pin with the IEDG2 bit (the ICAP2 pin
must be configured as a floating input).
And select the following in the CR1 register:
– Set the ICIE bit to generate an interrupt after an
input capture coming from either the ICAP1 pin
or the ICAP2 pin
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1pin must
be configured as a floating input).
When an input capture occurs:
– The ICFi bit is set.
– The ICiR register contains the value of the free
running counter on the active transition on the
ICAPi pin (see Figure 23).
– A timer interrupt is generated if the ICIE bit is set
and the I bit is cleared in the CC register. Otherwise, the interrupt remains pending until both
conditions become true.
Clearing the Input Capture interrupt request (i.e.
clearing the ICFi bit) is done in two steps:
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
Notes:
1. After reading the ICiHR register, the transfer of
input capture data is inhibited and ICFi will
never be set until the ICiLR register is also
read.
2. The ICiR register contains the free running
counter value which corresponds to the most
recent input capture.
3. The 2 input capture functions can be used
together even if the timer also uses the 2 output
compare functions.
4. In One Pulse mode and PWM mode only the
input capture 2 function can be used.
5. The alternate inputs (ICAP1 & ICAP2) are
always directly connected to the timer. So any
transitions on these pins activate the input capture function.
Moreover if one of the ICAPi pin is configured
as an input and the second one as an output,
an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set.
This can be avoided if the input capture function i is disabled by reading the ICiHR (see note
1).
6. The TOF bit can be used with an interrupt in
order to measure events that exceed the timer
range (FFFFh).
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ST72251
16-BIT TIMER (Cont’d)
Figure 22. Input Capture Block Diagram
ICAP1
pin
ICAP2
pin
(Control Register 1) CR1
EDGE DETECT
CIRCUIT2
EDGE DETECT
CIRCUIT1
ICIE
IEDG1
(Status Register) SR
IC2R Register
IC1R Register
ICF1
ICF2
0
16-BIT FREE RUNNING
CC1
CC0
COUNTER
Figure 23. Input Capture Timing Diagram
TIMER CLOCK
FF01
FF02
FF03
ICAPi PIN
ICAPi FLAG
ICAPi REGISTER
Note: Active edge is rising edge.
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0
(Control Register 2) CR2
16-BIT
COUNTER REGISTER
0
FF03
IEDG2
ST72251
16-BIT TIMER (Cont’d)
5.3.3.4 Output Compare
In this section, the index, i, may be 1 or 2 because
there are 2 output compare functions in the 16-bit
timer.
This function can be used to control an output
waveform or indicate when a period of time has
elapsed.
When a match is found between the Output Compare register and the free running counter, the output compare function:
– Assigns pins with a programmable value if the
OCIE bit is set
– Sets a flag in the status register
– Generates an interrupt if enabled
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the counter
register each timer clock cycle.
OCiR
MS Byte
OCiHR
LS Byte
OCiLR
These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OCiR value to 8000h.
Timing resolution is one count of the free running
counter: (fCPU/CC[1:0] ).
Procedure:
To use the output compare function, select the following in the CR2 register:
– Set the OCiE bit if an output is needed then the
OCMPi pin is dedicated to the output compare i
signal.
– Select the timer clock (CC[1:0]) (see Table 13).
And select the following in the CR1 register:
– Select the OLVL i bit to applied to the OCMPi pins
after the match occurs.
– Set the OCIE bit to generate an interrupt if it is
needed.
When a match is found between OCRi register
and CR register:
– OCFi bit is set.
– The OCMPi pin takes OLVLi bit value (OCMPi
pin latch is forced low during reset).
– A timer interrupt is generated if the OCIE bit is
set in the CR1 register and the I bit is cleared in
the CC register (CC).
The OCiR register value required for a specific timing application can be calculated using the following formula:
∆ OCiR =
∆t * fCPU
PRESC
Where:
∆t
= Output compare period (in seconds)
fCPU
= CPU clock frequency (in hertz)
PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 13)
If the timer clock is an external clock, the formula
is:
∆ OCiR = ∆t * fEXT
Where:
∆t
= Output compare period (in seconds)
fEXT
= External timer clock frequency (in hertz)
Clearing the output compare interrupt request (i.e.
clearing the OCFi bit) is done by:
1. Reading the SR register while the OCFi bit is
set.
2. An access (read or write) to the OCiLR register.
The following procedure is recommended to prevent the OCFi bit from being set between the time
it is read and the write to the OCiR register:
– Write to the OCiHR register (further compares
are inhibited).
– Read the SR register (first step of the clearance
of the OCFi bit, which may be already set).
– Write to the OCiLR register (enables the output
compare function and clears the OCFi bit).
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ST72251
16-BIT TIMER (Cont’d)
Notes:
1. After a processor write cycle to the OCi HR register, the output compare function is inhibited
until the OCiLR register is also written.
2. If the OCiE bit is not set, the OCMPi pin is a
general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
3. When the timer clock is fCPU/2, OCFi and
OCMPi are set while the counter value equals
the OCiR register value (see Figure 25, on
page 39). This behaviour is the same in OPM
or PWM mode.
When the timer clock is fCPU/4, fCPU/8 or in
external clock mode, OCFi and OCMPi are set
while the counter value equals the OCiR register value plus 1 (see Figure 26, on page 39).
4. The output compare functions can be used both
for generating external events on the OCMPi
pins even if the input capture mode is also
used.
5. The value in the 16-bit OCiR register and the
OLVi bit should be changed after each successful comparison in order to control an output
waveform or establish a new elapsed timeout.
Forced Compare Output capability
When the FOLVi bit is set by software, the OLVLi
bit is copied to the OCMPi pin. The OLVi bit has to
be toggled in order to toggle the OCMPi pin when
it is enabled (OCiE bit=1). The OCFi bit is then not
set by hardware, and thus no interrupt request is
generated.
FOLVLi bits have no effect in either One-Pulse
mode or PWM mode.
Figure 24. Output Compare Block Diagram
16 BIT FREE RUNNING
COUNTER
OC1E OC2E
CC1
CC0
(Control Register 2) CR2
16-bit
(Control Register 1) CR1
OUTPUT COMPARE
CIRCUIT
16-bit
OCIE
FOLV2 FOLV1 OLVL2
OLVL1
16-bit
Latch
2
OC1R Register
OCF1
OCF2
0
0
0
OC2R Register
(Status Register) SR
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Latch
1
OCMP1
Pin
OCMP2
Pin
ST72251
16-BIT TIMER (Cont’d)
Figure 25. Output Compare Timing Diagram, fTIMER =fCPU/2
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER REGISTER
2ECF 2ED0
2ED1 2ED2 2ED3 2ED4
OUTPUT COMPARE REGISTER i (OCR i)
2ED3
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
Figure 26. Output Compare Timing Diagram, fTIMER =fCPU/4
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER REGISTER
OUTPUT COMPARE REGISTER i (OCR i)
2ECF 2ED0
2ED1 2ED2 2ED3 2ED4
2ED3
COMPARE REGISTER i LATCH
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
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ST72251
16-BIT TIMER (Cont’d)
5.3.3.5 One Pulse Mode
One Pulse mode enables the generation of a
pulse when an external event occurs. This mode is
selected via the OPM bit in the CR2 register.
The One Pulse mode uses the Input Capture1
function and the Output Compare1 function.
Procedure:
To use One Pulse mode:
1. Load the OC1R register with the value corresponding to the length of the pulse (see the formula in the opposite column).
2. Select the following in the CR1 register:
– Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the pulse.
– Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the pulse.
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1 pin
must be configured as floating input).
3. Select the following in the CR2 register:
– Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1 function.
– Set the OPM bit.
– Select the timer clock CC[1:0] (see Table 13).
One Pulse mode cycle
When
event occurs
on ICAP1
OCMP1 = OLVL2
Counter is reset
to FFFCh
ICF1 bit is set
When
Counter
= OC1R
OCMP1 = OLVL1
Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and the OLVL2 bit is
loaded on the OCMP1 pin, the ICF1 bit is set and
the value FFFDh is loaded in the IC1R register.
Because the ICF1 bit is set when an active edge
occurs, an interrupt can be generated if the ICIE
bit is set.
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Clearing the Input Capture interrupt request (i.e.
clearing the ICFi bit) is done in two steps:
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
The OC1R register value required for a specific
timing application can be calculated using the following formula:
OCiR Value =
t * fCPU
-5
PRESC
Where:
t
= Pulse period (in seconds)
fCPU = CPU clock frequency (in hertz)
PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits, see Table 13)
If the timer clock is an external clock the formula is:
OCiR = t * f EXT -5
Where:
t
= Pulse period (in seconds)
fEXT
= External timer clock frequency (in hertz)
When the value of the counter is equal to the value
of the contents of the OC1R register, the OLVL1
bit is output on the OCMP1 pin (see Figure 27).
Notes:
1. The OCF1 bit cannot be set by hardware in
One Pulse mode but the OCF2 bit can generate
an Output Compare interrupt.
2. When the Pulse Width Modulation (PWM) and
One Pulse mode (OPM) bits are both set, the
PWM mode is the only active one.
3. If OLVL1=OLVL2 a continuous signal will be
seen on the OCMP1 pin.
4. The ICAP1 pin can not be used to perform input
capture. The ICAP2 pin can be used to perform
input capture (ICF2 can be set and IC2R can be
loaded) but the user must take care that the
counter is reset each time a valid edge occurs
on the ICAP1 pin and ICF1 can also generates
interrupt if ICIE is set.
5. When One Pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and
OCF2 can be used to indicate that a period of
time has elapsed but cannot generate an output
waveform because the OLVL2 level is dedicated to One Pulse mode.
ST72251
16-BIT TIMER (Cont’d)
Figure 27. One Pulse Mode Timing Example
COUNTER
FFFC FFFD FFFE
2ED0
2ED1 2ED2
FFFC FFFD
2ED3
ICAP1
OLVL2
OCMP1
OLVL1
OLVL2
compare1
Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
Figure 28. Pulse Width Modulation Mode Timing Example
COUNTER 34E2 FFFC FFFD FFFE
2ED0 2ED1 2ED2
OLVL2
OCMP1
compare2
OLVL1
compare1
34E2
FFFC
OLVL2
compare2
Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1
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ST72251
16-BIT TIMER (Cont’d)
5.3.3.6 Pulse Width Modulation Mode
Pulse Width Modulation (PWM) mode enables the
generation of a signal with a frequency and pulse
length determined by the value of the OC1R and
OC2R registers.
The Pulse Width Modulation mode uses the complete Output Compare 1 function plus the OC2R
register, and so these functions cannot be used
when the PWM mode is activated.
Procedure
To use Pulse Width Modulation mode:
1. Load the OC2R register with the value corresponding to the period of the signal using the
formula in the opposite column.
2. Load the OC1R register with the value corresponding to the period of the pulse if OLVL1=0
and OLVL2=1, using the formula in the opposite column.
3. Select the following in the CR1 register:
– Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a successful
comparison with OC1R register.
– Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a successful
comparison with OC2R register.
4. Select the following in the CR2 register:
– Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function.
– Set the PWM bit.
– Select the timer clock (CC[1:0]) (see Table
13).
If OLVL1=1 and OLVL2=0, the length of the positive pulse is the difference between the OC2R and
OC1R registers.
If OLVL1=OLVL2 a continuous signal will be seen
on the OCMP1 pin.
Pulse Width Modulation cycle
When
Counter
= OC1R
When
Counter
= OC2R
OCMP1 = OLVL1
OCMP1 = OLVL2
Counter is reset
to FFFCh
ICF1 bit is set
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The OCiR register value required for a specific timing application can be calculated using the following formula:
OCiR Value =
t * fCPU
-5
PRESC
Where:
t
= Signal or pulse period (in seconds)
fCPU = CPU clock frequency (in hertz)
PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 13)
If the timer clock is an external clock the formula is:
OCiR = t * f EXT -5
Where:
t
= Signal or pulse period (in seconds)
= External timer clock frequency (in hertz)
fEXT
The Output Compare 2 event causes the counter
to be initialized to FFFCh (See Figure 28)
Notes:
1. After a write instruction to the OCiHR register,
the output compare function is inhibited until the
OCiLR register is also written.
2. The OCF1 and OCF2 bits cannot be set by
hardware in PWM mode, therefore the Output
Compare interrupt is inhibited.
3. The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce a
timer interrupt if the ICIE bit is set and the I bit is
cleared.
4. In PWM mode the ICAP1 pin can not be used
to perform input capture because it is disconnected from the timer. The ICAP2 pin can be
used to perform input capture (ICF2 can be set
and IC2R can be loaded) but the user must
take care that the counter is reset after each
period and ICF1 can also generate an interrupt
if ICIE is set.
5. When the Pulse Width Modulation (PWM) and
One Pulse mode (OPM) bits are both set, the
PWM mode is the only active one.
ST72251
16-BIT TIMER (Cont’d)
5.3.4 Low Power Modes
Mode
WAIT
HALT
Description
No effect on 16-bit Timer.
Timer interrupts cause the device to exit from WAIT mode.
16-bit Timer registers are frozen.
In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous
count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter
reset value when the MCU is woken up by a RESET.
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequently, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and
the counter value present when exiting from HALT mode is captured into the ICiR register.
5.3.5 Interrupts
Event
Flag
Interrupt Event
Input Capture 1 event/Counter reset in PWM mode
Input Capture 2 event
Output Compare 1 event (not available in PWM mode)
Output Compare 2 event (not available in PWM mode)
Timer Overflow event
ICF1
ICF2
OCF1
OCF2
TOF
Enable
Control
Bit
ICIE
OCIE
TOIE
Exit
from
Wait
Yes
Yes
Yes
Yes
Yes
Exit
from
Halt
No
No
No
No
No
Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chapter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).
5.3.6 Summary of Timer modes
MODES
Input Capture (1 and/or 2)
Output Compare (1 and/or 2)
One Pulse mode
PWM Mode
1)
2)
3)
Input Capture 1
Yes
Yes
No
No
AVAILABLE RESOURCES
Input Capture 2
Output Compare 1 Output Compare 2
Yes
Yes
Yes
Yes
Yes
Yes
Not Recommended 1)
Not Recommended 3)
No
No
Partially 2)
No
See note 4 in Section 5.3.3.5 One Pulse Mode
See note 5 in Section 5.3.3.5 One Pulse Mode
See note 4 in Section 5.3.3.6 Pulse Width Modulation Mode
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ST72251
16-BIT TIMER (Cont’d)
5.3.7 Register Description
Each Timer is associated with three control and
status registers, and with six pairs of data registers
(16-bit values) relating to the two input captures,
the two output compares, the counter and the alternate counter.
CONTROL REGISTER 1 (CR1)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
Bit 4 = FOLV2 Forced Output Compare 2.
This bit is set and cleared by software.
0: No effect on the OCMP2 pin.
1: Forces the OLVL2 bit to be copied to the
OCMP2 pin, if the OC2E bit is set and even if
there is no successful comparison.
Bit 3 = FOLV1 Forced Output Compare 1.
This bit is set and cleared by software.
0: No effect on the OCMP1 pin.
1: Forces OLVL1 to be copied to the OCMP1 pin, if
the OC1E bit is set and even if there is no successful comparison.
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 7 = ICIE Input Capture Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
ICF1 or ICF2 bit of the SR register is set.
Bit 6 = OCIE Output Compare Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
OCF1 or OCF2 bit of the SR register is set.
Bit 5 = TOIE Timer Overflow Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF
bit of the SR register is set.
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Bit 2 = OLVL2 Output Level 2.
This bit is copied to the OCMP2 pin whenever a
successful comparison occurs with the OC2R register and OCxE is set in the CR2 register. This value is copied to the OCMP1 pin in One Pulse mode
and Pulse Width Modulation mode.
Bit 1 = IEDG1 Input Edge 1.
This bit determines which type of level transition
on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 0 = OLVL1 Output Level 1.
The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs with the
OC1R register and the OC1E bit is set in the CR2
register.
ST72251
16-BIT TIMER (Cont’d)
CONTROL REGISTER 2 (CR2)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Bit 7 = OC1E Output Compare 1 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP1 pin (OLV1 in Output Compare mode, both OLV1 and OLV2 in PWM and
one-pulse mode). Whatever the value of the OC1E
bit, the internal Output Compare 1 function of the
timer remains active.
0: OCMP1 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP1 pin alternate function enabled.
Bit 6 = OC2E Output Compare 2 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP2 pin (OLV2 in Output Compare mode). Whatever the value of the OC2E bit,
the internal Output Compare 2 function of the timer
remains active.
0: OCMP2 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP2 pin alternate function enabled.
Bit 5 = OPM One Pulse mode.
0: One Pulse mode is not active.
1: One Pulse mode is active, the ICAP1 pin can be
used to trigger one pulse on the OCMP1 pin; the
active transition is given by the IEDG1 bit. The
length of the generated pulse depends on the
contents of the OC1R register.
Bit 4 = PWM Pulse Width Modulation.
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a
programmable cyclic signal; the length of the
pulse depends on the value of OC1R register;
the period depends on the value of OC2R register.
Bits 3:2 = CC[1:0] Clock Control.
The timer clock mode depends on these bits:
Table 13. Clock Control Bits
Timer Clock
fCPU / 4
fCPU / 2
fCPU / 8
External Clock (where
available)
CC1
0
0
1
CC0
0
1
0
1
1
Note: If the external clock pin is not available, programming the external clock configuration stops
the counter.
Bit 1 = IEDG2 Input Edge 2.
This bit determines which type of level transition
on the ICAP2 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 0 = EXEDG External Clock Edge.
This bit determines which type of level transition
on the external clock pin (EXTCLK) will trigger the
counter register.
0: A falling edge triggers the counter register.
1: A rising edge triggers the counter register.
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ST72251
16-BIT TIMER (Cont’d)
STATUS REGISTER (SR)
Read Only
Reset Value: 0000 0000 (00h)
The three least significant bits are not used.
7
ICF1
0
OCF1
TOF
ICF2
OCF2
0
0
0
Bit 7 = ICF1 Input Capture Flag 1.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP1 pin
or the counter has reached the OC2R value in
PWM mode. To clear this bit, first read the SR
register, then read or write the low byte of the
IC1R (IC1LR) register.
Bit 6 = OCF1 Output Compare Flag 1.
0: No match (reset value).
1: The content of the free running counter matches
the content of the OC1R register. To clear this
bit, first read the SR register, then read or write
the low byte of the OC1R (OC1LR) register.
Bit 5 = TOF Timer Overflow Flag.
0: No timer overflow (reset value).
1: The free running counter has rolled over from
FFFFh to 0000h. To clear this bit, first read the
SR register, then read or write the low byte of
the CR (CLR) register.
Note: Reading or writing the ACLR register does
not clear TOF.
Bit 4 = ICF2 Input Capture Flag 2.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP2
pin. To clear this bit, first read the SR register,
then read or write the low byte of the IC2R
(IC2LR) register.
Bit 3 = OCF2 Output Compare Flag 2.
0: No match (reset value).
1: The content of the free running counter matches
the content of the OC2R register. To clear this
bit, first read the SR register, then read or write
the low byte of the OC2R (OC2LR) register.
Bit 2-0 = Reserved, forced by hardware to 0.
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INPUT CAPTURE 1 HIGH REGISTER (IC1HR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
input capture 1 event).
7
0
MSB
LSB
INPUT CAPTURE 1 LOW REGISTER (IC1LR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the input capture 1 event).
7
0
MSB
LSB
OUTPUT COMPARE 1 HIGH REGISTER
(OC1HR)
Read/Write
Reset Value: 1000 0000 (80h)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
7
0
MSB
LSB
OUTPUT COMPARE 1 LOW REGISTER
(OC1LR)
Read/Write
Reset Value: 0000 0000 (00h)
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
7
0
MSB
LSB
ST72251
16-BIT TIMER (Cont’d)
OUTPUT COMPARE 2 HIGH REGISTER
(OC2HR)
Read/Write
Reset Value: 1000 0000 (80h)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
ALTERNATE COUNTER HIGH REGISTER
(ACHR)
Read Only
Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part
of the counter value.
7
0
7
0
MSB
LSB
MSB
LSB
OUTPUT COMPARE 2 LOW REGISTER
(OC2LR)
Read/Write
Reset Value: 0000 0000 (00h)
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
7
0
MSB
LSB
COUNTER HIGH REGISTER (CHR)
Read Only
Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part
of the counter value.
7
0
MSB
LSB
COUNTER LOW REGISTER (CLR)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after accessing
the SR register clears the TOF bit.
7
0
MSB
LSB
ALTERNATE COUNTER LOW REGISTER
(ACLR)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after an access
to SR register does not clear the TOF bit in SR
register.
7
0
MSB
LSB
INPUT CAPTURE 2 HIGH REGISTER (IC2HR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
Input Capture 2 event).
7
0
MSB
LSB
INPUT CAPTURE 2 LOW REGISTER (IC2LR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the Input Capture 2 event).
7
0
MSB
LSB
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46
ST72251
16-BIT TIMER (Cont’d)
Table 14. 16-Bit Timer Register Map and Reset Values
Address
(Hex.)
Register
Name
TimerA: 32 CR1
7
6
5
4
3
2
1
0
ICIE
OCIE
TOIE
FOLV2
FOLV1
OLVL2
IEDG1
OLVL1
TimerB: 42 Reset Value
TimerA: 31 CR2
0
OC1E
0
OC2E
0
OPM
0
PWM
0
CC1
0
CC0
0
IEDG2
0
EXEDG
TimerB: 41 Reset Value
TimerA: 33 SR
0
ICF1
0
OCF1
0
TOF
0
ICF2
0
OCF2
0
-
0
-
0
-
0
0
0
0
0
0
0
0
TimerB: 43 Reset Value
TimerA: 34 IC1HR
TimerB: 44 Reset Value
TimerA: 35 IC1LR
TimerB: 45 Reset Value
TimerA: 36 OC1HR
TimerB: 46 Reset Value
TimerA: 37 OC1LR
TimerB: 47 Reset Value
TimerA: 3E OC2HR
TimerB: 4E Reset Value
TimerA: 3F OC2LR
TimerB: 4F Reset Value
TimerA: 38 CHR
TimerB: 48 Reset Value
TimerA: 39 CLR
TimerB: 49 Reset Value
TimerA: 3A ACHR
TimerB: 4A Reset Value
TimerA: 3B ACLR
TimerB: 4B Reset Value
TimerA: 3C IC2HR
TimerB: 4C Reset Value
TimerA: 3D IC2LR
TimerB: 4D Reset Value
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47
MSB
-
-
-
-
-
-
-
LSB
-
MSB
-
-
-
-
-
-
-
LSB
-
MSB
1
0
0
0
0
0
0
LSB
0
MSB
0
0
0
0
0
0
0
LSB
0
MSB
1
0
0
0
0
0
0
LSB
0
MSB
0
0
0
0
0
0
0
LSB
0
MSB
1
1
1
1
1
1
1
LSB
1
MSB
1
1
1
1
1
1
0
LSB
0
MSB
1
1
1
1
1
1
1
LSB
1
MSB
1
1
1
1
1
1
0
LSB
0
MSB
-
-
-
-
-
-
-
LSB
-
MSB
-
-
-
-
-
-
-
LSB
-
ST72251
5.4 I2C BUS INTERFACE (I2C)
5.4.1 Introduction
The I2C Bus Interface serves as an interface between the microcontroller and the serial I2C bus. It
provides both multimaster and slave functions,
and controls all I 2C bus-specific sequencing, protocol, arbitration and timing. It supports fast I2C
mode (400kHz).
5.4.2 Main Features
2
■ Parallel-bus/I C protocol converter
■ Multi-master capability
■ 7-bit/10-bit Addressing
■ Transmitter/Receiver flag
■ End-of-byte transmission flag
■ Transfer problem detection
I2C Master Features:
■ Clock generation
2
■ I C bus busy flag
■ Arbitration Lost Flag
■ End of byte transmission flag
■ Transmitter/Receiver Flag
■ Start bit detection flag
■ Start and Stop generation
I2C Slave Features:
■ Stop bit detection
2
■ I C bus busy flag
■ Detection of misplaced start or stop condition
2
■ Programmable I C Address detection
■ Transfer problem detection
■ End-of-byte transmission flag
■ Transmitter/Receiver flag
5.4.3 General Description
In addition to receiving and transmitting data, this
interface converts it from serial to parallel format
and vice versa, using either an interrupt or polled
handshake. The interrupts are enabled or disabled
by software. The interface is connected to the I2C
bus by a data pin (SDAI) and by a clock pin (SCLI).
It can be connected both with a standard I2C bus
and a Fast I2C bus. This selection is made by software.
Mode Selection
The interface can operate in the four following
modes:
– Slave transmitter/receiver
– Master transmitter/receiver
By default, it operates in slave mode.
The interface automatically switches from slave to
master after it generates a START condition and
from master to slave in case of arbitration loss or a
STOP generation, allowing then Multi-Master capability.
Communication Flow
In Master mode, it initiates a data transfer and
generates the clock signal. A serial data transfer
always begins with a start condition and ends with
a stop condition. Both start and stop conditions are
generated in master mode by software.
In Slave mode, the interface is capable of recognising its own address (7 or 10-bit), and the General Call address. The General Call address detection may be enabled or disabled by software.
Data and addresses are transferred as 8-bit bytes,
MSB first. The first byte(s) following the start condition contain the address (one in 7-bit mode, two
in 10-bit mode). The address is always transmitted
in Master mode.
A 9th clock pulse follows the 8 clock cycles of a
byte transfer, during which the receiver must send
an acknowledge bit to the transmitter. Refer to Figure 29.
Figure 29. I2C BUS Protocol
SDA
ACK
MSB
SCL
1
START
CONDITION
2
8
9
STOP
CONDITION
VR02119B
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ST72251
I2C BUS INTERFACE (Cont’d)
Acknowledge may be enabled and disabled by
software.
The I2C interface address and/or general call address can be selected by software.
The speed of the I2C interface may be selected
between Standard (0-100KHz) and Fast I2C (100400KHz).
SDA/SCL Line Control
Transmitter mode: the interface holds the clock
line low before transmission to wait for the microcontroller to write the byte in the Data Register.
Receiver mode: the interface holds the clock line
low after reception to wait for the microcontroller to
read the byte in the Data Register.
The SCL frequency (Fscl) is controlled by a programmable clock divider which depends on the
I2C bus mode.
When the I2C cell is enabled, the SDA and SCL
ports must be configured as floating inputs. In this
case, the value of the external pull-up resistor
used depends on the application.
When the I2C cell is disabled, the SDA and SCL
ports revert to being standard I/ O port pins.
Figure 30. I2C Interface Block Diagram
DATA REGISTER (DR)
SDA or SDAI
DATA CONTROL
DATA SHIFT REGISTER
COMPARATOR
OWN ADDRESS REGISTE R 1 (OAR1)
OWN ADDRESS REGISTER 2 (OAR2)
SCL or SCLI
CLOCK CONTROL
CLOCK CONTROL REGISTER (CCR)
CONTROL REGISTER (CR)
STATUS REGISTER 1 (SR1)
CONTROL LOGIC
STATUS REGISTER 2 (SR2)
INTE RRUPT
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ST72251
I2C BUS INTERFACE (Cont’d)
5.4.4 Functional Description
Refer to the CR, SR1 and SR2 registers in Section
5.4.7. for the bit definitions.
By default the I2C interface operates in Slave
mode (M/SL bit is cleared) except when it initiates
a transmit or receive sequence.
First the interface frequency must be configured
using the FRi bits in the OAR2 register.
5.4.4.1 Slave Mode
As soon as a start condition is detected, the
address is received from the SDA line and sent to
the shift register; then it is compared with the
address of the interface or the General Call
address (if selected by software).
Note: In 10-bit addressing mode, the comparision
includes the header sequence (11110xx0) and the
two most significant bits of the address.
Header matched (10-bit mode only): the interface
generates an acknowledge pulse if the ACK bit is
set.
Address not matched: the interface ignores it
and waits for another Start condition.
Address matched: the interface generates in sequence:
– Acknowledge pulse if the ACK bit is set.
– EVF and ADSL bits are set with an interrupt if the
ITE bit is set.
Then the interface waits for a read of the SR1 register, holding the SCL line low (see Figure 31
Transfer sequencing EV1).
Next, in 7-bit mode read the DR register to determine from the least significant bit (Data Direction
Bit) if the slave must enter Receiver or Transmitter
mode.
In 10-bit mode, after receiving the address sequence the slave is always in receive mode. It will
enter transmit mode on receiving a repeated Start
condition followed by the header sequence with
matching address bits and the least significant bit
set (11110xx1) .
Slave Receiver
Following the address reception and after SR1
register has been read, the slave receives bytes
from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence:
– Acknowledge pulse if the ACK bit is set
– EVF and BTF bits are set with an interrupt if the
ITE bit is set.
Then the interface waits for a read of the SR1 register followed by a read of the DR register, holding
the SCL line low (see Figure 31 Transfer sequencing EV2).
Slave Transmitter
Following the address reception and after SR1
register has been read, the slave sends bytes from
the DR register to the SDA line via the internal shift
register.
The slave waits for a read of the SR1 register followed by a write in the DR register, holding the
SCL line low (see Figure 31 Transfer sequencing
EV3).
When the acknowledge pulse is received:
– The EVF and BTF bits are set by hardware with
an interrupt if the ITE bit is set.
Closing slave communication
After the last data byte is transferred a Stop Condition is generated by the master. The interface
detects this condition and sets:
– EVF and STOPF bits with an interrupt if the ITE
bit is set.
Then the interface waits for a read of the SR2 register (see Figure 31 Transfer sequencing EV4).
Error Cases
– BERR: Detection of a Stop or a Start condition
during a byte transfer. In this case, the EVF and
the BERR bits are set with an interrupt if the ITE
bit is set.
If it is a Stop then the interface discards the data,
released the lines and waits for another Start
condition.
If it is a Start then the interface discards the data
and waits for the next slave address on the bus.
– AF: Detection of a non-acknowledge bit. In this
case, the EVF and AF bits are set with an interrupt if the ITE bit is set.
Note: In both cases, SCL line is not held low; however, SDA line can remain low due to possible «0»
bits transmitted last. It is then necessary to release
both lines by software.
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50
ST72251
I2C BUS INTERFACE (Cont’d)
How to release the SDA / SCL lines
Set and subsequently clear the STOP bit while
BTF is set. The SDA/SCL lines are released after
the transfer of the current byte.
5.4.4.2 Master Mode
To switch from default Slave mode to Master
mode a Start condition generation is needed.
Start condition
Setting the START bit while the BUSY bit is
cleared causes the interface to switch to Master
mode (M/SL bit set) and generates a Start condition.
Once the Start condition is sent:
– The EVF and SB bits are set by hardware with
an interrupt if the ITE bit is set.
Then the master waits for a read of the SR1 register followed by a write in the DR register with the
Slave address, holding the SCL line low (see
Figure 31 Transfer sequencing EV5).
Slave address transmission
Then the slave address is sent to the SDA line via
the internal shift register.
In 7-bit addressing mode, one address byte is
sent.
In 10-bit addressing mode, sending the first byte
including the header sequence causes the following event:
– The EVF bit is set by hardware with interrupt
generation if the ITE bit is set.
Then the master waits for a read of the SR1 register followed by a write in the DR register, holding
the SCL line low (see Figure 31 Transfer sequencing EV9).
Then the second address byte is sent by the interface.
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After completion of this transfer (and acknowledge
from the slave if the ACK bit is set):
– The EVF bit is set by hardware with interrupt
generation if the ITE bit is set.
Then the master waits for a read of the SR1 register followed by a write in the CR register (for example set PE bit), holding the SCL line low (see Figure 31 Transfer sequencing EV6).
Next the master must enter Receiver or Transmitter mode.
Note: In 10-bit addressing mode, to switch the
master to Receiver mode, software must generate
a repeated Start condition and resend the header
sequence with the least significant bit set
(11110xx1).
Master Receiver
Following the address transmission and after SR1
and CR registers have been accessed, the master
receives bytes from the SDA line into the DR register via the internal shift register. After each byte
the interface generates in sequence:
– Acknowledge pulse if if the ACK bit is set
– EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 register followed by a read of the DR register, holding
the SCL line low (see Figure 31 Transfer sequencing EV7).
To close the communication: before reading the
last byte from the DR register, set the STOP bit to
generate the Stop condition. The interface goes
automatically back to slave mode (M/SL bit
cleared).
Note: In order to generate the non-acknowledge
pulse after the last received data byte, the ACK bit
must be cleared just before reading the second
last data byte.
ST72251
I2C BUS INTERFACE (Cont’d)
Master Transmitter
Following the address transmission and after SR1
register has been read, the master sends bytes
from the DR register to the SDA line via the internal shift register.
The master waits for a read of the SR1 register followed by a write in the DR register, holding the
SCL line low (see Figure 31 Transfer sequencing
EV8).
When the acknowledge bit is received, the
interface sets:
– EVF and BTF bits with an interrupt if the ITE bit
is set.
To close the communication: after writing the last
byte to the DR register, set the STOP bit to generate the Stop condition. The interface goes automatically back to slave mode (M/SL bit cleared).
BERR bits are set by hardware with an interrupt
if ITE is set.
– AF: Detection of a non-acknowledge bit. In this
case, the EVF and AF bits are set by hardware
with an interrupt if the ITE bit is set. To resume,
set the START or STOP bit.
– ARLO: Detection of an arbitration lost condition.
In this case the ARLO bit is set by hardware (with
an interrupt if the ITE bit is set and the interface
goes automatically back to slave mode (the M/SL
bit is cleared).
Note: In all these cases, the SCL line is not held
low; however, the SDA line can remain low due to
possible «0» bits transmitted last. It is then necessary to release both lines by software.
Error Cases
– BERR: Detection of a Stop or a Start condition
during a byte transfer. In this case, the EVF and
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ST72251
I2C BUS INTERFACE (Cont’d)
Figure 31. Transfer Sequencing
7-bit Slave receiver:
S Address
A
Data1
A
Data2
EV1
A
EV2
EV2
.....
DataN
A
P
EV2
EV4
7-bit Slave transmitter:
S Address
A
Data1
A
EV1 EV3
Data2
A
EV3
EV3
DataN
.....
NA
P
EV3-1
EV4
7-bit Master receiver:
S
Address
A
EV5
Data1
A
EV6
Data2
A
EV7
EV7
DataN
.....
NA
P
EV7
7-bit Master transmitter:
S
Address
A
EV5
Data1
A
EV6 EV8
Data2
A
EV8
.....
EV8
DataN
A
P
EV8
10-bit Slave receiver:
S Header
A
Address
A
Data1
A
EV1
.....
EV2
DataN
A
P
EV2
EV4
10-bit Slave transmitter:
Sr Header A
Data1
A
EV1 EV3
EV3
.... DataN
.
A
P
EV3-1
EV4
10-bit Master transmitter
S
Header
EV5
A
Address
EV9
A
Data1
A
EV6 EV8
EV8
.....
DataN
A
P
EV8
10-bit Master receiver:
Header
Sr
EV5
A
Data1
EV6
A
EV7
.... .
DataN
A
P
EV7
Legend: S=Start, Sr = Repeated Start, P=Stop, A=Acknowledge, NA=Non-acknowledge,
EVx=Event (with interrupt if ITE=1)
EV1: EVF=1, ADSL=1, cleared by reading SR1 register.
EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading SR1 register. BTF is cleared by releasing the
lines (STOP=1, STOP=0) or by writing DR register (DR=FFh). Note: If lines are released by
STOP=1, STOP=0, the subsequent EV4 is not seen.
EV4: EVF=1, STOPF=1, cleared by reading SR2 register.
EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register.
EV6: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1).
EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
EV9: EVF=1, ADD10=1, cleared by reading SR1 register followed by writing DR register.
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ST72251
I2C BUS INTERFACE (Cont’d)
5.4.5 Low Power Modes
Mode
WAIT
HALT
Description
No effect on I2C interface.
I 2C interrupts cause the device to exit from WAIT mode.
I 2C registers are frozen.
In HALT mode, the I 2C interface is inactive and does not acknowledge data on the bus. The I 2C interface
resumes operation when the MCU is woken up by an interrupt with “exit from HALT mode” capability.
5.4.6 Interrupts
Figure 32. Event Flags and Interrupt Generation
ADD10
BTF
ADSL
SB
AF
STOPF
ARLO
BERR
ITE
INTERRUPT
EVF
*
* EVF can also be set by EV6 or an error from the SR2 register.
Interrupt Event
10-bit Address Sent Event (Master mode)
End of Byte Transfer Event
Address Matched Event (Slave mode)
Start Bit Generation Event (Master mode)
Acknowledge Failure Event
Stop Detection Event (Slave mode)
Arbitration Lost Event (Multimaster configuration)
Bus Error Event
Event
Flag
Enable
Control
Bit
ADD10
BTF
ADSEL
SB
AF
STOPF
ARLO
BERR
ITE
Exit
from
Wait
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Exit
from
Halt
No
No
No
No
No
No
No
No
Note: The I2C interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the I-bit in the CC register is reset (RIM instruction).
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ST72251
I2C BUS INTERFACE (Cont’d)
5.4.7 Register Description
I2C CONTROL REGISTER (CR)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
0
0
PE
ENGC START ACK
STOP
ITE
Bit 7:6 = Reserved. Forced to 0 by hardware.
Bit 5 = PE Peripheral enable.
This bit is set and cleared by software.
0: Peripheral disabled
1: Master/Slave capability
Notes:
– When PE=0, all the bits of the CR register and
the SR register except the Stop bit are reset. All
outputs are released while PE=0
– When PE=1, the corresponding I/O pins are selected by hardware as alternate functions.
– To enable the I2C interface, write the CR register
TWICE with PE=1 as the first write only activates
the interface (only PE is set).
Bit 4 = ENGC Enable General Call.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disabled (PE=0). The 00h General Call address is acknowledged (01h ignored).
0: General Call disabled
1: General Call enabled
Bit 3 = START Generation of a Start condition.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disabled (PE=0) or when the Start condition is sent
(with interrupt generation if ITE=1).
– In master mode:
0: No start generation
1: Repeated start generation
– In slave mode:
0: No start generation
1: Start generation when the bus is free
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Bit 2 = ACK Acknowledge enable.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disabled (PE=0).
0: No acknowledge returned
1: Acknowledge returned after an address byte or
a data byte is received
Bit 1 = STOP Generation of a Stop condition.
This bit is set and cleared by software. It is also
cleared by hardware in master mode. Note: This
bit is not cleared when the interface is disabled
(PE=0).
– In master mode:
0: No stop generation
1: Stop generation after the current byte transfer
or after the current Start condition is sent. The
STOP bit is cleared by hardware when the Stop
condition is sent.
– In slave mode:
0: No stop generation
1: Release the SCL and SDA lines after the current byte transfer (BTF=1). In this mode the
STOP bit has to be cleared by software.
Bit 0 = ITE Interrupt enable.
This bit is set and cleared by software and cleared
by hardware when the interface is disabled
(PE=0).
0: Interrupts disabled
1: Interrupts enabled
Refer to Figure 32 for the relationship between the
events and the interrupt.
SCL is held low when the ADD10, SB, BTF or
ADSL flags or an EV6 event (See Figure 31) is detected.
ST72251
I2C BUS INTERFACE (Cont’d)
I2C STATUS REGISTER 1 (SR1)
Read Only
Reset Value: 0000 0000 (00h)
arbitration (ARLO=1) or when the interface is disabled (PE=0).
0: Data byte received (if BTF=1)
1: Data byte transmitted
7
EVF
0
ADD10
TRA
BUSY
BTF
ADSL
M/SL
SB
Bit 7 = EVF Event flag.
This bit is set by hardware as soon as an event occurs. It is cleared by software reading SR2 register
in case of error event or as described in Figure 31.
It is also cleared by hardware when the interface is
disabled (PE=0).
0: No event
1: One of the following events has occurred:
– BTF=1 (Byte received or transmitted)
– ADSL=1 (Address matched in Slave mode
while ACK=1)
– SB=1 (Start condition generated in Master
mode)
– AF=1 (No acknowledge received after byte
transmission)
– STOPF=1 (Stop condition detected in Slave
mode)
– ARLO=1 (Arbitration lost in Master mode)
– BERR=1 (Bus error, misplaced Start or Stop
condition detected)
– ADD10=1 (Master has sent header byte)
– Address byte successfully transmitted in Master mode.
Bit 6 = ADD10 10-bit addressing in Master mode.
This bit is set by hardware when the master has
sent the first byte in 10-bit address mode. It is
cleared by software reading SR2 register followed
by a write in the DR register of the second address
byte. It is also cleared by hardware when the peripheral is disabled (PE=0).
0: No ADD10 event occurred.
1: Master has sent first address byte (header)
Bit 4 = BUSY Bus busy.
This bit is set by hardware on detection of a Start
condition and cleared by hardware on detection of
a Stop condition. It indicates a communication in
progress on the bus. This information is still updated when the interface is disabled (PE=0).
0: No communication on the bus
1: Communication ongoing on the bus
Bit 3 = BTF Byte transfer finished.
This bit is set by hardware as soon as a byte is correctly received or transmitted with interrupt generation if ITE=1. It is cleared by software reading
SR1 register followed by a read or write of DR register. It is also cleared by hardware when the interface is disabled (PE=0).
– Following a byte transmission, this bit is set after
reception of the acknowledge clock pulse. In
case an address byte is sent, this bit is set only
after the EV6 event (See Figure 31). BTF is
cleared by reading SR1 register followed by writing the next byte in DR register.
– Following a byte reception, this bit is set after
transmission of the acknowledge clock pulse if
ACK=1. BTF is cleared by reading SR1 register
followed by reading the byte from DR register.
The SCL line is held low while BTF=1.
0: Byte transfer not done
1: Byte transfer succeeded
Bit 2 = ADSL Address matched (Slave mode).
This bit is set by hardware as soon as the received
slave address matched with the OAR register content or a general call is recognized. An interrupt is
generated if ITE=1. It is cleared by software reading SR1 register or by hardware when the interface is disabled (PE=0).
The SCL line is held low while ADSL=1.
0: Address mismatched or not received
1: Received address matched
Bit 5 = TRA Transmitter/Receiver.
When BTF is set, TRA=1 if a data byte has been
transmitted. It is cleared automatically when BTF
is cleared. It is also cleared by hardware after detection of Stop condition (STOPF=1), loss of bus
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ST72251
I2C BUS INTERFACE (Cont’d)
Bit 1 = M/SL Master/Slave.
This bit is set by hardware as soon as the interface
is in Master mode (writing START=1). It is cleared
by hardware after detecting a Stop condition on
the bus or a loss of arbitration (ARLO=1). It is also
cleared when the interface is disabled (PE=0).
0: Slave mode
1: Master mode
Bit 0 = SB Start bit (Master mode).
This bit is set by hardware as soon as the Start
condition is generated (following a write
START=1). An interrupt is generated if ITE=1. It is
cleared by software reading SR1 register followed
by writing the address byte in DR register. It is also
cleared by hardware when the interface is disabled (PE=0).
0: No Start condition
1: Start condition generated
I2C STATUS REGISTER 2 (SR2)
Read Only
Reset Value: 0000 0000 (00h)
7
Bit 2 = ARLO Arbitration lost.
This bit is set by hardware when the interface loses the arbitration of the bus to another master. An
interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when
the interface is disabled (PE=0).
After an ARLO event the interface switches back
automatically to Slave mode (M/SL=0).
The SCL line is not held low while ARLO=1.
0: No arbitration lost detected
1: Arbitration lost detected
Bit 1 = BERR Bus error.
This bit is set by hardware when the interface detects a misplaced Start or Stop condition. An interrupt is generated if ITE=1. It is cleared by software
reading SR2 register or by hardware when the interface is disabled (PE=0).
The SCL line is not held low while BERR=1.
0: No misplaced Start or Stop condition
1: Misplaced Start or Stop condition
0
0
0
0
AF
STOPF ARLO BERR GCAL
Bit 7:5 = Reserved. Forced to 0 by hardware.
Bit 4 = AF Acknowledge failure.
This bit is set by hardware when no acknowledge
is returned. An interrupt is generated if ITE=1. It is
cleared by software reading SR2 register or by
hardware when the interface is disabled (PE=0).
The SCL line is not held low while AF=1.
0: No acknowledge failure
1: Acknowledge failure
Bit 3 = STOPF Stop detection (Slave mode).
This bit is set by hardware when a Stop condition
is detected on the bus after an acknowledge (if
ACK=1). An interrupt is generated if ITE=1. It is
cleared by software reading SR2 register or by
hardware when the interface is disabled (PE=0).
The SCL line is not held low while STOPF=1.
0: No Stop condition detected
1: Stop condition detected
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Bit 0 = GCAL General Call (Slave mode).
This bit is set by hardware when a general call address is detected on the bus while ENGC=1. It is
cleared by hardware detecting a Stop condition
(STOPF=1) or when the interface is disabled
(PE=0).
0: No general call address detected on bus
1: general call address detected on bus
ST72251
I2C BUS INTERFACE (Cont’d)
I2C CLOCK CONTROL REGISTER (CCR)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
I2C DATA REGISTER (DR)
Read / Write
Reset Value: 0000 0000 (00h)
7
FM/SM
CC6
CC5
CC4
CC3
CC2
CC1
0
CC0
D7
Bit 7 = FM/SM Fast/Standard I2C mode.
This bit is set and cleared by software. It is not
cleared when the interface is disabled (PE=0).
0: Standard I 2C mode
1: Fast I2C mode
Bit 6:0 = CC6-CC0 7-bit clock divider.
These bits select the speed of the bus (FSCL) depending on the I2C mode. They are not cleared
when the interface is disabled (PE=0).
– Standard mode (FM/SM=0): FSCL <= 100kHz
FSCL = FCPU /(2x([CC6..CC0]+2))
– Fast mode (FM/SM=1): FSCL > 100kHz
FSCL = FCPU /(3x([CC6..CC0]+2))
Note: The programmed FSCL assumes no load on
SCL and SDA lines.
D6
D5
D4
D3
D2
D1
D0
Bit 7:0 = D7-D0 8-bit Data Register.
These bits contain the byte to be received or transmitted on the bus.
– Transmitter mode: Byte transmission start automatically when the software writes in the DR register.
– Receiver mode: the first data byte is received automatically in the DR register using the least significant bit of the address.
Then, the following data bytes are received one
by one after reading the DR register.
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ST72251
I2C BUS INTERFACE (Cont’d)
I2C OWN ADDRESS REGISTER (OAR1)
Read / Write
Reset Value: 0000 0000 (00h)
7
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2 ADD1
I2C OWN ADDRESS REGISTER (OAR2)
Read / Write
Reset Value: 0100 0000 (40h)
0
7
ADD0
FR1
7-bit Addressing Mode
Bit 7:1 = ADD7-ADD1 Interface address.
These bits define the I 2C bus address of the interface. They are not cleared when the interface is
disabled (PE=0).
Bit 0 = ADD0 Address direction bit.
This bit is don’t care, the interface acknowledges
either 0 or 1. It is not cleared when the interface is
disabled (PE=0).
Note: Address 01h is always ignored.
10-bit Addressing Mode
Bit 7:0 = ADD7-ADD0 Interface address.
These are the least significant bits of the I2C bus
address of the interface. They are not cleared
when the interface is disabled (PE=0).
0
FR0
0
0
0
ADD9
ADD8
0
Bit 7:6 = FR1-FR0 Frequency bits.
These bits are set by software only when the interface is disabled (PE=0). To configure the interface
to I2C specifed delays select the value corresponding to the microcontroller frequency FCPU.
FCPU Range (MHz)
2.5 - 6
6 -10
10 - 14
14 - 24
FR1
0
0
1
1
FR0
0
1
0
1
Bit 5:3 = Reserved
Bit 2:1 = ADD9-ADD8 Interface address.
These are the most significant bits of the I2C bus
address of the interface (10-bit mode only). They
are not cleared when the interface is disabled
(PE=0).
Bit 0 = Reserved.
Table 15. I2C Register Map
Address
(Hex.)
Register
Name
28
CR
29
SR1
2A
SR2
2B
CCR
2C
OAR1
2D
OAR2
2E
DR
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59
7
6
EVF
FM/SM
5
4
3
2
1
0
PE
ENGC
START
ACK
STOP
ITE
TRA
BUSY
BTF
ADSL
M/SL
SB
AF
STOPF
ARLO
BERR
GCAL
ADD9
ADD8
CC6 .. CC0
ADD7 .. ADD0
FR1
FR0
DR7 .. DR0
ST72251
I2C INTERFACE (Cont’d)
5.4.8 Application Considerations
5.4.8.1 Programming Considerations
The interface can be used in two modes:
– Interrupt
– Polling
Caution: Care should be taken when polling error
events as the asynchronous setting of error bits
can result in error events being missed.
5.4.8.2 Application Example
The software routines given below describe a possible software driver to control the I2C interface
connected to an external EEPROM without communication error management.
The interface configuration is Master mode.
This polling software does not use the EVF flag
and can be easily adapted to manage interrupts
keeping the same strategy.
/**************** (c) 1997 SGS-Thomson Microelectronics ********************/
/*
*/
/* THE SOFTWARE INCLUDED IN THIS DOCUMENT IS FOR GUIDANCE ONLY. SGS-THOMSON */
/*
SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
*/
/* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM USE OF THIS SOFTWARE.
*/
/*
*/
/***************************************** *********************************/
/*---------------------------- Basic Routines -----------------------------*/
void I2Cm_Start (void)
/* Generates I2C-Bus Start Condition.*/
{
SetBit(I2C_CR,START);
/* Generate start condition.*/
while (!ValBit(I2C_SR1,SB)) ; /* Wait for the Start bit generation (“EV5”).*/
}
void I2Cm_Stop (void)
{
SetBit(I2C_CR,STOP);
}
void I2Cm_Ack (void)
{
SetBit(I2C_CR,ACK);
}
/* Generates I2C-Bus Stop Condition.*/
/* Generate stop condition.*/
/* Activate acknowledge generation.*/
/* Acknowledge after the next received data bytes.*/
void I2Cm_nAck (void)
/* Disactivate acknowledge generation.*/
{
ClrBit(I2C_CR,ACK); /* Non acknowledge after the next received data bytes.*/
}
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ST72251
I2C INTERFACE (Cont’d)
/*------------------------- Initialization Routine ---------------- --------*/
void I2Cm_Init (void)
{
I2C_CR = 0x00;
I2C_CCR = 0X12;
asm TNZ I2C_DR;
asm TNZ I2C_SR1;
asm TNZ I2C_SR2;
I2C_CR = 0x24;
I2C_CR = 0x24;
I2Cm_Start();
I2Cm_Stop();
}
/* Force reset status of the control register.*/
/* Set the I2C-bus speed to 0-100KHz.*/
/* Touch registers to remove pending interrupt.*/
/* PE=1, ACK=1: switch on the peripheral interface.*/
/* Write twice: switch on periph then set config.*/
/* Start condition generation.*/
/* Stop condition generation.*/
/*------------------------- Communication Routines ------------------------*/
void I2Cm_SetAddr (char i2c_addr)
{
I2Cm_Start();
I2C_DR = i2c_addr;
}
/* Generates a start condition.*/
/* Write address to be transmitted.*/
void I2Cm_TxData (char i2c_data)
/* Transmits a data byte.*/
{
do {
if (I2C_SR2) while(1);
/* Communication error detected: infinite loop.*/
SetBit(I2C_CR,PE);
/* Touch the control register to pass ”EV6”.*/
} while (!ValBit(I2C_SR1,BTF));
/* Wait for BTF (”EV8”).*/
I2C_DR = i2c_data;
/* Write data byte to be transmitted.*/
}
char I2Cm_RxData (char last) /* Return received data byte (last one flagged).*/
{
do {
if (I2C_SR2) while(1);
/* Communication error detected: infinite loop.*/
SetBit(I2C_CR,PE );
/* Touch the control register to pass ”EV6”.*/
} while (!ValBit(I2C_SR1,BTF));
/* Wait for BTF (”EV7”).*/
if (last) I2Cm_Stop(); /* End of communication: stop condition generation.*/
return(I2C_DR);
/* Read/return data byte received.*/
}
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ST72251
I2C INTERFACE (Cont’d)
/*---------------------- EEPROM Communication Routines ---------------- ----*/
void I2Cm_Tx (char *buff_add, char sub_add, char nb, char dest_add)
{
/* Transmit data buffer to EEPROM with least significant bytes first.*/
I2Cm_SetAddr (dest_add);
/* Slave address selection on I2C bus.*/
I2Cm_TxData(sub_add);
/* Sub address selection.*/
for (;nb > 0; nb--)
/* Loop to send all selected data from output buffer.*/
I2Cm_TxData(*(bu ff_add+nb-1));
/* Next output buffer data byte sent.*/
I2Cm_Stop();
/* End of communication: stop condition generation.*/
}
void I2Cm_Rx (char *buff_add, char sub_add, char nb, char dest_add)
{
/* Receive data buffer from EEPROM with least significant bytes first.*/
I2Cm_SetAddr (dest_add);
/* Slave address selection on I2C bus.*/
I2Cm_TxData(sub_add);
/* Sub address selection.*/
I2Cm_SetAddr(dest_add|0x01);
/* Slave address selection in read mode.*/
do
/* Loop to send all selected data from output buffer.*/
{
nb--;
if (nb==0)
/* Last byte to receive.*/
{
I2Cm_nAck();
/* Non acknowledge after last reception.*/
*(buff_add+nb) = I2Cm_RxData(1);
/* Last data byte reception.*/
}
else
*(buff_add+nb) = I2Cm_RxData(0);
/* Next data byte reception.*/
} while (nb > 0);
/* Loop to receive the selected number of bytes.*/
I2Cm_Ack();
/* Acknowledge after reception.*/
}
/*** (c) 1997 SGS-Thomson Microelectronics *************** END OF EXAMPLE ***/
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ST72251
5.5 SERIAL PERIPHERAL INTERFACE (SPI)
5.5.3 General description
The SPI is connected to external devices through
4 alternate pins:
– MISO: Master In Slave Out pin
– MOSI: Master Out Slave In pin
– SCK: Serial Clock pin
– SS: Slave select pin
5.5.1 Introduction
The Serial Peripheral Interface (SPI) allows fullduplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves or a system in
which devices may be either masters or slaves.
The SPI is normally used for communication between the microcontroller and external peripherals
or another microcontroller.
Refer to the Pin Description chapter for the devicespecific pin-out.
A basic example of interconnections between a
single master and a single slave is illustrated on
Figure 33.
The MOSI pins are connected together as are
MISO pins. In this way data is transferred serially
between master and slave (most significant bit
first).
When the master device transmits data to a slave
device via MOSI pin, the slave device responds by
sending data to the master device via the MISO
pin. This implies full duplex transmission with both
data out and data in synchronized with the same
clock signal (which is provided by the master device via the SCK pin).
Thus, the byte transmitted is replaced by the byte
received and eliminates the need for separate
transmit-empty and receiver-full bits. A status flag
is used to indicate that the I/O operation is complete.
Four possible data/clock timing relationships may
be chosen (see Figure 36) but master and slave
must be programmed with the same timing mode.
5.5.2 Main Features
■ Full duplex, three-wire synchronous transfers
■ Master or slave operation
■ Four master mode frequencies
■ Maximum slave mode frequency = fCPU/2.
■ Four programmable master bit rates
■ Programmable clock polarity and phase
■ End of transfer interrupt flag
■ Write collision flag protection
■ Master mode fault protection capability.
Figure 33. Serial Peripheral Interface Master/Slave
SLAVE
MASTER
MSBit
LSBit
8-BIT SHIFT REGISTER
SPI
CLOCK
GENERATOR
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MSBit
MISO
MISO
MOSI
MOSI
SCK
SS
SCK
+5V
SS
LSBit
8-BIT SHIFT REGISTER
ST72251
SERIAL PERIPHERAL INTERFACE (Cont’d)
Figure 34. Serial Peripheral Interface Block Diagram
Internal Bus
Read
DR
IT
Read Buffer
request
MOSI
MISO
SR
8-Bit Shift Register
SPIF WCOL - MODF
-
-
-
-
Write
SPI
STATE
CONTROL
SCK
SS
CR
SPIE
SPE
SPR2 MSTR CPOL CPHA SPR1 SPR0
MASTER
CONTROL
SERIAL
CLOCK
GENERATOR
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ST72251
SERIAL PERIPHERAL INTERFACE (Cont’d)
5.5.4 Functional Description
Figure 33 shows the serial peripheral interface
(SPI) block diagram.
This interface contains 3 dedicated registers:
– A Control Register (CR)
– A Status Register (SR)
– A Data Register (DR)
Refer to the CR, SR and DR registers in Section
5.5.7for the bit definitions.
5.5.4.1 Master Configuration
In a master configuration, the serial clock is generated on the SCK pin.
Procedure
– Select the SPR0 & SPR1 bits to define the serial clock baud rate (see CR register).
– Select the CPOL and CPHA bits to define one
of the four relationships between the data
transfer and the serial clock (see Figure 36).
– The SS pin must be connected to a high level
signal during the complete byte transmit sequence.
– The MSTR and SPE bits must be set (they remain set only if the SS pin is connected to a
high level signal).
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In this configuration the MOSI pin is a data output
and to the MISO pin is a data input.
Transmit sequence
The transmit sequence begins when a byte is written the DR register.
The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MOSI pin most
significant bit first.
When data transfer is complete:
– The SPIF bit is set by hardware
– An interrupt is generated if the SPIE bit is set
and the I bit in the CCR register is cleared.
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the DR register is read,
the SPI peripheral returns this buffered value.
Clearing the SPIF bit is performed by the following
software sequence:
1. An access to the SR register while the SPIF bit
is set
2. A read to the DR register.
Note: While the SPIF bit is set, all writes to the DR
register are inhibited until the SR register is read.
ST72251
SERIAL PERIPHERAL INTERFACE (Cont’d)
5.5.4.2 Slave Configuration
In slave configuration, the serial clock is received
on the SCK pin from the master device.
The value of the SPR0 & SPR1 bits is not used for
the data transfer.
Procedure
– For correct data transfer, the slave device
must be in the same timing mode as the master device (CPOL and CPHA bits). See Figure
36.
– The SS pin must be connected to a low level
signal during the complete byte transmit sequence.
– Clear the MSTR bit and set the SPE bit to assign the pins to alternate function.
In this configuration the MOSI pin is a data input
and the MISO pin is a data output.
Transmit Sequence
The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MISO pin most
significant bit first.
The transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its MOSI pin.
When data transfer is complete:
– The SPIF bit is set by hardware
– An interrupt is generated if SPIE bit is set and
I bit in CCR register is cleared.
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the DR register is read,
the SPI peripheral returns this buffered value.
Clearing the SPIF bit is performed by the following
software sequence:
1. An access to the SR register while the SPIF bit
is set.
2.A read to the DR register.
Notes: While the SPIF bit is set, all writes to the
DR register are inhibited until the SR register is
read.
The SPIF bit can be cleared during a second
transmission; however, it must be cleared before
the second SPIF bit in order to prevent an overrun
condition (see Section 5.5.4.6).
Depending on the CPHA bit, the SS pin has to be
set to write to the DR register between each data
byte transfer to avoid a write collision (see Section
5.5.4.4).
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ST72251
SERIAL PERIPHERAL INTERFACE (Cont’d)
5.5.4.3 Data Transfer Format
During an SPI transfer, data is simultaneously
transmitted (shifted out serially) and received
(shifted in serially). The serial clock is used to synchronize the data transfer during a sequence of
eight clock pulses.
The SS pin allows individual selection of a slave
device; the other slave devices that are not selected do not interfere with the SPI transfer.
Clock Phase and Clock Polarity
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits.
The CPOL (clock polarity) bit controls the steady
state value of the clock when no data is being
transferred. This bit affects both master and slave
modes.
The combination between the CPOL and CPHA
(clock phase) bits selects the data capture clock
edge.
Figure 36, shows an SPI transfer with the four
combinations of the CPHA and CPOL bits. The diagram may be interpreted as a master or slave
timing diagram where the SCK pin, the MISO pin,
the MOSI pin are directly connected between the
master and the slave device.
The SS pin is the slave device select input and can
be driven by the master device.
The master device applies data to its MOSI pinclock edge before the capture clock edge.
CPHA bit is set
The second edge on the SCK pin (falling edge if
the CPOL bit is reset, rising edge if the CPOL bit is
set) is the MSBit capture strobe. Data is latched on
the occurrence of the second clock transition.
No write collision should occur even if the SS pin
stays low during a transfer of several bytes (see
Figure 35).
CPHA bit is reset
The first edge on the SCK pin (falling edge if CPOL
bit is set, rising edge if CPOL bit is reset) is the
MSBit capture strobe. Data is latched on the occurrence of the first clock transition.
The SS pin must be toggled high and low between
each byte transmitted (see Figure 35).
To protect the transmission from a write collision a
low value on the SS pin of a slave device freezes
the data in its DR register and does not allow it to
be altered. Therefore the SS pin must be high to
write a new data byte in the DR without producing
a write collision.
Figure 35. CPHA / SS Timing Diagram
MOSI/MISO
Byte 1
Byte 2
Byte 3
Master SS
Slave SS
(CPHA=0)
Slave SS
(CPHA=1)
VR02131A
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ST72251
SERIAL PERIPHERAL INTERFACE (Cont’d)
Figure 36. Data Clock Timing Diagram
CPHA =1
SCLK (with
CPOL = 1)
SCLK (with
CPOL = 0)
MISO
(from master)
MOSI
(from slave)
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
SS
(to slave)
CAPTURE STROBE
CPHA =0
CPOL = 1
CPOL = 0
MSBit
MISO
(from master)
MOSI
(from slave)
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
SS
(to slave)
CAPTURE STROBE
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
VR02131B
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ST72251
SERIAL PERIPHERAL INTERFACE (Cont’d)
5.5.4.4 Write Collision Error
A write collision occurs when the software tries to
write to the DR register while a data transfer is taking place with an external device. When this happens, the transfer continues uninterrupted; and
the software write will be unsuccessful.
Write collisions can occur both in master and slave
mode.
Note: a ”read collision” will never occur since the
received data byte is placed in a buffer in which
access is always synchronous with the MCU operation.
In Slave mode
When the CPHA bit is set:
The slave device will receive a clock (SCK) edge
prior to the latch of the first data transfer. This first
clock edge will freeze the data in the slave device
DR register and output the MSBit on to the external MISO pin of the slave device.
The SS pin low state enables the slave device but
the output of the MSBit onto the MISO pin does
not take place until the first data transfer clock
edge.
When the CPHA bit is reset:
Data is latched on the occurrence of the first clock
transition. The slave device does not have any
way of knowing when that transition will occur;
therefore, the slave device collision occurs when
software attempts to write the DR register after its
SS pin has been pulled low.
For this reason, the SS pin must be high, between
each data byte transfer, to allow the CPU to write
in the DR register without generating a write collision.
In Master mode
Collision in the master device is defined as a write
of the DR register while the internal serial clock
(SCK) is in the process of transfer.
The SS pin signal must be always high on the
master device.
WCOL bit
The WCOL bit in the SR register is set if a write
collision occurs.
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software
sequence (see Figure 37).
Figure 37. Clearing the WCOL bit (Write Collision Flag) Software Sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
1st Step
Read SR
OR
Read SR
THEN
THEN
2nd Step
Read DR
SPIF =0
WCOL=0
Write DR
SPIF =0
WCOL=0 if no transfer has started
WCOL=1 if a transfer has started
before the 2nd step
Clearing sequence before SPIF = 1 (during a data byte transfer)
1st Step
Read SR
THEN
2nd Step
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Read DR
WCOL=0
Note: Writing in DR register instead of reading in it do not reset
WCOL bit
ST72251
SERIAL PERIPHERAL INTERFACE (Cont’d)
5.5.4.5 Master Mode Fault
Master mode fault occurs when the master device
has its SS pin pulled low, then the MODF bit is set.
Master mode fault affects the SPI peripheral in the
following ways:
– The MODF bit is set and an SPI interrupt is
generated if the SPIE bit is set.
– The SPE bit is reset. This blocks all output
from the device and disables the SPI peripheral.
– The MSTR bit is reset, thus forcing the device
into slave mode.
Clearing the MODF bit is done through a software
sequence:
1. A read or write access to the SR register while
the MODF bit is set.
2. A write to the CR register.
Notes: To avoid any multiple slave conflicts in the
case of a system comprising several MCUs, the
SS pin must be pulled high during the clearing sequence of the MODF bit. The SPE and MSTR bits
may be restored to their original state during or after this clearing sequence.
Hardware does not allow the user to set the SPE
and MSTR bits while the MODF bit is set except in
the MODF bit clearing sequence.
In a slave device the MODF bit can not be set, but
in a multi master configuration the device can be in
slave mode with this MODF bit set.
The MODF bit indicates that there might have
been a multi-master conflict for system control and
allows a proper exit from system operation to a reset or default system state using an interrupt routine.
5.5.4.6 Overrun Condition
An overrun condition occurs when the master device has sent several data bytes and the slave device has not cleared the SPIF bit issuing from the
previous data byte transmitted.
In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the DR register returns this byte. All other bytes
are lost.
This condition is not detected by the SPI peripheral.
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ST72251
SERIAL PERIPHERAL INTERFACE (Cont’d)
5.5.4.7 Single Master and Multimaster Configurations
There are two types of SPI systems:
For more security, the slave device may respond
to the master with the received data byte. Then the
– Single Master System
master will receive the previous byte back from the
– Multimaster System
slave device if all MISO and MOSI pins are connected and the slave has not written its DR register.
Single Master System
Other transmission security methods can use
A typical single master system may be configured,
ports for handshake lines or data bytes with comusing an MCU as the master and four MCUs as
mand fields.
slaves (see Figure 38).
Multi-master System
The master device selects the individual slave deA multi-master system may also be configured by
vices by using four pins of a parallel port to control
the user. Transfer of master control could be imthe four SS pins of the slave devices.
plemented using a handshake method through the
The SS pins are pulled high during reset since the
I/O ports or by an exchange of code messages
master device ports will be forced to be inputs at
through the serial peripheral interface system.
that time, thus disabling the slave devices.
The multi-master system is principally handled by
the MSTR bit in the CR register and the MODF bit
Note: To prevent a bus conflict on the MISO line
in the SR register.
the master allows only one active slave device
during a transmission.
Figure 38. Single Master Configuration
SS
SCK
Slave
MCU
Slave
MCU
MOSI MISO
MOSI MISO
SCK
Master
MCU
5V
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SS
Ports
MOSI MISO
SS
SS
SCK
SS
SCK
Slave
MCU
SCK
Slave
MCU
MOSI MISO
MOSI MISO
ST72251
SERIAL PERIPHERAL INTERFACE (Cont’d)
5.5.5 Low Power Modes
Mode
WAIT
HALT
Description
No effect on SPI.
SPI interrupt events cause the device to exit from WAIT mode.
SPI registers are frozen.
In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with
“exit from HALT mode” capability.
5.5.6 Interrupts
Interrupt Event
SPI End of Transfer Event
Master Mode Fault Event
Event
Flag
Enable
Control
Bit
SPIF
MODF
SPIE
Exit
from
Wait
Yes
Yes
Exit
from
Halt
No
No
Note: The SPI interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the interrupt mask in
the CC register is reset (RIM instruction).
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ST72251
SERIAL PERIPHERAL INTERFACE (Cont’d)
5.5.7 Register Description
CONTROL REGISTER (CR)
Read/Write
Reset Value: 0000xxxx (0xh)
7
SPIE
0
SPE SPR2
MSTR
CPOL
CPHA
SPR1
SPR0
Bit 7 = SPIE Serial peripheral interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever SPIF=1
or MODF=1 in the SR register
Bit 6 = SPE Serial peripheral output enable.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 5.5.4.5 Master Mode Fault).
0: I/O port connected to pins
1: SPI alternate functions connected to pins
The SPE bit is cleared by reset, so the SPI peripheral is not initially connected to the external pins.
Bit 5 = SPR2 Divider Enable.
this bit is set and cleared by software and it is
cleared by reset. It is used with the SPR[1:0] bits to
set the baud rate. Refer to Table 16.
0: Divider by 2 enabled
1: Divider by 2 disabled
Bit 4 = MSTR Master.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 5.5.4.5 Master Mode Fault).
0: Slave mode is selected
1: Master mode is selected, the function of the
SCK pin changes from an input to an output and
the functions of the MISO and MOSI pins are reversed.
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Bit 3 = CPOL Clock polarity.
This bit is set and cleared by software. This bit determines the steady state of the serial Clock. The
CPOL bit affects both the master and slave
modes.
0: The steady state is a low value at the SCK pin.
1: The steady state is a high value at the SCK pin.
Bit 2 = CPHA Clock phase.
This bit is set and cleared by software.
0: The first clock transition is the first data capture
edge.
1: The second clock transition is the first capture
edge.
Bit 1:0 = SPR[1:0] Serial peripheral rate.
These bits are set and cleared by software.Used
with the SPR2 bit, they select one of six baud rates
to be used as the serial clock when the device is a
master.
These 2 bits have no effect in slave mode.
Table 16. Serial Peripheral Baud Rate
Serial Clock
SPR2
SPR1
SPR0
fCPU/4
1
0
0
fCPU/8
0
0
0
fCPU/16
0
0
1
fCPU/32
1
1
0
fCPU/64
0
1
0
f CPU/128
0
1
1
ST72251
SERIAL PERIPHERAL INTERFACE (Cont’d)
STATUS REGISTER (SR)
Read Only
Reset Value: 0000 0000 (00h)
7
SPIF
WCOL
-
MODF
-
-
-
DATA I/O REGISTER (DR)
Read/Write
Reset Value: Undefined
0
7
-
D7
Bit 7 = SPIF Serial Peripheral data transfer flag.
This bit is set by hardware when a transfer has
been completed. An interrupt is generated if
SPIE=1 in the CR register. It is cleared by a software sequence (an access to the SR register followed by a read or write to the DR register).
0: Data transfer is in progress or has been approved by a clearing sequence.
1: Data transfer between the device and an external device has been completed.
Note: While the SPIF bit is set, all writes to the DR
register are inhibited.
Bit 6 = WCOL Write Collision status.
This bit is set by hardware when a write to the DR
register is done during a transmit sequence. It is
cleared by a software sequence (see Figure 37).
0: No write collision occurred
1: A write collision has been detected
0
D6
D5
D4
D3
D2
D1
D0
The DR register is used to transmit and receive
data on the serial bus. In the master device only a
write to this register will initiate transmission/reception of another byte.
Notes: During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
the serial peripheral data I/O register, the buffer is
actually being read.
Warning:
A write to the DR register places data directly into
the shift register for transmission.
A write to the the DR register returns the value located in the buffer and not the contents of the shift
register (See Figure 34 ).
Bit 5 = Unused.
Bit 4 = MODF Mode Fault flag.
This bit is set by hardware when the SS pin is
pulled low in master mode (see Section 5.5.4.5
Master Mode Fault). An SPI interrupt can be generated if SPIE=1 in the CR register. This bit is
cleared by a software sequence (An access to the
SR register while MODF=1 followed by a write to
the CR register).
0: No master mode fault detected
1: A fault in master mode has been detected
Bits 3-0 = Unused.
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ST72251
SERIAL PERIPHERAL INTERFACE (Cont’d)
Table 17. SPI Register Map and Reset Values
Address
(Hex.)
21
22
23
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Register
Name
7
6
5
4
3
2
1
0
DR
Reset Value
CR
Reset Value
SR
Reset Value
D7
x
SPIE
0
SPIF
0
D6
x
SPE
0
WCOL
0
D5
x
SPR2
0
0
D4
x
MSTR
0
MODF
0
D3
x
CPOL
x
0
D2
x
CPHA
x
0
D1
x
SPR1
x
0
D0
x
SPR0
x
0
ST72251
5.6 8-BIT A/D CONVERTER (ADC)
5.6.1 Introduction
The on-chip Analog to Digital Converter (ADC) peripheral is a 8-bit, successive approximation converter with internal sample and hold circuitry. This
peripheral has up to 8 multiplexed analog input
channels (refer to device pin out description) that
allow the peripheral to convert the analog voltage
levels from up to 8 different sources.
The result of the conversion is stored in a 8-bit
Data Register. The A/D converter is controlled
through a Control/Status Register.
5.6.2 Main Features
■ 8-bit conversion
■ Up to 8 channels with multiplexed input
■ Linear successive approximation
■ Data register (DR) which contains the results
■ Conversion complete status flag
■ On/Off bit (to reduce consumption)
The block diagram is shown in Figure 39.
Figure 39. ADC Block Diagram
COCO
-
ADON
0
-
CH2
CH1
CH0
(Control Status Register) CSR
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
ANALOG
MUX
fCPU
SAMPLE
&
HOLD
ANALOG TO
DIGITAL
CONVERTER
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
(Data Register) DR
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ST72251
8-BIT A/D CONVERTER (ADC) (Cont’d)
5.6.3 Functional Description
The high level reference voltage VDDA must be
connected externally to the VDD pin. The low level
reference voltage VSSA must be connected externally to the VSS pin. In some devices (refer to device pin out description) high and low level reference voltages are internally connected to the VDD
and VSS pins.
Conversion accuracy may therefore be degraded
by voltage drops and noise in the event of heavily
loaded or badly decoupled power supply lines.
Figure 40. Recommended Ext. Connections
VDD
VDDA
0.1µF
VSSA
ST7
RAIN
VAIN
Px.x/AINx
Characteristics:
The conversion is monotonic, meaning the result
never decreases if the analog input does not and
never increases if the analog input does not.
If input voltage is greater than or equal to VDD
(voltage reference high) then results = FFh (full
scale) without overflow indication.
If input voltage ≤ VSS (voltage reference low) then
the results = 00h.
The conversion time is 64 CPU clock cycles including a sampling time of 31.5 CPU clock cycles.
RAIN is the maximum recommended impedance
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
alloted time.
The A/D converter is linear and the digital result of
the conversion is given by the formula:
255 x Input Voltage
Digital result =
Reference Voltage
Where Reference Voltage is VDD - VSS.
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The accuracy of the conversion is described in the
Electrical Characteristics Section.
Procedure:
Refer to the CSR and DR register description section for the bit definitions.
Each analog input pin must be configured as input,
no pull-up, no interrupt. Refer to the “I/O Ports”
chapter. Using these pins as analog inputs does
not affect the ability of the port to be read as a logic
input.
In the CSR register:
– Select the CH2 to CH0 bits to assign the analog channel to convert. Refer to Table 18.
– Set the ADON bit. Then the A/D converter is
enabled after a stabilization time (typically 30
µs). It then performs a continuous conversion
of the selected channel.
When a conversion is complete
– The COCO bit is set by hardware.
– No interrupt is generated.
– The result is in the DR register.
A write to the CSR register aborts the current conversion, resets the COCO bit and starts a new
conversion.
5.6.4 Low Power Modes
Note: The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced
power consumption when no conversion is needed.
Mode
WAIT
HALT
Description
No effect on A/D Converter
A/D Converter disabled.
After wakeup from Halt mode, the A/D
Converter requires a stabilisation time
before accurate conversions can be
performed.
5.6.5 Interrupts
None.
ST72251
8-BIT A/D CONVERTER (ADC) (Cont’d)
5.6.6 Register Description
CONTROL/STATUS REGISTER (CSR)
Read/Write
Reset Value: 0000 0000 (00h)
7
These bits are set and cleared by software. They
select the analog input to convert.
Table 18. Channel Selection
0
COCO
-
ADON
0
-
CH2
CH1
CH0
Bit 7 = COCO Conversion Complete
This bit is set by hardware. It is cleared by software reading the result in the DR register or writing
to the CSR register.
0: Conversion is not complete.
1: Conversion can be read from the DR register.
Pin*
CH2
CH1
CH0
AIN0
AIN1
0
0
0
0
0
1
AIN2
0
1
0
AIN3
0
1
1
AIN4
AIN5
1
1
0
0
0
1
AIN6
AIN7
1
1
1
1
0
1
*IMPORTANT NOTE: The number of pins AND
the channel selection vary according to the device.
REFER TO THE DEVICE PINOUT).
Bit 6 = Reserved. Must always be cleared.
Bit 5 = ADON A/D converter On
This bit is set and cleared by software.
0: A/D converter is switched off.
1: A/D converter is switched on.
Note: A typical 30 µs delay time is necessary for
the ADC to stabilize when the ADON bit is set.
DATA REGISTER (DR)
Read Only
Reset Value: 0000 0000 (00h)
7
0
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Bit 4 = Reserved. Forced by hardware to 0.
Bit 7:0 = AD[7:0] Analog Converted Value
This register contains the converted analog value
in the range 00h to FFh.
Reading this register resets the COCO flag.
Bit 3 = Reserved. Must always be cleared.
Bits 2:0: CH[2:0] Channel Selection
Table 19. ADC Register Map
Address
Register
Name
7
6
5
4
3
2
1
0
70
Reset Value
DR
AD7
0
AD6
0
AD5
0
AD4
0
AD3
0
AD2
0
AD1
0
AD0
0
71
Reset Value
CSR
COCO
0
0
ADON
0
0
0
0
CH2
0
CH1
0
CH0
0
(Hex.)
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ST72251
6 INSTRUCTION SET
6.1 ST7 ADDRESSING MODES
The ST7 Core features 17 different addressing
modes which can be classified in 7 main groups:
Addressing Mode
Example
Inherent
nop
Immediate
ld A,#$55
Direct
ld A,$55
Indexed
ld A,($55,X)
Indirect
ld A,([$55],X)
Relative
jrne loop
Bit operation
bset
byte,#5
The ST7 Instruction set is designed to minimize
the number of bytes required per instruction: To do
so, most of the addressing modes may be subdivided in two sub-modes called long and short:
– Long addressing mode is more powerful because it can use the full 64 Kbyte address space,
however it uses more bytes and more CPU cycles.
– Short addressing mode is less powerful because
it can generally only access page zero (0000h 00FFh range), but the instruction size is more
compact, and faster. All memory to memory instructions use short addressing modes only
(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
The ST7 Assembler optimizes the use of long and
short addressing modes.
Table 20. ST7 Addressing Mode Overview
Mode
Syntax
Pointer
Address
(Hex.)
Destination/
Source
Pointer
Size
(Hex.)
Length
(Bytes)
Inherent
nop
+0
Immediate
ld A,#$55
+1
Short
Direct
ld A,$10
00..FF
+1
Long
Direct
ld A,$1000
0000..FFFF
+2
No Offset
Direct
Indexed
ld A,(X)
00..FF
+ 0 (with X register)
+ 1 (with Y register)
Short
Direct
Indexed
ld A,($10,X)
00..1FE
+1
Long
Direct
Indexed
ld A,($1000,X)
0000..FFFF
Short
Indirect
ld A,[$10]
00..FF
00..FF
byte
+2
Long
Indirect
ld A,[$10.w]
0000..FFFF
00..FF
word
+2
Short
Indirect
Indexed
ld A,([$10],X)
00..1FE
00..FF
byte
+2
Long
Indirect
Indexed
ld A,([$10.w],X)
0000..FFFF
00..FF
word
+2
00..FF
byte
00..FF
byte
+2
1)
Relative
Direct
jrne loop
PC-128/PC+127
Relative
Indirect
jrne [$10]
PC-128/PC+127 1)
Bit
Direct
bset $10,#7
00..FF
Bit
Indirect
bset [$10],#7
00..FF
Bit
Direct
Relative
btjt $10,#7,skip
00..FF
Bit
Indirect
Relative
btjt [$10],#7,skip 00..FF
+1
+2
+1
+2
+2
00..FF
byte
+3
Note 1. At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx.
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ST72251
ST7 ADDRESSING MODES (Cont’d)
6.1.1 Inherent
All Inherent instructions consist of a single byte.
The opcode fully specifies all the required information for the CPU to process the operation.
Inherent Instruction
Function
NOP
No operation
TRAP
S/W Interrupt
WFI
Wait For Interrupt (Low Power
Mode)
HALT
Halt Oscillator (Lowest Power
Mode)
RET
Sub-routine Return
IRET
Interrupt Sub-routine Return
SIM
Set Interrupt Mask
RIM
Reset Interrupt Mask
SCF
Set Carry Flag
RCF
Reset Carry Flag
RSP
Reset Stack Pointer
LD
Load
CLR
Clear
PUSH/POP
Push/Pop to/from the stack
INC/DEC
Increment/Decrement
TNZ
Test Negative or Zero
CPL, NEG
1 or 2 Complement
MUL
Byte Multiplication
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
SWAP
Swap Nibbles
6.1.2 Immediate
Immediate instructions have two bytes, the first
byte contains the opcode, the second byte contains the operand value.
Immediate Instruction
Function
LD
Load
CP
Compare
BCP
Bit Compare
AND, OR, XOR
Logical Operations
ADC, ADD, SUB, SBC
Arithmetic Operations
6.1.3 Direct
In Direct instructions, the operands are referenced
by their memory address.
The direct addressing mode consists of two submodes:
Direct (short)
The address is a byte, thus requires only one byte
after the opcode, but only allows 00 - FF addressing space.
Direct (long)
The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after the opcode.
6.1.4 Indexed (No Offset, Short, Long)
In this mode, the operand is referenced by its
memory address, which is defined by the unsigned
addition of an index register (X or Y) with an offset.
The indirect addressing mode consists of three
sub-modes:
Indexed (No Offset)
There is no offset, (no extra byte after the opcode),
and allows 00 - FF addressing space.
Indexed (Short)
The offset is a byte, thus requires only one byte after the opcode and allows 00 - 1FE addressing
space.
Indexed (long)
The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode.
6.1.5 Indirect (Short, Long)
The required data byte to do the operation is found
by its memory address, located in memory (pointer).
The pointer address follows the opcode. The indirect addressing mode consists of two sub-modes:
Indirect (short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - FF addressing space, and
requires 1 byte after the opcode.
Indirect (long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
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ST72251
ST7 ADDRESSING MODES (Cont’d)
6.1.6 Indirect Indexed (Short, Long)
This is a combination of indirect and short indexed
addressing modes. The operand is referenced by
its memory address, which is defined by the unsigned addition of an index register value (X or Y)
with a pointer value located in memory. The pointer address follows the opcode.
The indirect indexed addressing mode consists of
two sub-modes:
Indirect Indexed (Short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte after the opcode.
Indirect Indexed (Long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
Table 21. Instructions Supporting Direct,
Indexed, Indirect and Indirect Indexed
Addressing Modes
Long and Short
Instructions
Function
LD
Load
CP
Compare
AND, OR, XOR
Logical Operations
ADC, ADD, SUB, SBC
Arithmetic Addition/subtraction operations
BCP
Bit Compare
Short Instructions Only
Functio n
CLR
Clear
INC, DEC
Increment/Decrement
TNZ
Test Negative or Zero
CPL, NEG
1 or 2 Complement
BSET, BRES
Bit Operations
BTJT, BTJF
Bit Test and Jump Operations
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
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SWAP
Swap Nibbles
CALL, JP
Call or Jump subroutine
6.1.7 Relative Mode (Direct, Indirect)
This addressing mode is used to modify the PC
register value by adding an 8-bit signed offset to it.
Available Relative Direct/
Indirect Instructions
Function
JRxx
Conditional Jump
CALLR
Call Relative
The relative addressing mode consists of two submodes:
Relative (Direct)
The offset follows the opcode.
Relative (Indirect)
The offset is defined in memory, of which the address follows the opcode.
ST72251
6.2 INSTRUCTION GROUPS
The ST7 family devices use an Instruction Set
consisting of 63 instructions. The instructions may
be subdivided into 13 main groups as illustrated in
the following table:
Load and Transfer
LD
CLR
Stack operation
PUSH
POP
Increment/Decrement
INC
DEC
Compare and Tests
CP
TNZ
BCP
XOR
Logical operations
AND
OR
Bit Operation
BSET
BRES
Conditional Bit Test and Branch
BTJT
BTJF
RSP
CPL
NEG
Arithmetic operations
ADC
ADD
SUB
SBC
MUL
Shift and Rotates
SLL
SRL
SRA
RLC
RRC
SWAP
SLA
Unconditional Jump or Call
JRA
JRT
JRF
JP
CALL
CALLR
NOP
Conditional Branch
JRxx
Interruption management
TRAP
WFI
HALT
IRET
Condition Code Flag modification
SIM
RIM
SCF
RCF
Using a pre-byte
The instructions are described with one to four
bytes.
In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are defined. These prebytes
modify the meaning of the instruction they precede.
The whole instruction becomes:
PC-2 End of previous instruction
PC-1 Prebyte
PC
Opcode
PC+1 Additional word (0 to 2) according to the
number of bytes required to compute the
effective address
RET
These prebytes enable instruction in Y as well as
indirect addressing modes to be implemented.
They precede the opcode of the instruction in X or
the instruction using direct addressing mode. The
prebytes are:
PDY 90 Replace an X based instruction using
immediate, direct, indexed, or inherent
addressing mode by a Y one.
PIX 92 Replace an instruction using direct, direct bit, or direct relative addressing
mode to an instruction using the corresponding indirect addressing mode.
It also changes an instruction using X
indexed addressing mode to an instruction using indirect X indexed addressing
mode.
PIY 91 Replace an instruction using X indirect
indexed addressing mode by a Y one.
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ST72251
INSTRUCTION GROUPS (Cont’d)
Mnemo
Description
Function/Example
Dst
Src
H
I
N
Z
C
ADC
Add with Carry
A=A+M+ C
A
M
H
N
Z
C
ADD
Addition
A=A+M
A
M
H
N
Z
C
AND
Logical And
A=A.M
A
M
N
Z
BCP
Bit compare A, Memory
tst (A . M)
A
M
N
Z
BRES
Bit Reset
bres Byte, #3
M
BSET
Bit Set
bset Byte, #3
M
BTJF
Jump if bit is false (0)
btjf Byte, #3, Jmp1
M
C
BTJT
Jump if bit is true (1)
btjt Byte, #3, Jmp1
M
C
CALL
Call subroutine
CALLR
Call subroutine relative
CLR
Clear
CP
Arithmetic Compare
tst(Reg - M)
reg
CPL
One Complement
A = FFH-A
DEC
Decrement
dec Y
reg, M
HALT
Halt
IRET
Interrupt routine return
Pop CC, A, X, PC
INC
Increment
inc X
JP
Absolute Jump
jp [TBL.w]
JRA
Jump relative always
JRT
Jump relative
JRF
Never jump
JRIH
Jump if ext. interrupt = 1
JRIL
Jump if ext. interrupt = 0
JRH
Jump if H = 1
H= 1?
JRNH
Jump if H = 0
H= 0?
JRM
Jump if I = 1
I=1?
JRNM
Jump if I = 0
I=0?
JRMI
Jump if N = 1 (minus)
N= 1?
JRPL
Jump if N = 0 (plus)
N= 0?
JREQ
Jump if Z = 1 (equal)
Z=1?
JRNE
Jump if Z = 0 (not equal)
Z=0?
JRC
Jump if C = 1
C= 1?
JRNC
Jump if C = 0
C= 0?
JRULT
Jump if C = 1
Unsigned <
JRUGE
Jump if C = 0
Jmp if unsigned >=
JRUGT
Jump if (C + Z = 0)
Unsigned >
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0
1
N
Z
C
reg, M
N
Z
1
reg, M
N
Z
N
Z
N
Z
M
0
jrf *
H
reg, M
I
C
ST72251
INSTRUCTION GROUPS (Cont’d)
Mnemo
Description
Function/Example
Dst
Src
JRULE
Jump if (C + Z = 1)
Unsigned <=
LD
Load
dst <= src
reg, M
M, reg
MUL
Multiply
X,A = X * A
A, X, Y
X, Y, A
NEG
Negate (2’s compl)
neg $10
reg, M
NOP
No Operation
OR
OR operation
A=A+M
A
M
POP
Pop from the Stack
pop reg
reg
M
pop CC
CC
M
M
reg, CC
H
I
N
Z
N
Z
0
H
C
0
I
N
Z
N
Z
N
Z
C
C
PUSH
Push onto the Stack
push Y
RCF
Reset carry flag
C=0
RET
Subroutine Return
RIM
Enable Interrupts
I=0
RLC
Rotate left true C
C <= Dst <= C
reg, M
N
Z
C
RRC
Rotate right true C
C => Dst => C
reg, M
N
Z
C
RSP
Reset Stack Pointer
S = Max allowed
SBC
Subtract with Carry
A=A-M-C
N
Z
C
SCF
Set carry flag
C=1
SIM
Disable Interrupts
I=1
SLA
Shift left Arithmetic
C <= Dst <= 0
reg, M
N
Z
C
SLL
Shift left Logic
C <= Dst <= 0
reg, M
N
Z
C
SRL
Shift right Logic
0 => Dst => C
reg, M
0
Z
C
SRA
Shift right Arithmetic
Dst7 => Dst => C
reg, M
N
Z
C
SUB
Subtraction
A=A-M
A
N
Z
C
SWAP
SWAP nibbles
Dst[7..4] <=> Dst[3..0] reg, M
N
Z
TNZ
Test for Neg & Zero
tnz lbl1
N
Z
TRAP
S/W trap
S/W interrupt
WFI
Wait for Interrupt
XOR
Exclusive OR
N
Z
0
0
A
M
1
1
M
1
0
A = A XOR M
A
M
85/100
84
ST72251
7 ELECTRICAL CHARACTERISTICS
7.1 ABSOLUTE MAXIMUM RATINGS
This product contains devices to protect the inputs
against damage due to high static voltages, however it is advisable to take normal precaution to
avoid application of any voltage higher than the
specified maximum rated voltages.
For proper operation it is recommended that VI
and VO be higher than VSS and lower than V DD.
Reliability is enhanced if unused inputs are connected to an appropriate logic voltage level (VDD
or VSS).
Symbol
VDD
Parameter
Supply Voltage
Power Considerations.The average chip-junction temperature, TJ, in Celsius can be obtained
from:
TJ=
TA + PD x RthJA
Where:TA = Ambient Temperature.
RthJA = Package thermal resistance
(junction-to ambient).
PD = PINT + PPORT.
PINT = IDD x VDD (chip internal power).
PPORT =Port power dissipation
determined by the user)
Value
Unit
-0.3 to 6.0
V
V
Analog Input Voltage (A/D Converter)
VSS - 0.3 to VDD + 0.3
VSS - 0.3 to VDD + 0.3
Output Voltage
VI
Input Voltage
VAI
VO
V
VSS - 0.3 to VDD + 0.3
V
Total Current into VDD (source)
Total Current out of VSS (sink)
80
mA
80
mA
TJ
Junction Temperature
150
°C
TSTG
Storage Temperature
-60 to 150
°C
IV DD
IVSS
Note: Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these conditions is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
86/100
85
ST72251
7.2 RECOMMENDED OPERATING CONDITIONS
Value
Symbol
Parameter
Test Condition s
Unit
Min.
TA
Operating Temperature
Typ.
Max.
1 Suffix Version
0
70
°C
6 Suffix Version
-40
85
°C
3 Suffix Version
-40
125
°C
VDD
Operating Supply Voltage
f OSC = 16 MHz (1 & 6 Suffix)
f OSC = 8 MHz
3.5
3.0
5.5
5.5
V
fOSC
Oscillator Frequency
V DD = 3.0V
V DD = 3.5V (1 & 6 Suffix)
01)
01)
8
16
MHz
Note 1: A/D operation and Oscillator start-up are not guaranteed below 1MHz.
Figure 41. Maximum Operating Frequency (Fmax) Versus Supply Voltage (VDD)
FUNCTIONALITY NOT GUARANTEED IN THIS AREA
FUNCTIONALITY NOT GUARANTEED IN THIS AREA
f OSC
FUNCTIONALITY GUARANTEED IN THIS AREA
FOR TEMPERATURE HIGHER THAN 85°C
[MHz]
16
8
4
Supplly Voltage
[V]
1
0
2.5
3
3.5
4
4.5
5
5.5
6
FUNCTIONALITY NOT GUARANTEED IN THIS AREA WITH RESONATOR
87/100
86
ST72251
7.3 DC ELECTRICAL CHARACTERISTICS
(TA = -40°C to +125°C and VDD = 5V unless otherwise specified)
Value
Symbol
Parameter
Test Conditions
Unit
Min.
VIL
VIH
VHYS
VOL
VOH
IIL
IIH
IIH
R PU
IDD
Input Low Level Voltage
All Input pins
Input High Level Voltage
All Input pins
Hysteresis Voltage 1)
All Input pins
Low Level Output Voltage
All Output pins
Low Level Output Voltage
High Sink I/O pins
High Level Output Voltage
All Output pins
Input Leakage Current
All Input pins but RESET 4)
Input Leakage Current
RESET pin
I/O Weak Pull-up R PU
Typ.
3V < VDD < 5.5V
3V < VDD < 5.5V
Max.
VDD x 0.3
VDD x 0.7
V
400
IOL = +10µA
IOL = + 2mA
IOL = +10µA
IOL = +10mA
IOL = + 15mA
IOL = + 20mA, TA < 85°C
IOH = - 10µA
IOH = - 2mA
VIN = VSS (No Pull-up configured)
VIN = VDD
VIN = VDD
VIN < VIL
fOSC = 4 MHz, fCPU = 2 MHz
Supply Current in
fOSC = 8 MHz, fCPU = 4 MHz
2)
RUN Mode
fOSC = 16 MHz, fCPU = 8 MHz
fOSC = 4 MHz, fCPU= 125 kHz
Supply Current in SLOW Mode 2) fOSC = 8 MHz, fCPU= 250 kHz
fOSC = 16 MHz, fCPU= 500 kHz
fOSC = 4MHz, fCPU = 2MHz
Supply Current in WAIT Mode 3) fOSC = 8MHz, fCPU = 4 MHz
fOSC = 16MHz, fCPU = 8 MHz
fOSC = 4 MHz, fCPU= 125 kHz
Supply Current in WAIT-MINIfOSC = 8 MHz, fCPU= 250 kHz
5)
MUM Mode
fOSC = 16 MHz, fCPU= 500 kHz
Supply Current in HALT Mode
ILOAD = 0mA, TA<85°C
ILOAD = 0mA, 85°C<TA<125°C
(ROM version)
Supply Current in HALT Mode
ILOAD = 0mA, TA<25°C
ILOAD = 0mA, 25°C<TA<125°C
(OTP version)
V
mV
0.1
0.4
0.1
1.5
3.0
3.0
4.9
4.2
V
V
0.1
1.0
0.1
1.0
µA
100
3
5.5
10
1.5
2.5
4
2
3.5
6
0.8
1
1.6
1
5
1
kΩ
6
11
20
3
5
8
4
7
12
1.5
2
3.5
10
20
10
50
mA
mA
mA
mA
µA
µA
Notes:
1. Hysteresis voltage between switching levels. Based on characterisation results, not tested.
2. CPU running with memory access, no DC load or activity on I/O’s; clock input (OSCIN) driven by external square wave.
3. No DC load or activity on I/O’s; clock input (OSCIN) driven by external square wave.
4. Except OSCIN and OSCOUT
5. WAIT Mode with SLOW Mode selected. Based on characterisation results, not tested.
88/100
87
ST72251
7.4 RESET CHARACTERISTICS
(TA=-40...+125oC and VDD=5V±10% unless otherwise specified.
Symbol
R ON
tRESET
tPULSE
Parameter
Reset Weak Pull-up RON
Condition s
VIN > VIH
VIN < VIL
Pulse duration generated by watchdog and POR reset
Minimum pulse duration to be applied on external RESET pin
Min
Typ 1)
Max
Unit
20
60
40
120
80
240
kΩ
µs
1
10 1)
ns
Note:
1) These values given only as design guidelines and are not tested.
7.5 OSCILLATOR CHARACTERISTICS
(TA = -40°C to +125°C unless otherwise specified)
Value
Symbol
Parameter
Test Conditions
Unit
Min.
gm
fOSC
tSTART
Oscillator transconductance
Crystal frequency
Osc. start up time
2
1
VDD = 5V±10%
Typ.
Max.
9
16
50
mA/V
MHz
ms
89/100
88
ST72251
7.6 A/D CONVERTER CHARACTERISTICS
(TA = -40°C to +125°C and VDD = 5V±10% unless otherwise specified )
Symbol
Parameter
Conditio ns
TSAMPLE
Sample Duration
Res
ADC Resolution
DLE
Differential Linearity Error*
ILE
Integral Linearity Error*
VAIN
Analog Input Voltage
IADC
Supply current rise
during A/D conversion
tSTAB
Stabilization time after ADC enable
tCONV
Conversion Time
R AIN
Resistance of analog sources
(VAIN)
C HOLD
Hold Capacitance
R SS
Resistance of sampling switch and
internal trace
Min
Typ
Max
31.5
fCPU=8MHz
VDD=VDDA=5V
Unit
1/fCPU
8
bit
±0.6
±1
±2
V SSA
VDDA
fCPU=8MHz
VDD=VDDA=5V
V
1
mA
30
µs
8
64
µs
1/f CPU
fCPU=8MHz, T=25°C,
VDD=VDDA=5V
15
ΚΩ
22
pF
2
ΚΩ
*Note: ADC Accuracy vs. Negative Injection Current:
For Iinj-=0.8mA, the typical leakage induced inside the die is 1.6µA and the effect on the ADC accuracy is
a loss of 1 LSB by 10KΩ increase of the external analog source impedance.
These measurement results and recommendations take worst case injection conditions into account:
- negative injection
- injection to an Input with analog capability, adjacent to the enabled Analog Input
- at 5V VDD supply, and worst case temperature.
V DD
Sampling
Switch
V T = 0.6V
R AIN
V AIN
C pin
VT
= input capacitance
= threshold voltage
SS
= sampling switch
C hold
= sample/hold
capacitance
leakage = leakage current
at the pin due
to various junctions
90/100
89
R SS
SS
Px.x/AINx
2ΚΩ
C pin
5pF
Chold
22 pF
VT = 0.6V
leakage max.
±1µA
VSS
ST72251
Figure 42. ADC conversion characteristics
Offset Error OSE
Gain Error GE
255
254
253
252
251
250
( 2)
code
out 7
1LS B
V
–V
ref P
ref M
= ---------------------------------------ideal
256
( 1)
6
5
(5)
4
(4)
3
(3)
2
1
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) Differential non-linearity error (DLE)
(4) Integral non-linearity error (ILE)
(5) Center of a step of the actual transfer curve
1 LSB (ideal)
0
1
2
3
Offset Error OSE
4
5
6
7
250 251 252 253 254 255 256
Vin(A) (LSBideal)
VR02133A
91/100
90
ST72251
7.7 SPI CHARACTERISTICS
Serial Peripheral Interface
Value
Ref.
Symbol
Parameter
Condition
Unit
Min.
Max.
1/4
1/2
fSPI
SPI frequency
Master
Slave
1/128
dc
1
tSPI
SPI clock period
Master
Slave
4
2
tCPU
2
tLead
Enable lead time
Slave
120
ns
3
tLag
Enable lag time
Slave
120
ns
100
90
ns
fCPU
4
tSPI_H
Clock (SCK) high time
Master
Slave
5
tSPI_L
Clock (SCK) low time
Master
Slave
100
90
ns
6
tSU
Data set-up time
Master
Slave
100
100
ns
7
tH
Data hold time (inputs)
Master
Slave
100
100
ns
8
tA
Access time (time to data active
from high impedance state)
9
tDis
10
tV
11
0
Disable time (hold time to high impedance state)
120
ns
240
ns
120
tCPU
ns
Slave
Data valid
Master (before capture edge)
Slave (after enable edge)
0.25
tHold
Data hold time (outputs)
Master (before capture edge)
Slave (after enable edge)
0.25
0
12
tRise
Outputs: SCK,MOSI,MISO
Rise time
(20% VDD to 70% VDD, CL = 200pF) Inputs: SCK,MOSI,MISO, SS
100
100
ns
µs
13
tFall
Outputs: SCK,MOSI,MISO
Fall time
(70% VDD to 20% VDD, CL = 200pF) Inputs: SCK,MOSI,MISO, SS
100
100
ns
µs
tCPU
ns
Measurement points are VOL, VOH, VIL and VIH in the SPI Timing Diagram
Figure 43. SPI Master Timing Diagram CPHA=0, CPOL=0
SS
(INPUT)
1
SCK
(OUTPUT)
4
MISO
(INPUT)
MOSI
(OUTPUT)
6
10
D7-IN
7
D7-OUT
11
13
12
5
D6-IN
D6-OUT
D0-IN
D0-OUT
VR000109
92/100
91
ST72251
SPI CHARACTERISTICS (Cont’d)
Measurement points are VOL, VOH, VIL and VIH in the SPI Timing Diagram
Figure 44. SPI Master Timing Diagram CPHA=0, CPOL=1
SS
(INPUT)
1
13
SCK
(OUTPUT)
5
MISO
(INPUT)
6
MOSI
(OUTPU T)
10
12
4
D7-IN
7
D6-IN
D7-OUT
11
D0-IN
D6-OUT
D0-OUT
VR000110
Figure 45. SPI Master Timing Diagram CPHA=1, CPOL=0
SS
(INPUT)
1
13
SCK
(OUTPUT)
4
MISO
(INPUT)
5
D7-OUT
6
MOSI
(OUTPU T)
12
10
D6-OUT
D0-OUT
7
D6-IN
D7-IN
11
D0-IN
VR000107
Figure 46. SPI Master Timing Diagram CPHA=1, CPOL=1
SS
(INPUT)
1
12
SCK
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
13
4
5
6
10
D7-IN
7
D7-OUT
11
D6-IN
D6-OUT
D0-IN
D0-OUT
VR000108
93/100
ST72251
SPI CHARACTERISTICS (Cont’d)
Measurement points are VOL, VOH, VIL and VIH in the SPI Timing Diagram
Figure 47. SPI Slave Timing Diagram CPHA=0, CPOL=0
SS
(INPUT)
2
1
12
13
SCK
(INPUT)
4
MISO HIGH-Z
(OUTPU T)
8
5
D7-OUT
D6-OUT
10
MOSI
(INPUT)
3
D0-OUT
11
D7-IN
9
D6-IN
D0-IN
7
6
VR000113
Figure 48. SPI Slave Timing Diagram CPHA=0, CPOL=1
SS
(INPUT)
1
2
SCK
(INPUT)
5
MISO
HIGH-Z
(OUTPU T)
8
MOSI
(INPUT)
13
12
3
4
D7-OUT
D6-OUT
10
D0-OUT
11
D7-IN
9
D6-IN
D0-IN
7
6
VR000114
Figure 49. SPI Slave Timing Diagram CPHA=1, CPOL=0
SS
(INPUT)
2
SCK
(INPUT)
HIGH-Z
MISO
(OUTPUT)
1
4
13
3
5
D7-OUT
D6-OUT
8
D7-IN
D0-OUT
11
10
MOSI
(INPUT)
12
9
D6-IN
D0-IN
7
6
VR000111
Figure 50. SPI Slave Timing Diagram CPHA=1, CPOL=1
SS
(INPUT)
2
SCK
(INPUT)
HIGH-Z
MISO
(OUTPUT)
MOSI
(INPUT)
1
5
12
3
4
D7-OUT
D6-OUT
D7-IN
D0-OUT
11
10
8
6
13
D6-IN
9
D0-IN
7
VR000112
94/100
ST72251
7.8 I2C CHARACTERISTICS
I2C-Bus Electrical specifications
Standard mode I2C
Symbol
Fast mode I2C
Parameter
Unit
Min
Max
Min
Max
V IL
Low level input voltage:
fixed input levels
VDD-related input levels
-0.5
-0.5
1.5
0.3 VDD
-0.5
-0.5
1.5
0.3 V DD
V
V IH
High level input voltage:
fixed input levels
VDD-related input levels
3.0
0.7 VDD
VDD+0.5
VDD+0.5
3.0
0.7 VDD
V DD+0.5
V DD+0.5
V
V HYS
Hysteresis of Schmitt trigger inputs
fixed input levels
VDD-related input levels
na
na
na
na
0.2
0,05 VDD
TSP
Pulse width of spikes which must be suppressed by
na
the input filter
na
0 ns
50 ns
V OL1
V OL2
Low level output voltage (open drain and open collector)
at 3 mA sink current
0
at 6 mA sink current
na
0.4
na
0
0
0.4
0.6
TOF
Output fall time from VIH min to VIL max with a bus
capacitor from 10 pF to 400 pF
with up to 3 mA sink current at VOL1
with up to 6 mA sink current at VOL2
na
250
na
20+0.1Cb 250
20+0.1Cb 250
I
Input current each I/O pin with an input voltage be- 10
tween 0.4V and 0.9 VDD max
10
-10
C
Capacitor for each I/O pin
10
V
ns
V
ns
10
µA
10
pF
Note: Cb = total capacitance of one bus line in pF.
I2C-Bus Timings
Standard I2C
Symbol
Fast I2C
Parameter
Unit
Min
Max
Min
Max
TBUF
Bus free time between a STOP and START condition
4.7
1.3
ms
THD:STA
Hold time START condition. After this period, the first clock
pulse is generated
4.0
0.6
µs
TLOW
LOW period of the SCL clock
4.7
1.3
µs
THIGH
HIGH period of the SCL clock
4.0
0.6
µs
TSU:STA
Set-up time for a repeated START condition
4.7
0.6
THD:DAT
Data hold time
0 (1)
0 (1)
TSU:DAT
Data set-up time
250
TR
Rise time of both SDA and SCL signals
TF
Fall time of both SDA and SCL signals
TSU:STO
Set-up time for STOP condition
Cb
Capacitive load for each bus line
µs
0.9 (2)
100
ns
1000
20+0.1Cb
300
300
20+0.1Cb
300
4.0
0.6
400
ns
ns
ns
ns
400
pF
Note 1: The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined
region of the falling edge of SCL
Note 2: The maximum hold time of the START condition has only to be met if the interface does not stretch the low period
of SCL signal
95/100
ST72251
8 GENERAL INFORMATION
8.1 EPROM ERASURE
EPROM version devices are erased by exposure
to high intensity UV light admitted through the
transparent window. This exposure discharges the
floating gate to its initial state through induced
photo current.
It is recommended that the EPROM devices be
kept out of direct sunlight, since the UV content of
sunlight can be sufficient to cause functional failure. Extended exposure to room level fluorescent
lighting may also cause erasure.
An opaque coating (paint, tape, label, etc...)
should be placed over the package window if the
product is to be operated under these lighting conditions. Covering the window also reduces IDD in
power-saving modes due to photo-diode leakage
currents.
An Ultraviolet source of wave length 2537 Å yielding a total integrated dosage of 15 Watt-sec/cm2 is
required to erase the device. It will be erased in 15
to 20 minutes if such a UV lamp with a 12mW/cm2
power rating is placed 1 inch from the device window without any interposed filters.
8.2 PACKAGE MECHANICAL DATA
Figure 51. 28-Pin Plastic Small Outline Package, 300-mil Width
Dim.
D
mm
Min
Typ
inches
Max
Min
Typ
A1
A
C
a
B
e
A
2.35
2.65 0.093
0.104
A1
0.10
0.30 0.004
0.012
B
0.33
0.51 0.013
0.020
C
0.23
0.32 0.009
0.013
D
17.70
18.10 0.697
0.713
E
7.40
e
E H
7.60 0.291
1.27
0.299
0.050
H
10.00
10.65 0.394
0.419
h
0.25
0.75 0.010
0.030
α
0°
L
0.40
8°
0°
1.27 0.016
Number of Pins
N
96/100
Max
h x 45×
L
L
28
8°
0.050
ST72251
Figure 52. 32-Pin Plastic Dual In-Line Package, Shrink 400-mil Width
Dim.
E
A2 A
A1
L
E1
C
b
b2
e
eA
eB
D
mm
inches
Min
Typ
Max
A
3.56
3.76
5.08 0.140 0.148 0.200
A1
0.51
A2
3.05
3.56
4.57 0.120 0.140 0.180
eC
Min
Typ
Max
0.020
b
0.36
0.46
0.58 0.014 0.018 0.023
b1
0.76
1.02
1.40 0.030 0.040 0.055
C
0.20
0.25
0.36 0.008 0.010 0.014
D
27.43
E
9.91 10.41 11.05 0.390 0.410 0.435
E1
7.62
28.45 1.080 1.100 1.120
8.89
9.40 0.300 0.350 0.370
e
1.78
0.070
eA
10.16
0.400
eB
12.70
0.500
eC
1.40
0.055
L
2.54
3.05
3.81 0.100 0.120 0.150
Number of Pins
N
32
Figure 53. 32-Pin Shrink Ceramic Dual In-Line Package
Dim.
mm
Min
Typ
A
Min
Typ
3.63
Max
0.143
A1
0.38
B
0.36
0.46
0.58 0.014 0.018 0.023
B1
0.64
0.89
1.14 0.025 0.035 0.045
C
0.20
0.25
0.36 0.008 0.010 0.014
D
29.41 29.97 30.53 1.158 1.180 1.202
0.015
D1
26.67
1.050
E
10.16
0.400
E1
CDIP32SW
inches
Max
9.45
9.91 10.36 0.372 0.390 0.408
e
1.78
G
9.40
0.070
0.370
G1
14.73
0.580
G2
1.12
0.044
L
3.30
0.130
Ø
7.37
0.290
Number of Pins
N
32
97/100
ST72251
8.3 ORDERING INFORMATION
Each device is available for production in user programmable version (OTP) as well as in factory
coded version (ROM). OTP devices are shipped to
customer with a default blank content FFh, while
ROM factory coded parts contain the code sent by
customer. There is one common EPROM version
for debugging and prototyping which features the
maximum memory size and peripherals of the
family. Care must be taken to only use resources
available on the target device.
8.3.1 Transfer Of Customer Code
Customer code is made up of the ROM contents
and the list of the selected options (if any). The
ROM contents are to be sent on diskette, or by
electronic means, with the hexadecimal file in .S19
format generated by the development tool. All unused bytes must be set to FFh.
The selected options are communicated to STMicroelectronics using the correctly completed OPTION LIST appended.
The STMicroelectronics Sales Organization will be
pleased to provide detailed information on contractual points.
Figure 54. ROM Factory Coded Device Types
TEMP.
DEVICE PACKAGE RANGE / XXX
Code name (defined by STMicroelectronics)
1 = standard 0 to +70°C
3 = automotive -40 to +125°C
6 = industrial -40 to +85°C
B = Plastic DIP
M = Plastic SOIC
ST72251G1
ST72251G2
Figure 55. OTP User Programmable Device Types
TEMP.
DEVICE PACKAGE RANGE
XXX
Option (if any)
3 = automotive -40 to +125°C
6 = industrial -40 to +85°C
B = Plastic DIP
M = Plastic SOIC
ST72T251G1
ST72T251G2
Note: The ST72E251G2D0 (CERDIP 25 °C) is used as the EPROM version for the above devices.
98/100
ST72251
ST72251 MICROCONTROLLER OPTION LIST
Customer
Address
. . ... ... . .. .. . .. .. .. . .. ... . ..
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Contact
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Phone No . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STMicroelectronics references
Device:
[ ] ST72251
Package:
[ ] Dual in Line Plastic [ ] Small Outline Plastic with conditionning:
[ ] Standard (Stick)
[ ] Tape & Reel
Temperature Range:
[ ] 0°C to + 70°C
[ ] - 40°C to + 85°C
[ ] - 40°C to + 125°C
Special Marking:
[ ] No
[ ] Yes ”_ _ _ _ _ _ _ _ _ _ _ ”
Authorized characters are letters, digits, ’.’, ’-’, ’/’ and spaces only.
Maximum character count: SDIP32:
10
SO28:
8
Comments :
Supply Operating Range in the application:
Oscillator Fequency in the application:
Notes
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Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Date
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ST72251
9 SUMMARY OF CHANGES
Change Description (Rev. 1.5 to 1.6)
Page
Added new External Connections section
Removed RP external resistor .
Changed ORed to ANDed in External interrupts paragraph, to read “If several input pins, connected to the same interrupt vector, are configured as interrupts, their signals are logically ANDed before entering the edge/level detection block”.
8
15
Added note ”Any modification of one of these two bits resets the interrupt request related to
this interrupt vector.”
Added clamping diodes to I/O pin figure and table
Added sections on low power modes and interrupts to peripheral descriptions
Changed 16-bit timer Chapter
Added details to description of FOLV1 and FOLV2 bits
Added ADC recommended external connections
Added Reset characteristics section
Added figure to ADC electrical characteristics section
17 and 23
22
25
30,42,54,72,77
31 to 47
43
77
88
89
Change Description (Rev. 1.6 to 1.7)
SPR2 bit reinstated in SPI chapter
63 to 75
Change Description (Rev. 1.7 to 1.8) of 31 May 2001
SPI frequency changed from fCPU/2 to fCPU/4 in Table 16
74
Change Description (Rev. 1.8 to 1.9) of 7 June 2001
Changed section 7.3 on page 88 (IDD value for OTP versions).
88
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.
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2001 STMicroelectronics - All Rights Reserved.
Purchase of I2 C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an
I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips.
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