ST95022
2 Kbit Serial SPI EEPROM with High Speed Clock
HIGH SPEED CLOCK RATE:
– 2.1 MHz Max
1,000,000 ERASE/WRITE CYCLES
40 YEARS DATA RETENTION
SINGLE 4.5V to 5.5V SUPPLY VOLTAGE
SPI BUS COMPATIBLE SERIAL INTERFACE
BLOCK WRITE PROTECTION
STATUS REGISTER
16 BYTE PAGE MODE
WRITE PROTECT
SELF-TIMED PROGRAMMING CYCLE
E.S.D.PROTECTION GREATER than 4000V
SUPPORTS POSITIVE CLOCK SPI MODES
8
1
SO8 (M)
150mil Width
Figure 1. Logic Diagram
DESCRIPTION
The ST95022 is an high speed 2 Kbit Electrically
Erasable Programmable Memory (EEPROM) fabricated with STMicroelectronics’s High Endurance
Single Polysilicon CMOS technology. The memory
is accessed by a simple SPI bus compatible serial
interface. The bus signals are a serial clock input
(C), a serial data input (D) and a serial data output
(Q).
VCC
D
Q
C
Table 1. Signal Names
C
Serial Clock
D
Serial Data Input
Q
Serial Data Output
S
Chip Select
W
Write Protect
HOLD
Hold
VCC
Supply Voltage
VSS
Ground
February 1999
S
ST95022
W
HOLD
VSS
AI01722
1/16
ST95022
Table 2. Absolute Maximum Ratings (1)
Symbol
Parameter
TA
(2)
Ambient Operating Temperature
TSTG
Storage Temperature
TLEAD
Lead Temperature, Soldering
VO
Output Voltage
VI
VCC
VESD
(SO8 package)
40 sec
Value
Unit
–40 to 125
°C
–65 to 150
°C
215
°C
–0.3 to VCC +0.6
V
Input Voltage with respect to Ground
–0.3 to 6.5
V
Supply Voltage
–0.3 to 6.5
V
Electrostatic Discharge Voltage (Human Body model) (3)
Electrostatic Discharge Voltage (Machine model)
(4)
4000
V
500
V
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and
other relevant quality documents.
2. Depends on range.
3. MIL-STD-883C, 3015.7 (100pF, 1500Ω)
4. EIAJ IC-121 (Condition C) (200pF, 0Ω)
Figure 2B. SO Pin Connections
ST95022
S
Q
W
VSS
1
2
3
4
8
7
6
5
VCC
HOLD
C
D
AI01723
DESCRIPTION (cont’d)
The device connected to the bus is selected when
the chip select input (S) goes low. Communications
with the chip can be interrupted with a hold input
(HOLD). The write operation is disabled by a write
protect input (W).
Data is clocked in during the low to high transition
of clock C, data is clocked out during the high to
low transition of clock C.
2/16
SIGNALS DESCRIPTION
Serial Output (Q). The output pin is used to transfer data serially out of the ST95022. Data is shifted
out on the falling edge of the serial clock.
Serial Input (D). The input pin is used to transfer
data serially into the device. It receives instructions,
addresses, and the data to be written. Input is
latched on the rising edge of the serial clock.
Serial Clock (C). The serial clock provides the
timing of the serial interface. Instructions, addresses, or data present at the input pin are latched
on the rising edge of the clock input, while data on
the Q pin changes after the falling edge of the clock
input.
Chip Select (S). When S is high, the ST95022 is
deselected and the D output pin is at high impedance and, unless an internal write operation is
underway the ST95022 will be in the standby power
mode. S low enables the ST95022, placing it in the
active power mode. It should be noted that after
power-on, a high to low transition on S is required
prior to the start of any operation.
Write Protect (W). This pin is for hardware write
protection. When W is low, writes to the ST95022
memory are disabled but any other operations stay
enabled. When W is high, all writes operations are
available. W going low at any time before the last
bit D0 of the data stream will reset the write enable
latch and prevent programming. No action on W or
on the write enable latch can interrupt a write cycle
which has commenced.
ST95022
Figure 3. Data and Clock Timing
CPOL
CPHA
0
0
C
1
1
C
D or Q
MSB
LSB
AI01438
Figure 4. Microcontroller and SPI Interface Set-up
MICROCONTROLLER
(ST6, ST7, ST9)
SCK
SPI Interface with
(CPOL, CPHA) =
('0', '0') or ('1', '1')
SDI
SDO
C
ST95xx0
Q
D
AI01439
Hold (HOLD). The HOLD pin is used to pause
serial communications with a ST95022 without resetting the serial sequence. To take the Hold condition into account, the product must be selected
(S = 0). Then the Hold state is validated by a high
to low transition on HOLD when C is low. To resume
the communications, HOLD is brought high while
C is low. During the Hold condition D, Q, and C are
at a high impedance state.
When the ST95022 is under the Hold condition, it
is possible to deselect the device. However, the
serial communications will remain paused after a
reselect, and the chip will be reset.
The ST95022 can be driven by a microcontroller
with its SPI peripheral running in either of the two
following modes: (CPOL, CPHA) = (’0’, ’0’) or
(CPOL, CPHA) = (’1’, ’1’).
For these two modes, input data is latched in by the
low to high transition of clock C, and output data is
available from the high to low transition of Clock
(C).
The difference between (CPOL, CPHA) = (0, 0) and
(CPOL, CPHA) = (1, 1) is the stand-by polarity: C
remains at ’0’ for (CPOL, CPHA) = (0, 0) and C
remains at ’1’ for (CPOL, CPHA) = (1, 1) when there
is no data transfer.
3/16
ST95022
OPERATIONS
All instructions, addresses and data are shifted in
and out of the chip MSB first. Data input (D) is
sampled on the first rising edge of clock (C) after
the chip select (S) goes low. Prior to any operation,
a one-byte instruction code must be entered in the
chip. This code is entered via the data input (D),
and latched on the rising edge of the clock input
(C). To enter an instruction code, the product must
have been previously selected (S = low). Table 3
shows the instruction set and format for device
operation. If an invalid instruction is sent (one not
contained in Table 3), the chip is automatically
deselected.
Write Enable (WREN) and Write Disable (WRDI)
The ST95022 contains a write enable latch. This
latch must be set prior to every WRITE or WRSR
operation. The WREN instruction will set the latch
and the WRDI instruction will reset the latch. The
latch is reset under the following conditions:
– W pin is low
– Power on
– WRDI instruction executed
– WRSR instruction executed
– WRITE instruction executed
As soon as the WREN or WRDI instruction is
received by the ST95022, the circuit executes the
instruction and enters a wait mode until it is deselected.
Read Status Register (RDSR)
The RDSR instruction provides access to the status
register. The status register may be read at any
time, even during a write to the memory operation.
As soon as the 8th bit of the status register is read
out, the ST95022 enters a wait mode (data on D is
not decoded, Q is in Hi-Z) until it is deselected.
The status register format is as follows:
b7
1
b0
1
1
1
BP1
BP0
WEL
BP1, BP0: Read and write bits.
WEL, WIP: Read only bits.
b7 to b4: Read only bits.
During a write to the memory operation to the
memory array, all bits BP1, BP0, WEL, WIP are
valid and can be read. During a write to the status
register, only the bits WEL and WIP are valid and
can be read. The values of BP1 and BP0 read at
that time correspond to the previous contents of the
status register.
The Write-In-Process (WIP) read-only bit indicates
whether the ST95022 is busy with a write operation. When set to a ’1’ a write is in progress, when
set to a ’0’ no write is in progress.
The Write Enable Latch (WEL) read-only bit indicates the status of the write enable latch. When set
to a ’1’ the latch is set, when set to a ’0’ the latch is
reset. The Block Protect (BP0 and BP1) bits indicate the extent of the protection employed. These
bits are set by the user issuing the WRSR instruction. These bits are non-volatile.
Write Status Register (WRSR)
The WRSR instruction allows the user to select the
size of protected memory. The ST95022 is divided
into four 512 bit blocks. The user may read the
blocks but will be unable to write within the pro-
Table 3. Instruction Set
Instruction
4/16
Description
Instruction Format
WREN
Set Write Enable Latch
0000 0110
WRDI
Reset Write Enable Latch
0000 0100
RDSR
Read Status Register
0000 0101
WRSR
Write Status Register
0000 0001
READ
Read Data from Memory Array
0000 0011
WRITE
Write Data to Memory Array
0000 0010
Notes: A = 1, Upper page selected
A = 0, Lower page selected
WIP
ST95022
Figure 5. Block Diagram
HOLD
W
High Voltage
Generator
Control Logic
S
C
D
I/O Shift Register
Q
Address Register
and Counter
Data
Register
Status
Y Decoder
Block
Protect
16 Bytes
X Decoder
AI01272
tected blocks. The blocks and respective WRSR
control bits are shown in Table 4.
When the WRSR instruction and the 8 bits of the
Status Register are latched-in, the internal write
cycle is then triggered by the rising edge of S.
This rising edge of S must appear no later than the
16th clock cycle of the WRSR instruction of the
Status Register content (it must not appear a 17th
clock pulse before the rising edge of S), otherwise
the internal write sequence is not performed.
Table 4. Write Protected Block Size
Status Register
Bits
Array
Addresses
Protected
Protected
Block
BP1
BP0
0
0
none
none
0
1
C0h - FFh
Upper quarter
1
0
80h - FFh
Upper half
1
1
00h - FFh
Whole memory
5/16
ST95022
Figure 6. Read Operation Sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
C
INSTRUCTION
BYTE ADDRESS
A7 A6 A5 A4 A3 A2 A1 A0
D
DATA OUT
HIGH IMPEDANCE
Q
7
6
5
4
3
2
1
0
AI01558
Read Operation
The chip is first selected by putting S low. The serial
one byte read instruction is followed by a one byte
address (A7-A0), each bit being latched-in during
the rising edge of the clock (C). Then the data
stored in the memory at the selected address is
shifted out on the Q output pin; each bit being
shifted out during the falling edge of the clock (C).
The data stored in the memory at the next address
can be read in sequence by continuing to provide
clock pulses. The byte address is automatically
incremented to the next higher address after each
byte of data is shifted out. When the highest address is reached, the address counter rolls over to
0h allowing the read cycle to be continued indefinitely. The read operation is terminated by deselecting the chip. The chip can be deselected at any
time during data output. Any read attempt during a
write cycle will be rejected and will deselect the
chip.
6/16
Byte Write Operation
Prior to any write attempt, the write enable latch
must be set by issuing the WREN instruction. First
the device is selected (S = low) and a serial WREN
instruction byte is issued. Then the product is deselected by taking S high. After the WREN instruction byte is sent, the ST95022 will set the write
enable latch and then remain in standby until it is
deselected. Then the write state is entered by
selecting the chip, issuing two bytes of instruction
and address, and one byte of data.
Chip Select (S) must remain low for the entire
duration of the operation. The product must be
deselected just after the eighth bit of data has been
latched in. If not, the write process is cancelled. As
soon as the product is deselected, the self-timed
write cycle is initiated. While the write is in progress,
the status register may be read to check BP1, BP0,
WEL and WIP. WIP is high during the self-timed
write cycle. When the cycle is completed, the write
enable latch is reset.
ST95022
Figure 7. Write Enable Latch Sequence
S
1
0
2
3
4
5
6
7
C
D
HIGH IMPEDANCE
Q
AI01441
Figure 8. Byte Write Operation Sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
C
INSTRUCTION
BYTE ADDRESS
A7 A6 A5 A4 A3 A2 A1 A0 7
D
DATA BYTE
6
5
4
3
2
1
0
HIGH IMPEDANCE
Q
AI01559
7/16
ST95022
Figure 9. Page Write Operation Sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
C
INSTRUCTION
BYTE ADDRESS
DATA BYTE 1
A7 A6 A5 A4 A3 A2 A1 A0 7
D
6
5
4
3
2
1
0
7
143
142
141
140
139
138
137
136
15+8N
14+8N
13+8N
12+8N
11+8N
10+8N
9+8N
24 25 26 27 28 29 30 31
8+8N
S
C
DATA BYTE N
DATA BYTE 2
7
D
6
5
4
3
2
1
0
7
6
5
4
3
2
DATA BYTE 16
1
0
7
6
5
4
3
2
1
0
AI01560
Figure 10. RDSR: Read Status Register Sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
INSTRUCTION
D
STATUS REG. OUT
HIGH IMPEDANCE
Q
7
6
5
4
3
2
1
0
MSB
AI01444
8/16
ST95022
Figure 11. WRSR: Write Status Register Sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
INSTRUCTION
STATUS REG.
D
HIGH IMPEDANCE
Q
AI01445
Page Write Operation
A maximum of 16 bytes of data may be written
during one non-volatile write cycle. All 16 bytes
must reside on the same page. The page write
mode is the same as the byte write mode except
that instead of deselecting the device after the first
byte of data, up to 15 additional bytes can be shifted
in prior to deselecting the chip. A page address
begins with address xxxx 0000 and ends with xxxx
1111. If the address counter reaches xxxx 1111 and
the clock continues, the counter will roll over to the
first address of the page (xxxx 0000) and overwrite
any previously written data. The programming cycle will only start if the S transition occurs just after
the eighth bit of data of a word is received.
POWER ON STATE
After a Power up the ST95022 is in the following
state:
– The device is in the low power standby state.
– The chip is deselected.
– The chip is not in hold condition.
– The write enable latch is reset.
– BP1 and BP0 are unchanged (non-volatile
bits).
DATA PROTECTION AND PROTOCOL SAFETY
– All inputs are protected against noise, see Table 5.
– Non valid S and HOLD transitions are not
taken into account.
– S must come high at the proper clock count in
order to start a non-volatile write cycle (in the
memory array or in the cycle status register),
that is the Chip Select S must rise during the
clock pulse following the introduction of a multiple of 8 bits.
– Access to the memory array during non-volatile programming cycle is ignored; however,
the programming cycle continues.
– After any of the operations WREN, WRDI,
RDSR is completed, the chip enters a wait
state and waits for a deselect.
– The write enable latch is reset upon power-up.
– The write enable latch is reset when W is
brought low.
INITIAL DELIVERY STATE
The device is delivered with the memory array in a
fully erased state (all data set at all "1’s" or FFh).
The block protect bits are initialized to 00.
9/16
ST95022
Table 5. AC Measurement Conditions
Figure 12. AC Testing Input Output
Waveforms
Input Rise and Fall Times
≤ 50ns
Input Pulse Voltages
0.2VCC to 0.8VCC
Input and Output Timing
Reference Voltages
0.3VCC to 0.7VCC
Output Load
CL = 100pF
0.8VCC
0.7VCC
0.3VCC
0.2VCC
AI00825
Note that Output Hi-Z is defined as the point where data is no
longer driven.
Table 6. Input Parameters (1) (TA = 25 °C, f = 2.1 MHz )
Symbol
Parameter
Min
Max
Unit
CIN
Input Capacitance (D)
8
pF
CIN
Input Capacitance (other pins)
6
pF
tLPF
Input Signal Pulse Width Filtered Out
10
ns
Note: 1. Sampled only, not 100% tested.
Table 7. DC Characteristics
(TA = –40 to 125°C; VCC = 4.5V to 5.5V)
Symbol
Parameter
Test Condition
Min
Max
Unit
ILI
Input Leakage Current
2
µA
ILO
Output Leakage Current
±2
µA
ICC
VCC Supply Current (Active)
C = 0.1 VCC/0.9 VCC ,
fC = 2.1 MHz, Q = Open
2
mA
ICC1
VCC Supply Current (Standby)
S = VCC, VIN = VSS or VCC
50
µA
VIL
Input Low Voltage
– 0.3
0.3 VCC
V
VIH
Input High Voltage
0.7 VCC
VCC + 1
V
VOL (1)
Output Low Voltage
IOL = 2mA
0.4
V
Output High Voltage
IOH = –2mA
VOH
(1)
Note: 1. The device meets output requirements for both TTL and CMOS standards.
10/16
VCC –0.6
V
ST95022
Table 8. AC Characteristics
(TA = –40 to 125°C; VCC = 4.5V to 5.5V)
Symbol
Alt
fC
fC
tSLCH
tCSS
tCHSL
Parameter
Test Condition
Min
Max
Unit
Clock Frequency
D.C.
2.1
MHz
S Active Setup Time (relative to
the rising edge of C)
100
ns
S Not Active Hold Time (relative
to the rising edge of C)
100
ns
tCH (1)
tCLH
Clock High Time
190
ns
tCL(1)
tCLL
Clock Low Time
190
ns
tCLCH
tRC
Clock Rise Time
1
µs
tCHCL
tFC
Clock Fall Time
1
µs
tDVCH
tDSU
Data In Setup Time
50
ns
tCHDX
tDH
Data In Hold Time
50
ns
tDLDH
tRI
Data In Rise Time
1
µs
tDHDL
tFI
Data In Fall Time
1
µs
tHHCH
tHSU
HOLD Setup Time
100
ns
Clock Low Hold Time after HOLD
Active
100
ns
HOLD Hold Time
80
ns
tCLHH
Clock Low Set-up Time before
HOLD Inactive
100
ns
tCHSH
S Active Hold Time (relative to the
rising edge of C)
200
ns
tSHCH
S Not Active Setup Time (relative
to the rising edge of C)
100
ns
200
ns
tHLCH
tCLHL
tHH
tSHSL
tCSH
S Deselect Time
tSHQZ
tDIS
Output Disable Time
150
ns
tCLQV
tV
Clock Low to Output Valid
240
ns
tCLQX
tHO
Output Hold Time
tQLQH (2)
tRO
Output Rise Time
100
ns
(2)
tFO
Output Fall Time
100
ns
tHHQX
tLZ
HOLD High to Output Low-Z
100
ns
tHLQZ
tHZ
HOLD Low to Output High-Z
200
ns
tW
tWP
Write Cycle Time
7
ms
tQHQL
0
ns
Notes: 1. tCH + tCL ≥ 1/fc
2. Value guaranteed by characterization, not 100% tested in production.
11/16
ST95022
Figure 13. Serial Input Timing
tSHSL
S
tSLCH
tCHSL
tCHSH
tSHCH
C
tDVCH
tCHCL
tCHDX
D
Q
tCLCH
LSB IN
MSB IN
HIGH IMPEDANCE
tDLDH
tDHDL
AI01447
Figure 14. Hold Timing
S
tHLCH
tCLHL
tHHCH
C
tCLHH
tHLQZ
tHHQX
Q
D
HOLD
AI01448
12/16
ST95022
Figure 15. Output Timing
S
tCH
C
tCLQV
tCL
tSHQZ
tCLQX
LSB OUT
Q
tQLQH
tQHQL
D ADDR.LSB IN
AI01449B
Figure 16. EEPROM and SPI Bus
D
Q
C
MASTER
CS3
CS2
CS1
C Q D
C Q D
C Q D
ST95xxx
ST95xxx
ST95xxx
S
S
S
AI01446
13/16
ST95022
ORDERING INFORMATION SCHEME
Example:
ST95022
Data Strobe
2
Note 1
Package
M
SO8
150mil Width
M
3
TR
Temperature Range
3
–40 to 125 °C
Option
TR
Tape & Reel
Packing
Note: 1. Data In is strobed on rising edge of the clock (C) and Data Out is synchronized from the falling edge of the clock.
Devices are shipped from the factory with the memory content set at all "1’s" (FFh).
For a list of available options (Package, etc...) or for further information on any aspect of this device, please
contact the STMicroelectronics Sales Office nearest to you.
14/16
ST95022
SO8 - 8 lead Plastic Small Outline, 150 mils body width
mm
Symb
Typ
inches
Min
Max
A
1.35
A1
Min
Max
1.75
0.053
0.069
0.10
0.25
0.004
0.010
B
0.33
0.51
0.013
0.020
C
0.19
0.25
0.007
0.010
D
4.80
5.00
0.189
0.197
E
3.80
4.00
0.150
0.157
–
–
–
–
H
5.80
6.20
0.228
0.244
h
0.25
0.50
0.010
0.020
L
0.40
0.90
0.016
0.035
α
0°
8°
0°
8°
N
8
e
1.27
Typ
0.050
8
CP
0.10
0.004
h x 45˚
A
C
B
CP
e
D
N
E
H
1
A1
α
L
SO-a
Drawing is not to scale.
15/16
ST95022
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
© 1999 STMicroelectronics - All Rights Reserved
All other names are the property of their respective owners
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
http://www.st.com
16/16