STC Very Low Power/Voltage CMOS SRAM 256K X 8 bit FEATURES STC62WV2568 • Fully static operation • Data retention supply voltage as low as 1.5V • Easy expansion with CE2, CE1, and OE options • Wide Vcc operation voltage : 2.4V~5.5V • Very low power consumption : Vcc = 3.0V C-grade : 22mA (@55ns) operating current I- grade : 23mA (@55ns) operating current C-grade : 17mA (@70ns) operating current I- grade : 18mA (@70ns) operating current 0.3uA (Typ.) CMOS standby current Vcc = 5.0V C-grade : 53mA (@55ns) operating current I- grade : 55mA (@55ns) operating current C-grade : 43mA (@70ns) operating current I- grade : 45mA (@70ns) operating current 1.0uA (Typ.) CMOS standby current • High speed access time : -55 55ns -70 70ns • Automatic power down when chip is deselected • Three state outputs and TTL compatible DESCRIPTION The STC62WV2568 is a high performance, very low power CMOS Static Random Access Memory organized as 262,144 words by 8 bits and operates from a wide range of 2.4V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.3uA at 3.0V /25oC and maximum access time of 55ns at 3.0V /85oC. Easy memory expansion is provided by an active LOW chip enable (CE1), an active HIGH chip enable (CE2), and active LOW output enable (OE) and three-state output drivers. The STC62WV2568 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The STC62WV2568 is available in DICE form, JEDEC standard 32 pin 450mil Plastic SOP, 8mmx13.4mm STSOP and 8mmx20mm TSOP. PRODUCT FAMILY PRODUCT FAMILY OPERATING TEMPERATURE Vcc RANGE POWER DISSIPATION STANDBY Operating SPEED ( ns ) ( ICCSB1, Max ) 55ns :3.0~5.5V 70ns :2.7~5.5V STC62WV2568DC STC62WV2568TC +0 O C to +70 O C STC62WV2568STC STC62WV2568SC STC62WV2568DI STC62WV2568TI -40 O C to +85 O C STC62WV2568STI STC62WV2568SI • 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 32 2 31 3 30 4 29 5 28 6 27 7 STC62WV2568S 26 8 STC62WV2568SI 25 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 • A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND STC62WV2568TC STC62WV2568STC STC62WV2568TI STC62WV2568STI Vcc=5.0V Vcc=3.0V 70ns Vcc=5.0V 70ns 2.4V ~5.5V 55/70 3.0uA 10uA 17mA 43mA 2.4V ~ 5.5V 55/70 5.0uA 30uA 18mA 45mA DICE TSOP-32 STSOP-32 SOP-32 DICE TSOP-32 STSOP-32 SOP-32 BLOCK DIAGRAM PIN CONFIGURATIONS A11 A9 A8 A13 WE CE2 A15 VCC A17 A16 A14 A12 A7 A6 A5 A4 PKG TYPE ( ICC, Max ) Vcc=3.0V 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 DQ7 DQ6 DQ5 DQ4 DQ3 OE A10 CE1 DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2 A3 A13 A17 A15 A16 A14 A12 A7 A6 A5 A4 Address Input Buffer 20 Row 1024 Memory Array 1024 x 2048 Decoder 2048 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 8 8 Data Input Buffer Data Output Buffer Column I/O 8 8 Write Driver Sense Amp 256 Column Decoder 16 CE1 CE2 WE OE Vdd Gnd Control Address Input Buffer A11 A9 A8 A3 A2 A1 A0 A10 STC International Limited. reserves the right to modify document contents without notice. STC62WV2568 1 Revision 1.1 Jan. 2004 STC STC62WV2568 PIN DESCRIPTIONS Name Function A0-A17 Address Input These 18 address inputs select one of the 262,144 x 8-bit words in the RAM CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when data read from or write to the device. If either chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive. DQ0-DQ7 Data Input/Output Ports These 8 bi-directional ports are used to read data from or write data into the RAM. Vcc Power Supply Gnd Ground TRUTH TABLE MODE WE CE1 CE2 OE Not selected (Power Down) X H X X X X L X I/O OPERATION Vcc CURRENT High Z I CCSB, I CCSB1 Output Disabled H L H H High Z I CC Read H L H L D OUT I CC Write L L H X D IN I CC ABSOLUTE MAXIMUM RATINGS(1) SYMBOL PARAMETER OPERATING RANGE RATING UNITS -0.5 to Vcc+0.5 V V TERM Terminal Voltage with Respect to GND TBIAS Temperature Under Bias -40 to +85 O TSTG Storage Temperature -60 to +150 O PT Power Dissipation 1.0 W I OUT DC Output Current 20 mA C RANGE AMBIENT TEMPERATURE Commercial 0 O C to +70 O C Industrial -40 C to +85 C O 2.4V ~ 5.5V 2.4V ~ 5.5V C CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz) SYMBOL 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. STC62WV2568 O Vcc 2 CIN CDQ PARAMETER Input Capacitance Input/Output Capacitance CONDITIONS MAX. UNIT VIN=0V 6 pF VI/O=0V 8 pF 1. This parameter is guaranteed and not 100% tested. Revision 1.1 Jan. 2004 STC STC62WV2568 DC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC ) PARAMETER NAME VIL VIH PARAMETER Guaranteed Input Low Voltage(3) Guaranteed Input High Voltage(3) Vcc=3.0V Vcc=5.0V Vcc = Max, VIN = 0V to Vcc ILO Output Leakage Current Vcc = Max, CE1 = VIH or CE2=VIL or OE = VIH, VI/O = 0V to Vcc VOL Output Low Voltage Vcc = Max, IOL = 2.0mA ICC (5) ICCSB ICCSB1(4) -- 2.0 2.2 -- ---- -- Vcc=5.0V Input Leakage Current Output High Voltage -0.5 Vcc=3.0V IIL VOH MIN. TYP. (1) MAX. TEST CONDITIONS Vcc=3.0V Vcc=5.0V Vcc=3.0V Vcc = Min, IOH = -1.0mA 0.8 V Vcc+0.3 V 1 uA -- 1 uA -- -- 0.4 V V 2.4 -- -- 70ns Vcc=3.0V -- -- 18 70ns Vcc=5.0V -- -- 45 Vcc=5.0V Operating Power Supply Current Vcc=Max,CE1=VIL, CE2=VIH IDQ = 0mA, F = Fmax(2) Standby Current-TTL Vcc = Max, CE1 = VIH or CE2=VIL IDQ = 0mA Vcc=3.0V -- -- 0.5 Vcc=5.0V -- -- 1.0 Vcc = Max, CE1≧Vcc-0.2V or CE2≦0.2V ;VIN≧ Vcc - 0.2V or VIN≦0.2V Vcc=3.0V -- 0.3 5 Vcc=5.0V -- 1.0 30 Standby Current-CMOS UNITS mA mA uA 1. Typical characteristics are at TA = 25oC. 2. Fmax = 1/tRC . 3. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 5. Icc_MAX. is 23mA(@3V) / 55mA(@5V) under 55ns operation. 4. IccsB1_MAX. is 3uA / 10uA at Vcc=3V / 5V and TA=70oC. DATA RETENTION CHARACTERISTICS ( TA = -40oC to + 85oC ) SYMBOL VDR (3) ICCDR tCDR tR TEST CONDITIONS MIN. TYP. (1) MAX. UNITS Vcc for Data Retention CE1 ≧ Vcc - 0.2V or CE2 ≦ 0.2V, VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V 1.5 -- -- V Data Retention Current CE1 ≧ Vcc - 0.2V or CE2 ≦ 0.2V, VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V -- 0.1 1.0 uA -- -- ns -- -- ns PARAMETER Chip Deselect to Data Retention Time See Retention Waveform Operation Recovery Time 0 TRC (2) 1. Vcc = 1.5V, TA = + 25OC 2. tRC = Read Cycle Time 3. IccDR_MAX. is 0.7uA at TA=70oC. LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled ) Data Retention Mode Vcc VDR ≥ 1.5V Vcc CE1 Vcc tR t CDR CE1 ≥ Vcc - 0.2V VIH VIH LOW VCC DATA RETENTION WAVEFORM (2) ( CE2 Controlled ) Data Retention Mode Vcc VDR ≧ 1.5V Vcc CE2 STC62WV2568 VIL Vcc tR t CDR CE2 ≦ 0.2V 3 VIL Revision 1.1 Jan. 2004 STC STC62WV2568 KEY TO SWITCHING WAVEFORMS AC TEST CONDITIONS (Test Load and Input/Output Reference) WAVEFORM Input Pulse Levels Vcc / 0V Input Rise and Fall Times 1V/ns Input and Output Timing Reference Level 0.5Vcc Output Load CL = 100pF+1TTL CL = 30pF+1TTL INPUTS OUTPUTS MUST BE STEADY MUST BE STEADY MAY CHANGE FROM H TO L WILL BE CHANGE FROM H TO L MAY CHANGE FROM L TO H WILL BE CHANGE FROM L TO H , DON T CARE: ANY CHANGE PERMITTED CHANGE : STATE UNKNOWN DOES NOT APPLY CENTER LINE IS HIGH IMPEDANCE ”OFF ”STATE AC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC) READ CYCLE JEDEC PARAMETER NAME PARAMETER NAME tAVAX tRC Read Cycle Time tAVQV tAA Address Access Time tE1LQV tACS1 Chip Select Access Time (CE1) tE2HOV tACS2 Chip Select Access Time tGLQV tOE Output Enable to Output Valid t E1LQX tCLZ1 tE2HOX DESCRIPTION CYCLE TIME : 55ns CYCLE TIME : 70ns MIN. TYP. MAX. MIN. TYP. MAX. (Vcc = 3.0~5.5V) (Vcc = 2.7~5.5V) 55 -- -- 70 -- -- -- 55 -- -- 70 ns -- -- 55 -- -- 70 ns (CE2) -- -- 55 -- -- 70 ns -- -- 30 -- -- 35 ns Chip Select to Output Low Z (CE1) 10 -- -- 10 -- -- ns tCLZ2 Chip Select to Output Low Z (CE2) 10 -- -- 10 -- -- ns tGLQX tOLZ Output Enable to Output in Low Z 5 -- -- 5 -- -- ns tE1HQZ tCHZ1 Chip Deselect to Output in High Z (CE1) -- -- 30 -- -- 35 ns tE2HQZ tCHZ2 Chip Deselect to Output in High Z (CE2) -- -- 30 -- -- 35 ns tGHQZ tOHZ Output Disable to Output in High Z -- -- 25 -- -- 30 ns tAXOX tOH Data Hold from Address Change 10 -- -- 10 -- -- ns STC62WV2568 4 -- UNIT ns Revision 1.1 Jan. 2004 STC STC62WV2568 SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1 (1,2,4) t RC ADDRESS t t t OH AA OH D OUT READ CYCLE2 (1,3,4) CE1 CE2 t t ACS1 t ACS2 t (5) (5) CHZ1, t CHZ2 CLZ D OUT READ CYCLE3 (1,4) t RC ADDRESS t AA OE t t CE1 t CE2 (5) t OH OLZ t ACS1 CLZ1 t t OE t OHZ (5) (1,5) t CHZ1 ACS2 t (5) (2,5) CHZ2 CLZ2 D OUT NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE1 = VIL and CE2= VIH. 3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high. 4. OE = VIL . 5. The parameter is guaranteed but not 100% tested. STC62WV2568 5 Revision 1.1 Jan. 2004 STC STC62WV2568 AC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC ) WRITE CYCLE JEDEC PARAMETER NAME CYCLE TIME : 55ns PARAMETER NAME tAVAX tE1LWH tAVWL tAVWH tWLWH tWHAX tE2LAX tWLQZ tDVWH tWHDX tGHQZ t WC t CW t AS t AW t WP t WR1 t WR2 t WHZ t DW t DH t OHZ tWHOX t OW DESCRIPTION CYCLE TIME : 70ns (Vcc = 3.0~5.5V) (Vcc = 2.7~5.5V) MIN. TYP. MAX. MIN. TYP. MAX. UNIT Write Cycle Time 55 -- -- 70 -- -- ns Chip Select to End of Write 55 -- -- 70 -- -- ns 0 -- -- 0 -- -- ns Address Valid to End of Write 55 -- -- 70 -- -- ns Write Pulse Width 30 -- -- 35 -- -- ns ns Address Setup Time Write recovery Time (CE1,WE) 0 -- -- 0 -- -- Write recovery Time (CE2) 0 -- -- 0 -- -- ns -- -- 25 -- -- 30 ns Data to Write Time Overlap 25 -- -- 30 -- -- ns Data Hold from Write Time 0 -- -- 0 -- -- ns Output Disable to Output in High Z -- -- 25 -- -- 30 ns End of Write to Output Active 5 -- -- 5 -- -- ns Write to Output in High Z SWITCHING WAVEFORMS (WRITE CYCLE) t WC WRITE CYCLE1 (1) ADDRESS t (3) WR1 OE (11) t CW (5) CE1 (5) CE2 t CW t WE (11) t WR2 AW t t AS (3) WP (2) (4,10) t OHZ D OUT t DH t DW D IN STC62WV2568 6 Revision 1.1 Jan. 2004 STC STC62WV2568 WRITE CYCLE2 (1,6) t WC ADDRESS (11) t (5) CW CE1 CE2 (5) (11) t t CW AW t WR2 t WP (3) (2) WE t AS (4,10) t WHZ D OUT t OW t DH (7) (8) t DW (8,9) D IN NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE1 going low or CE2 going high to the end of write. STC62WV2568 7 Revision 1.1 Jan. 2004 STC STC62WV2568 ORDERING INFORMATION STC62WV2568X X Z YY SPEED 55: 55ns 70: 70ns PKG MATERIAL -: Normal G: Green P: Pb free GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC PACKAGE S: SOP T: TSOP (8mm x 20mm) ST: Small TSOP (8mm x 13.4mm) D: DICE Note: STC (STC International Limited.) assumes no responsibility for the application or use of any product or circuit described herein. STC does not authorize its products for use as critical components in any application in which the failure of the STC product may be expected to result in significant injury or death, including life-support systems and critical medical instruments. PACKAGE DIMENSIONS STSOP - 32 STC62WV2568 8 Revision 1.1 Jan. 2004 STC STC62WV2568 PACKAGE DIMENSIONS (continued) TSOP - 32 WITH PLATING b c c1 BASE METAL b1 SECTION A-A SOP -32 STC62WV2568 9 Revision 1.1 Jan. 2004