STE110NA20 N - CHANNEL ENHANCEMENT MODE FAST POWER MOS TRANSISTOR PRELIMINARY DATA TYPE ST E110NA20 ■ ■ ■ ■ ■ ■ ■ ■ ■ V DSS R DS(on) ID 200 V < 0.019 Ω 110 A TYPICAL RDS(on) = 0.015 Ω HIGH CURRENT POWER MODULE AVALANCHE RUGGED TECHNOLOGY VERY LARGE SOA - LARGE PEAK POWER CAPABILITY EASY TO MOUNT SAME CURRENT CAPABILITY FOR THE TWO SOURCE TERMINALS EXTREMELY LOW Rth (Junction to case) VERY LOW INTERNAL PARASITIC INDUCTANCE ISOLATED PACKAGE UL RECOGNIZED ISOTOP APPLICATIONS ■ SMPS & UPS ■ MOTOR CONTROL ■ WELDING EQUIPMENT ■ OUTPUT STAGE FOR PWM, ULTRASONIC CIRCUITS INTERNAL SCHEMATIC DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol V DS Parameter Value Unit Drain-source Voltage (V GS = 0) 200 V V DGR Drain- gate Voltage (R GS = 20 kΩ) 200 V V GS Gate-source Voltage ± 30 V 110 A Drain Current (continuous) at Tc = 100 C 73 A Drain Current (pulsed) 440 A Total Dissipation at T c = 25 C 450 W Derating Factor 3.6 W/ C o ID Drain Current (continuous) at Tc = 25 C ID o I DM (•) P to t T st g Tj V ISO o o -55 to 150 o C Max. Operating Junction Temperature 150 o C Insulation Withhstand Voltage (AC-RMS) 2500 Storage Temperature V (•) Pulse width limited by safe operating area March 1996 1/8 STE110NA20 THERMAL DATA R t hj-ca se R thc -h Thermal Resistance Junction-case Thermal Resistance Case-heats ink With Conductive Grease Applied Max 0.27 o C/W Max 0.05 o C/W AVALANCHE CHARACTERISTICS Symb ol Parameter Max Valu e Unit 55 A I AR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max, δ < 1%) E AS Single Pulse Avalanche Energy (starting Tj = 25 oC, ID = I AR , V DD = 50 V) 500 mJ E AR Repetitive Avalanche Energy (pulse width limited by Tj max, δ < 1%) 175 mJ I AR Avalanche Current, Repetitive or Not-Repetitive (T c = 100 o C, pulse width limited by Tj max, δ < 1%) 32.5 A ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) OFF Symb ol V (BR)DSS Parameter Drain-source Breakdown Voltage Test Cond ition s I D = 1 mA Min. V GS = 0 Typ . Max. 200 Un it V I DSS V DS = Max Rating Zero Gate Voltage o Drain Current (V GS = 0) V DS = Max Rating x 0.8 T c = 125 C 400 200 µA mA I GSS Gate-body Leakage Current (V DS = 0) V GS = ± 30 V ± 400 nA ON (∗) Symb ol Parameter Test Cond ition s V GS(th) Gate T hreshold Voltage V DS = VGS ID = 1 mA R DS( on) Static Drain-source On Resistance V GS = 10V V GS = 10V I D = 55 A ID = 55 A On State Drain Current V DS > I D(on) x R DS(on) max V GS = 10 V ID(o n) Min. Typ . Max. Un it 2.25 3 3.75 V 0.015 0.019 Ω Ω o T c = 100 C 110 A DYNAMIC Symb ol g fs (∗) C iss C oss C rss 2/8 Parameter Test Cond ition s Forward Transconductance V DS =15 V Input Capacitance Output Capacitance Reverse Transfer Capacitance V DS = 25 V ID = 55 A f = 1 MHz VGS = 0 Min. Typ . 38 Max. Un it S 12.9 2870 980 nF pF pF STE110NA20 ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symb ol t d(on) tr (di/dt) on Qg Q gs Q gd Typ . Max. Un it Turn-on T ime Rise Time Parameter V DD = 100 V I D = 55 A VGS = 10 V R G = 4.7 Ω (see test circuit, figure 3) Test Cond ition s Min. 70 95 100 125 ns ns Turn-on Current Slope V DD = 160 V I D = 110 A R G = 47 Ω VGS = 10 V (see test circuit, figure 5) 290 Total Gate Charge Gate-Source Charge Gate-Drain Charge V DD = 160 V 470 43 226 600 nC nC nC Typ . Max. Un it 115 68 160 150 100 210 ns ns ns Typ . Max. Un it 110 440 A A 1.6 V I D = 110 A V GS = 10 V A/µs SWITCHING OFF Symb ol t r(Vof f) tf tc Parameter Off-voltage Rise Time Fall T ime Cross-over T ime Test Cond ition s Min. V DD = 160 V ID = 110 A V GS = 10 V R G = 4.7 Ω (see test circuit, figure 5) SOURCE DRAIN DIODE Symb ol Parameter Test Cond ition s Min. I SD I SDM (•) Source-drain Current Source-drain Current (pulsed) V SD (∗) Forward O n Voltage I SD = 110 A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 110 A di/dt = 100 A/µs o Tj = 150 C V R = 50 V (see test circuit, figure 5) t rr Q rr I RRM V GS = 0 625 ns 11 µC 35 A (∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % (•) Pulse width limited by safe operating area Safe Operating Area Thermal Impedance 3/8 STE110NA20 Derating Curve Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage 4/8 STE110NA20 Capacitance Variations Normalized Gate Threshold Voltage vs Temperature Normalized On Resistance vs Temperature Turn-on Current Slope Turn-off Drain-source Voltage Slope Cross-over Time 5/8 STE110NA20 Switching Safe Operating Area Accidental Overload Area Source-drain Diode Forward Characteristics Fig. 1: Unclamped Inductive Load Test Circuit 6/8 Fig. 2: Unclamped Inductive Waveform STE110NA20 Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And DIode Recovery Times 7/8 STE110NA20 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectonics. 1995 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A ... 8/8