STMICROELECTRONICS STLC5048

STLC5048
FULLY PROGRAMMABLE
FOUR CHANNEL CODEC AND FILTER
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FULLY PROGRAMMABLE MONOLITHIC 4
CHANNEL CODEC/FILTER
SINGLE +3.3V SUPPLY
A/m LAW PROGRAMMABLE
LINEAR CODING (16 BITS) OPTION
PCM HIGHWAY FORMAT AUTOMATICALLY
DETECTED:1.536 or 1.544 MHz2.048, 4.096,
8192 MHz
TWO PCM PORTS AVAILABLE
TX GAIN PROGRAMMING: 33dB RANGE;
<0.01dB STEP
RX GAIN PROGRAMMING:42dB RANGE;
<0.01dB STEP
PROGRAMMABLE SLIC INPUT IMPEDANCE
PROGRAMMABLE TRANSHYBRID BALANCE
FILTER
PROGRAMMABLE EQUALIZATION
(FREQUENCY RESPONSE)
PROGRAMMABLE TIME SLOT ASSIGNMENT
DIGITAL AND ANALOG LOOPBACKS
SLIC CONTROL PORTSTATIC (16 I/Os)
DYNAMIC (12 I/Os + 4 CS)
BUILT-IN TEST MODE WITH TONE
GENERATION, MCU ACCESS TO PCM DATA
64 TQFP (10X10mm) PACKAGE
PROGRAMMABLE SLIC LINE CURRENT
LIMITATION
PROGRAMMABLE SLIC OFF-HOOK
DETECTION THRESHOLD
DESCRIPTION
The STLC5048 is a monolithic fully programmable 4
channel CODEC and filter. It operates with a single
+3.3V supply.
The analog interface is based on a receive output
January 2003
TQFP64 (10x10mm)
ORDERING NUMBER: STLC5048
buffer driving the SLIC RX input and on an amplifier
input stage normally driven by the SLIC TX output.
Due to the single supply voltage a midsupply reference level is generated internally by the device and
all analog signals are referred to this level (AGND).
The PCM interface uses one common 8KHz frame
sync. pulse for transmit and receive direction. The bit
clock is automatically detected between four standards: 1.563/1.544MHz, 2.048MHz, 4.096MHz,
8192MHz.
Two PCM port are provided: the channels can be
connected to port A or/and B.
Device programmability is achieved by means of
several registers and commands allowing to set the
different parameters like TX/RX gains, line impedance, transhybrid balance, equalization (frequency
response), encoding law (A/µ), time slot assignment,
independent channels power up/down, loopbacks,
PCM bits offset.
The STLC5048 can be programmed via serial interface running up to 8 MHz. One interrupt output pin is
also provided.
A GUI interface is also available to emulate and program the coefficients for impedance synthesis, echo
cancelling and channel filtering.
1/45
STLC5048
BLOCK DIAGRAM
VCC
VEE
VDD
VSS
ANALOG FRONT END
SUB
CAP
M1
M0
DIGITAL PROCESSOR
FS
MCLK
D/A
CH0
16
GR0
DRB
PLL
BLOCK
DATA INTERFACE
D/A
CH1
GR1
SHAPPIRE
MACRO
8
VFX11
INTERPOLAT.
DECIMATORS
KD FILTERS
8
GX1
COEFF BUS
TSXA
DECODER
A/D
CH1
DXB
A/U LAW
GX0
VFRO1
DXA
ENCODER
A/D
CH0
VFX10
DRA
A/U LAW
CONTROL INTERFACE
VFRO0
PCM
INTERFACE
16
TSXB
IO11
IO10
IO9
IO8
IO7
IO6
IO5
SLIC
INTERFACE
IO1
GR2
BIAS
GENER.
IO0
CONTROLLER
CS3
A/D
CH2
VFX12
IO3
IO2
D/A
CH2
VFRO2
IO4
CS2
GX2
CS1
to analog FE
CONFIG.
REGISTERS
CS0
INT
D/A
CH3
VFRO3
CCLK
GR3
VFX13
CI
SERIAL
INTERFACE
SLIC
THR
A/D
CH3
CO
GX3
CS
ITH
ILIM
VBG
D00TL467
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC
VCC to VEE
4.6
V
VDD
VDD to VSS
4.6
V
VDIN
Digital Input Pin Voltage
5.5
V
VAin
Analog Input Pin Voltage(VDD=VCC; VEE=VSUB)
VCC + 0.5; VEE - 0.5
V
TSTG
Storage Temperature Range
-65 to +150
°C
TLEAD
Lead Temperature (soldering, 10s)
300
°C
Value
Unit
Supply Voltage
3.3 +/- 5%
V
Operating Temperature Range
-40 to +85
°C
Value
Unit
70
°C/W
OPERATING RANGE
Symbol
VCC , VDD
TOP
Parameter
THERMAL DATA
Symbol
Parameter
Rth j-amb
Thermal Resistance Junction-Ambient
2/45
STLC5048
VBG
VEE3
VEE2
CS3_
CS2_
M1
VEE4
VCC4
IO11
IO10
IO9
IO8
IO7
IO6
N.C.
RES.
PIN CONNECTION (Top view)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
N.C.
1
48
VFRO3
N.C.
2
47
ILIM
INT
3
46
VFXI3
CS
4
45
VCC3
CO
5
44
VCC2
CI
6
43
VFXI2
CCLK
7
42
VFRO2
VSS
8
41
SUB
VDD
9
40
CAP
DRA
10
39
VFRO1
DXA
11
38
VFXI1
TSXA
12
37
VCC1
MCLK
13
36
VCC0
FS
14
35
VFXI0
DXB
15
34
ITH
DRB
16
33
VFRO0
RES
VEE0
VEE1
CS1_
CS0_
M0
VEE5
VCC5
IO5
IO4
IO3
IO2
IO1
IO0
N.C.
TSXB_
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
D94TL150
PIN DESCRIPTION
I/O DEFINITION
Type
Definition
AI
Analog Input
AO
Analog Output
ODO
Open Drain Output
DI
Digital Input
DO
Digital Output
DIO
Digital Input / Output
DTO
Digital Tristate Output
DPS
Digital Power Supply
APS
Analog Power Supply
3/45
STLC5048
PIN DESCRIPTION (continued)
ANALOG PIN DESCRIPTION
No.
Name
Type
Description
33
VFRO0
AO
Receive analog amplifier output channel 0. PCM data received on
the programmed Time Slot on DR input is decoded and appears at
this output.
39
VFRO1
AO
Receive analog amplifier output channel 1. PCM data received on
the programmed Time Slot on DR input is decoded and appears at
this output.
42
VFRO2
AO
Receive analog amplifier output channel 2. PCM data received on
the programmed Time Slot on DR input is decoded and appears at
this output.
48
VFRO3
AO
Receive analog amplifier output channel 3. PCM data received on
the programmed Time Slot on DR input is decoded and appears at
this output.
35
VFXI0
AI
TX Input Amplifier channel 0. Typ 1MΩ input impedance
38
VFXI1
AI
TX Input Amplifier channel 1. Typ 1MΩ input impedance
43
VFXI2
AI
TX Input Amplifier channel 2. Typ 1MΩ input impedance
46
VFXI3
AI
TX Input Amplifier channel 3. Typ 1MΩ input impedance
40
CAP
34
ITH
AO
SLIC Off Hook detection threshold.
47
ILIM
AO
SLIC line current limitation.
49
VBG
AI
SLIC VBG reference for DC characterisrics programmability.
AGND Voltage filter pin: a 100nF capacitor must be connected
between ground and this pin.
NOT CONNECTED
2, 18, 63, 1
N.C.
Not Connected, must be left open
32, 64
RES
Reserved pins, must be connected to ground
POWER SUPPLY PIN DESCRIPTION
4/45
25,36,
37,44,
45,56
VCC0..5
APS
Total 6 pins: 3.3V analog power supplies, should be shorted together,
require 100nF decoupling capacitor to VEE.
26,30,
31,50,
51,55
VEE0..5
APS
Total 6 pins: analog ground, should be shorted together.
9
VDD
DPS
Digital Power supply 3.3V, require 100nF decoupling capacitor to
VSS.
8
VSS
DPS
Digital Ground.
41
SUB
DPS
Substrate connection. Must be shorted together with VEE and VSS
pins.
STLC5048
PIN DESCRIPTION (continued)
DIGITAL PIN DESCRIPTION
No.
Name
Type
Description
27
54
M0
M1
DI
14
FS
DI
Frame Sync. Pulse. A pulse or a square waveform with an 8kHz
repetition rate is applied to this pin to define the start of the receive
and transmit frame. Effective start of the frame can be then shifted of
up to 7 clock pulses independently in receive and transmit directions
by proper programming of the PCMSH register.
13
MCLK
DI
Master Clock Input.
Four possible frequencies can be used:
1.536/1.544 MHz; 2.048 MHz; 4.096 MHz; 8.192 MHz.
The device automatically detect the frequency applied.
This signal is also used as bit clock and it is used to shift data into
and out of the DRA/B and DXA/B pins.
12
TSXA
ODO
Transmit Time Slot (open drain output, 3.2mA). Normally it is floating
in high impedance state except when a time slot is active on the DXA
output. In this case TSXA output pulls low to enable the backplane
line driver.
11
DXA
DTO
Transmit PCM interface A. It remains in high impedance state except
during the assigned time slots during which the PCM data byte is
shifted out on the rising edge of MCLK.
10
DRA
DI
Receive PCM interface A. It remains inactive except during the
assigned receive time slots during which the PCM data byte is shifted
in on the falling edge of MCLK.
24
IO5
DIO
General control I/O pin #5. Can be programmed as input or output via
DIR register. Depending on content of CONF register can be a static
input/output or a dynamic input/output synchronised with the CSn
output signals controlling the SLICs.
62
IO6
DIO
General control I/O pin #6. (see IO5 description).
61
IO7
DIO
General control I/O pin #7. (see IO5 description).
60
IO8
DIO
General control I/O pin #8. (see IO5 description).
59
IO9
DIO
General control I/O pin #9. (see IO5 description).
58
IO10
DIO
General control I/O pin #10. (see IO5 description).
57
IO11
DIO
General control I/O pin #11. (see IO5 description).
19
IO0
DIO
General control I/O pin #0. (see IO5 description).
20
IO1
DIO
General control I/O pin #1. (see IO5 description).
21
IO2
DIO
General control I/O pin #2. (see IO5 description).
22
IO3
DIO
General control I/O pin #3. (see IO5 description).
23
IO4
DIO
General control I/O pin #4. (see IO5 description).
Mode Select.
M1
M0
0
0
1
0
0
1
1
1
Mode select
Reset Status
Normal Operation
Not Allowed
Not Allowed
5/45
STLC5048
PIN DESCRIPTION (continued)
DIGITAL PIN DESCRIPTION (continued
6/45
No.
Name
Type
Description
28
CS0
DIO
Slic CS control #0. Depending on CONF reg. content can be a CS
output for SLIC #0 or a static I/O.
When configured as CS output it is automatically generated by the
CODEC with a repetition time of 31.25ms. In this mode also the
IO0..11 are synchronised and carry proper data in and out
synchronous with CS.
When configured as static I/O, the direction is defined by CSDIR
register content.
29
CS1
DIO
Slic CS control #1, (see CS0 description).
53
CS2
DIO
Slic CS control #2, (see CS0 description).
52
CS3
DIO
Slic CS control #3, (see CS0 description).
4
CS
DI
Chip Select Input, when this pin is low control information can be
written to or read from the device via the CI and CO pins.
7
CCLK
DI
Clock of Serial Control Bus. This clock shifts serial control information
into or out of CI or CO when CS input is low depending on the current
instruction. CCLK may be asynchronous with the other system
clocks.
6
CI
DI
Control Data Input of Serial Control Bus.
Control data is shifted in the device when CS is low and clocked by
CCLK. Depending on the addressed register different numbers of
consecutive bytes can be loaded.
5
CO
DI
Control Data Output of Serial Control Bus.
Control data is shifted out the device when CS is low and clocked by
CCLK. Depending on the addressed register different numbers of
consecutive bytes can be shifted out.
3
INT
ODO
Interrupt output (open drain), goes low when a data change has been
detected in the I/O pins or another interrupt source is active. One
mask register allows to mask any I/O pin. Interrupt is reset when the I/
O register is read.
17
TSXB
ODO
Transmit Time Slot (open drain output, 3.2mA). Normally it is floating
in high impedance state except when a time slot is active on the DXB
output. In this case TSXB output pulls low to enable the backplane
line driver.
15
DXB
DTO
Transmit PCM interface B. It remains in high impedance state except
during the assigned time slots during which the PCM data byte is
shifted out on the rising edge of MCLK.
16
DRB
DI
Receive PCM interface B. It remains inactive except during the
assigned receive time slots during which the PCM data byte is shifted
in on the falling edge of MCLK.
STLC5048
FUNCTIONAL DESCRIPTION
The STLC5048 is a fully programmable device with embedded ROM and RAM. The ROM is used to contain the default
state coefficients for the programmable filters, while the RAM is used to load the desired coefficient values.
POWER ON INITIALIZATION
When power is first applied it is recommended to reset the device (M1=M0=0) in order to set all the internal registers to the reset value (see register description); this means also power down mode for all the four channels
and SW reset bit (RES) set in the CONF register.
When the RES bit is set, the only instructions allowed are the one that disable this bit and the REACOM instruction: all other instructions are ignored. It is not possible to disable the RES bit and write the other bits of the
CONF register with the same instruction.
Of course, RESET mode can be programmed also by writing the RES bit of the CONF register.
See appendix C for the power up sequence.
During RESET condition all the I/On and CSn pins are set as inputs, DX is in high impedance and all VFROn
are set to AGND. After the reset all registers are loaded with the reset value.
It means that the PCM interface and all the VFRO outputs are configured as described in the Power Down State,
while no transmit or receive time slot are set.
Then, filters and gain blocks are configured with the coefficient defined in the Default State.
POWER DOWN STATE
Each of the four channel may be put into power down mode by setting the appropriate bit in the CONF register.
In this mode the eventual programmed DX channel is set in high impedance while the VFRO outputs are forced
to AGND. When all the channels are set in Power Down mode the device enters the Power Down state: all the
blocks related to the data processing are turned off, while the RAM is On or Off according to the PDR bit value
in the COMEN register.
Figure 1. Block Diagram of a single channel.
*
DR
A/mu
HPR
R
RX
*
GR
LPR
D/A
*
*
B
*
DX
A/mu
HPX
X
Z
VFRO
*
*
KD
KA
*
GX
*
*
LPX
VFXI
A/D
TX
* PROGRAMMABLE BLOCKS
D00TL468
7/45
STLC5048
FUNCTIONAL DESCRIPTION (continued)
RINGING STATE
This state can be used during the ringing phase in order to transmit a low frequency ringing signal (25-50 Hz).
In order to obtain a 1 Vrms ringing signal at VFRO output a digital signal DR equal to -0.78dBm0 must be provided.
This state means B, Z, X, KD and KA blocks equal to open circuits and the R block configured in order to obtain
the maximum gain at the frequency of 25-50 Hz. During the ringing state if the TX time slot is enabled the idle
PCM code is forced to DX.
To switch to this state, a bit (FR0..3) in the COEFST register must be set for every channel.
The programmed values for the previous blocks become active only when the FR and FD bits are reset.
If both FR and FD bits of a channel are set, the selected coefficient will be those of the Ringing State.
IMPEDANCE SYNTHESYS
The impedance synthesis is performed by fully digital filters (Z and KD) and by an analog path (KA).
The Z, KD and KA filters report to the receive path the feedback signal coming from the transmit path. The coefficients of the Z, KD and KA filters are programmed via the ZFC, KD and AFE_CFF commands respectively.
ECHO CANCELING
The trans-hybrid balance is performed by the digital programmable filter B.
The B filter reports to the transmit path the signal coming from the receive path. The coefficient of the B filter
are programmed via the BFC command.
Figure 2. Transmit path.
TXG
Σ∆
CONV.
VFXI
GXO
GX
A/µ
DX
1MΩ
AGND
for TXG=0dB; GX=0dB (FF)
61mVms => 0dBm0
D00TL469
TRANSMIT PATH
The transmit section input consist of the input amplifier, the A/D converter, the equalization filter X, the gain
block GX, the encoder and the channel filters (LPX and HPX).
The input amplifier is provided of a programmable gain with a typical input impedance of 1MΩ. The amplifier
gain can be programmed with two different values (0dB, +3.52dB) by means of the TXG Register.
VFXI input must be AC coupled to the signal; the voltage swing allowed is 1.4Vpp when the preamplifier gain is
set to 0dB and 0.93Vpp when the gain is 3.52dB; higher levels must be reduced through proper dividers.
Following the input amplifier the signal is converted into digital domain and a X filter block is programmed to
equalise together with the HPX and LPX filters the frequency response. The coefficients of the X filter are programmed via the XFC command.
A gain block (GX) allows to set the transmit level in a 30dB range, with steps <0.01dB. This block can be programmed via the GTX command.
8/45
STLC5048
FUNCTIONAL DESCRIPTION (continued)
The needed TX gain can be set by proper programming of the GX block in combination with the TX amplifier.
Setting GTX=00h, the transmitted signal is muted and an idle PCM signal is generated on DX.
Concerning the CODING function, A/m law can be selected writing the CONF register (bit 5 AMU). In addition,
via the CONF register (bit 6 LIN) the coding law can be set to linear mode (16 bits). In this case the signal sent
on the DX will take two adjacent PCM channels, proper care has to be taken in the time slot selection programming (DXTS register).
The intrinsec non programmable gain GX0 set the TX path gain to 22.07dB. The absolute gain level (see electrical characteristics) refers to this intrinsec gain.
RECEIVE PATH
The receive path of the STLC5048 consists of the decoder section, the gain block GR, the R filter, the channel
filters (LPR, HPR) the D/A converter and the output amplifier.
Concerning the DECODING function, A/m law can be selected writing the CONF register (bit 5 AMU). In addition
via the CONF register (bit 6 LIN) the coding law can be set to linear mode (16 bits).
In this case the signal received on the DR input will take two adjacent PCM channels, proper care has to be
taken in the time slot selection programming (DRTS register).
The gain block GR is controlled by the GRX command allowing 30dB gain range in 0.01dB steps.
The R filter together the channel filters (LPR and HPR) performs the line equalization. The coefficients of the R
filter are programmed via the RFC command.
The signal is converted in the analog domain and amplified by the RX amplifier that can be programmed with
four different values (mute, 0dB, -6dB and -12dB) by means of RXG register.
Figure 3. Receive path.
RXG
DR
A/µ
GR
GRO
Σ∆
CONV.
D00TL470
VFRO
for RXG=0dB; GR=0dB
0dBm0 => -3dBm/600Ω
VFRO output, referred to AGND must be AC coupled to the load, referred to VSS, to prevent a DC current flow.
In order to get the best noise performances it is recommended to keep GRX value as close as possible to the
maximum (FFh) setting properly the additional attenuation by means of RXG.
The intrinsec non programmable gain GR0 set the RX path gain to -3.15dB. The absolute gain level (see electrical characteristics) refers to this intrinsec gain.
PCM INTERFACE
The STLC5048 dedicates eight pins to the interface with the PCM highways.
MCLK represents the bit clock and is also used by the device as a source for the clock of the internal PLL.
Five possible frequencies can be used: 1.536/1.544MHz (24 channels PCM frame); 2048MHz (32 channels
PCM frame); 4.096MHz (64 channels PCM frame); 8.192MHz (128 channels PCM frame). The operating fre9/45
STLC5048
quency is automatically detected by the device the first time both MCLK and FS are applied and becomes active
after the second FS period. MCLK synchronises both the transmit data (DXA/B) and the receive data (DRA/B).
The Frame Sync. signal FS is the common time base for all the four channels.
Transmit and Receive programmable Time-Slots are framed by an internal sync. signal that can be coincident
with FS or delayed of 1 or 7 MCLK cycles depending on the programming of PCMSH register.
Two PCM ports are available: every channel can be connected to a different PCM port by means of PCMCOM
register.
DXA/B represents the transmit PCM interface. It remains in high impedance state except during the assigned
time slots during which the PCM data byte is shifted out on the rising/falling edge of MCLK according to the TE
bit of PCMCOM register. The four channels can be shifted out in any possible timeslot as defined by the DXTS
registers. The assigned Time Slot (Transmit and Receive) takes place in the 8 MCLK cycles following the rising
edge of FS.
The data can be shifted out on port A and/or B according to PCMCOM register.
If one CODEC is set in Power Down by software programming the corresponding time slot is set in High Impedance. When linear coding mode is selected by CONF register programming the output channel will need two
consecutive time slots (see register description).
DRA/B represents the receive PCM interface. It remains inactive except during the assigned time slots during
which the PCM data byte is shifted in on the falling edge of MCLK. The four channels are shifted in any possible
time slot as defined by the DRTS registers.
If one Codec is set in Power Down by software programming the corresponding time slot is not loaded and the
VFRO output is kept at steady AGND level.
INSTRUCTION BYTE STRUCTURE
First Byte (Address or command ID)
Following Bytes (Data)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
R/W
I6
I5
I4
I3
I2
I1
I0
D7
D6
D5
D4
D3
D2
D1
D0
R/W=0: Write Operation
R/W=1: Read Operation
I6..I0: Instruction Identifier: it can be a register address or a command identifier.
The number of data bytes depends on the instruction type. The first bit of a byte is the MSB, the first byte of an instruction is the LSByte.
When linear coding mode is selected by CONF register programming the input channel will need two consecutive time slots (see register description).
The data can be shifted in from port A or B according to the PCMCOM register.
TSXA/B represents the Transmit Time Slot (open drain output, 3.2mA). Normally it is floating in high impedance
state except when a time slot is active on the DXA/B output. In this case TSXA/B output pulls low to enable the
backplane line driver. Should be strapped to VSS when not used.
Finally by means of the LOOPB register it is possible to implement a digital or analog loopback on any of the
selected channels.
MCU CONTROL INTERFACE
The MCU serial control interface consists of 4 pins.
CCLK: Control Clock
CI:
Serial Data In
CO:
Serial Data Out
CS:
Chip Select Input
Control instructions require at least two bytes: however two single byte instructions are also provided.
10/45
STLC5048
In the multiple byte instructions the first one specifies the command or the register address and the access type
(Read or Write).
The following bytes contain the data to be loaded into the internal RAM (on CI wire) or carry out the RAM content
(on CO wire) depending on the R/W bit of the first byte. CO wire is normally in High Impedance and goes to low
impedance only after the first byte in case of Read operation. This allows to use a common wire for both CI/CO.
CS, normally High, is set Low during the transmission/reception of a byte, lasting 8 CCLK pulses. Between two
consecutive access the CS must be set high.
The CCLK can be a continuos or a gated clock.
The result of any instruction (read/write operation), if negative, can generate an interrupt (maskable). The interrupt register (INT) contains the cause information of the generated interrupt and it is cleared every time that it
is read.
Depending on the instruction specified in the first byte, the STLC5048 waits a defined number of data bytes. If
the STLC5048 doesn't receive the data byte within a predefined period specified by means of T_OUT command,
an internal time out rejects the instruction. The time-out time is verified between two consecutive MCU interface
access (between the falling edge of the CS and the following rising edge).
This feature is used to verify the synchronisation of the MCU interface: however it can be disabled if not desired
(see T_OUT reg description). To check this synchronisation is provided a specific register (SYNCK) that returns
always a predefined value: if the returned value is different the MCU interface is in out of sync state (the device
is waiting a data byte while the MCU is writing an address or vice versa). In this case, it is possible to realign it
by means of the execution of a specific single byte instruction (REACOM) from 1 to 53 times, depending on the
instructions.
Every time an illegal operation (access to not allowed address, time-out violation or clock pulse different than 8
inside a CS active) is performed the MCU interface is put on an error state: to resume it from this state a single
REACOM instruction can be used.
Anyway after a REACOM instruction a successful SYNC instruction guarantees the correct synchronisation.
One additional wire provided to the control interface is an open drain interrupt output (INT) that goes low when
a change of status is detected on the I/O pins or other interrupt source are active (see INT register). INT is automatically reset after reading of the register corresponding the cause that has generated the interrupt (see INT
register description).
A particular register (COMEN) allows to enable a command on different channel at the same time. Every time
a command operation is performed at least one channel must be enabled in this register.
This feature is useful when all channels must be configured in the same condition. When a command is used
to perform a read operation only one channel can be enabled at the same time.
To check the configuration of the device a checksum value is provided. This value is calculated on all coefficient
parameters entered (coefficients of KD, AFE_CFF, GRX, GTX, RFC, XFC, BFC, ZFC blocks; see CKSUM register description). Two commands are required to get this value: the first one (CKSTART) starts the internal
checksum calculation, the second one (CKSUM) returns the calculated value. Between this two commands no
other operation are allowed. The checksum value is available within 400us the CKSTART command.
Coefficient checksum is defined by this algorithm:
X16 + X12 + X5 + 1
This algorithm guarantees a fault coverage of 1 - 2 -16.
PROGRAMMING THE DEVICE
After the power up, the filters and gain blocks can be programmed also with all the channels set in Power Down.
In this case the PDR bit of the COMEN register must be set to 0.
With the proper setting of the COMEN register, the commands can be applied to more than one channel at the
same time.
To read the coefficient values loaded in the RAM, only one channel per time must be enabled in the COMEN
register.
11/45
STLC5048
SLIC CONTROL INTERFACE
The device provides 12 I/O pins plus 4 CS signals. The interface can work in dynamic or static mode: it can be
selected by means of STA bit of the CONF register.
■ Dynamic Mode: the I/O pins are configured as input or output by means of DIR register. The CS signals
are used to select the different SLIC interface. In this case the I/O pin can be multiplexed. The data
loaded from SLIC #n via I/O pins configured as input can be read in the DATAn register. The data written
in a DATAn register will be loaded on the I/O pins configured as output when the Csn signal will be
active.
■
Static Mode: The CS signal can be used as I/O pins. They can be configured as input or output I/O by
means of DATA1 register. The data corresponding to the CS signal can be read or written by means of
DATA2 register. All data related to the other I/O pins can be read or written by means of DATA0 register.
DC SLIC PROGRAMMABILITY
Three additional pins are used to select the On-Hook/Off-Hook detection threshold and the line card limitation
of the STLC3080 SLIC. This two values are programmed by ILIM and ITH registers. The programmation of
these two registers must be done before the filter coefficients download.
The VBG input pin must be connected to the IREF pin of the STLC3080.
When the L3235N is used in kit with STLC5048 the ILIM, ITH and VBG pin must be not connected.
BUILT IN TEST
By means of TONEG register it is possible to inject a tone of variable frequency (25Hz, 1 and 3KHz) and 0dBm0
amplitude into the receive path, replacing any signal coming from the PCM interface. This test can be performed
on every channel.
Setting the proper bit of the PCMCOM register is also possible to read/write the PCM data coming from the
transmit path via the MCU interface (PCMRD/PCMWD registers). This feature can be enabled only on one
channel per time.
These two features can be used to test the line interface operation.
REGISTER ADDRESSES
12/45
Addr
Name
Description
00h
DIR-L
I/O Direction (bit 7-0)
01h
DIR-H
I/O Direction (bit 11-8)
02h
DATA0-L
I/O Data ch#0 (bit 7-0)
03h
DATA0-H
I/O Data ch #0 (bit 11-8)
04h
DATA1-L
I/O Data ch#1 (bit 7-0)
05h
DATA1-H
I/O Data ch #1 (bit 11-8)
06h
DATA2-L
I/O Data ch#2 (bit 7-0)
07h
DATA2-H
I/O Data ch #2 (bit 11-8)
08h
DATA3-L
I/O Data ch#3 (bit 7-0)
09h
DATA3-H
I/O Data ch #3 (bit 11-8)
0Ah
PCHK-A
Persistency Check Time for input A
0Bh
PCHK-B
Persistency Check Time for input B
10h
INT
Interrupt register
STLC5048
REGISTER ADDRESSES (continued)
11h
DMASK-L
Int. Mask I/O Port (03h)
12h
DMASK-H
Int. Mask I/O Port (04h)
Addr
Name
13h
IMASK
Interrupt Mask reg.
14h
ALARM
Alarm register
20h
CONF
Configuration register
21h
COMEN
Command Enable reg.
23h
SYNCCK
Synchronous Check reg.
25h
CTRLACK
DSP status register
26h
CKSUM-L
Cheksum register L
27h
CKSUM-H
Cheksum register H
2Ah
LOOPB
2Bh
TXG
Transmit preamp. Gain
2Ch
RXG
Receive preamp. Gain
2Dh
ILIM
SLIC line current lim.
2Eh
ITH
SLIC Off-Hook threshold
50h
PCMSH
PCM Shift register
51h
PCMCOM
PCMCOM register
52h
DXTS0
Transmit Timeslot ch #0
53h
DXTS1
Transmit Timeslot ch #1
54h
DXTS2
Transmit Timeslot ch #2
55h
DXTS3
Transmit Timeslot ch #3
56h
DRTS0
Receive Timeslot ch #0
57h
DRTS1
Receive Timeslot ch #1
58h
DRTS2
Receive Timeslot ch #2
59h
DRTS3
Receive Timeslot ch #3
5Ah
PCMWD-L
PCMW Data register
5Bh
PCMWD-H
PCMW Data register
5Ch
PCMRD-L
PCMR Data register
5Dh
PCMRD-H
PCMR Data register
5Eh
PCMCTRL
PCM Control register
60h
TONEG
Tone Generation reg.
61h
COEFST
Coefficient State reg.
70h
SWRID
Software rev. ID code
71h
HWRID
Silicon revision ID code
Description
Loopback register
13/45
STLC5048
REGISTER DESCRIPTION
I/O Direction Register (DIR)
Addr=00h; Reset Value=00h
Addr=01h; Reset Value=X0h
BIt7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
0
0
0
0
0
0
0
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
BIt7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
0
0
0
0
0
0
1
IO11
IO100
IO9
IO8
IO11..0=0 I/O pin 11..0 is an input, data on the I/O input is written in DATAn register bit 11..0.
IO11..0=1 I/O pin 11..0 is an output, data contained in DATAn register bit 11..0 is transferred to the I/O output.
I/O Data Register channel #0 (DATA0)
Addr=02h; Reset Value=00h
Addr=03h; Reset Value=X0h
If bit 4 of CONF register (STA)=0 Dynamic I/O mode:
BIt7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
0
0
0
0
0
1
0
D07
D06
D05
D04
D03
D02
D01
D00
BIt7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
0
0
0
0
0
1
1
D011
D010
D09
D08
When CS0 is active D011..0 are transferred to the corresponding I/O pins configured as outputs (see DIR register). For the I/O pins configured as inputs the corresponding D011..0 will be written by the values applied to
those pins while CS0 is low.
If bit 4 of CONF register (STA)=1 Static I/O mode:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
0
0
0
0
0
1
0
DS7
DS6
DS5
DS4
DS3
DS2
DS1
DS0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
0
0
0
0
0
1
1
DS11
DS10
DS9
DS8
DS11..0 are transferred to the corresponding I/O pins configured as outputs (see DIR register). For the I/O pins
configured as inputs the corresponding DS11..0 will be written by the values applied to those pins.
14/45
STLC5048
I/O Data Register channel #1 (DATA1)
Addr=04h; Reset Value=00h
Addr=05h; Reset Value=X0h
If bit 4 of CONF register (STA)=0 Dynamic I/O mode:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
0
0
0
0
1
0
0
D17
D16
D15
D14
D13
D12
D11
D10
BIt7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
0
0
0
0
1
0
1
D111
D110
D19
D18
When CS1 is active D111..0 are transferred to the corresponding I/O pins configured as outputs (see DIR register). For the I/O pins configured as inputs the corresponding D111..0 will be written by the values applied to
those pins while CS1 is low.
If bit 4 of CONF register (STA)=1 Static I/O mode:
In static mode CS pins are used as additional I/O pins. The CIO0..3 bits are used to define the direction of these pins.
BIt7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
0
0
0
0
1
0
0
CIO3
CIO2
CIO1
CIO0
CIO0..3=0 The CS0..3 is a static input, DATA is written in DATA2 register bits 0..3.
CIO0..3=1 The CS0..3 is a static output, DATA is taken from DATA2 register bits 0..3.
I/O Data Register channel #2 (DATA2)
Addr=06h; Reset Value=00h
Addr=07h; Reset Value=X0h
If bit 4 of CONF register (STA)=0 Dynamic I/O mode:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
0
0
0
0
1
1
0
D27
D26
D25
D24
D23
D22
D21
D20
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
0
0
0
0
1
1
1
D211
D210
D29
D28
When CS2 is active D211..0 are transferred to the corresponding I/O pins configured as outputs (see DIR register). For the I/O pins configured as inputs the corresponding D211..0 will be written by the values applied to
those pins while CS2 is low.
15/45
STLC5048
If bit 4 of CONF register (STA)=1 Static I/O mode:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
0
0
0
0
1
1
0
CD3
CD2
CD1
CD0
CD0..3 are transferred to the corresponding CS pin if configured as static output (see register DATA1). For the
CS pins configured as static inputs the corresponding CD0..3 will be written by the values applied to those pins.
I/O Data Register channel #3 (DATA3)
Addr=08h; Reset Value=00h
Addr=09h; Reset Value=X0h
Used only if bit 4 of CONF register (STA)=0; Dynamic I/O mode:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
0
0
0
1
0
0
0
D37
D36
D35
D34
D33
D32
D31
D30
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
0
0
0
1
0
0
1
D311
D310
D39
D38
When CS3 is active D311..0 are transferred to the corresponding I/O pins configured as outputs (see DIR register). For the I/O pins configured as inputs the corresponding D311..0 will be written by the values applied to
those pins while CS3 is low.
If bit4 of CONF register (STA) = 1
Static I/O mode:
D33..0=1: The corresponding CSn cannot generate interrupt.
D33..0=0: The corresponding I/O (programmed as input) can generate interrupt if a change of status is detected.
Persistency Check Register (PCHK-A/B)
Addr=0Ah; Reset Value=00h
Addr=0Bh; Reset Value=00h
Two input signal per channel, labelled A and B, are submitted to persistency check.
In dynamic mode (STA=0), A and B inputs of the four channels, are sampled on the multiplexed lines IO0 (pin
13) and IO1 (pin 14).
In static mode (STA=1) persistency check is performed on four pairs of lines, assigned to each channel according to the table:
16/45
CHAN #
Input A
Input B
0
IO0 (pin 19)
IO1 (pin 14)
1
IO4 (pin 17)
IO5 (pin 18)
2
IO6 (pin 48)
IO7 (pin 47)
3
IO10 (pin 44)
IO11 (pin 43)
STLC5048
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
0
0
0
1
0
1
0
TA7
TA6
TA5
TA4
TA3
TA2
TA1
TA0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
0
0
0
1
0
1
1
TB7
TB6
TB5
TB4
TB3
TB2
TB1
TB0
TA7..0 and TB7..0, contents of PCHKA and PCHKB registers, define the minimum duration of input A and B to
generate interrupt; spurious transitions shorter than the programmed value are ignored.
The time width can be calculated according to the formula:
Time - Width A = (TA7..0)*64µs
Time - Width B = (TB7..0)*64µs
If PCHKA/B is programmed to 00h the persistency check is not performed and any detected transition will generate interrupt.
All the inputs, with or without persistency check, are sampled with a repetition rate of 32µs.
Interrupt Register (INT)
Addr=10h; Reset Value=00h
Read Only
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1
0
0
1
0
0
0
0
ITV
IPCM
ICKF
ID3
ID2
ID1
ID0
In dynamic I/O configuration the ID3..0 bits latch the interrupt request from the related channel (SLIC). Any single bit IDn is cleared after reading related I/O register or by setting MCn bit High (i.e. when channel n is disabled
to generate interrupt).
In static I/O configuration ID0 and ID2 bits latch the interrupt request from I/O11..0 and CS3..0 respectively:
ID0: is set High when the interrupt is requested from any the I/O11..0 lines.
ID2: is set High when the interrupt is requested from any the CS3..0 (configured as I/O).
ID0 and ID2 are cleared after reading related I/O register.
ID1 and ID3 are don’t care.
ITV = 1: If the interrupt has been generated by time-out violation on the MCU serial interface.
IPCM = 1: When transmit PCM data reading/writing test is enabled an interrupt is generated every time valid
data are available (RRD bit set to 1) or must be written (WRD bit set to 1). The interrupt is cleared after reading/
writing the data in the PCMRD/PCMWD register via the MCU interface.
ICKF = 1: If the interrupt has been generated by a clock failure on PCM port (MCLK).
The INT register is cleared after reading operation only if signals (alarm cause) are inactive.
17/45
STLC5048
Interrupt Mask Register for I/O port (DMASK)
Addr=11h; Reset Value=FFh
Addr=12h; Reset Value=XFh
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
0
0
1
0
0
0
1
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
0
0
1
0
0
1
0
MD11
MD10
MD9
MD8
MD11..0=1: The corresponding I/O doesn’t generate interrupt.
MD11..0=0: The corresponding I/O (programmed as input) generate interrupt if a change of status is detected.
Input lines with persistency check generate interrupt if the changed status remains stable longer than the time
programmed in the persistency check register PCHKA/B. Line without persistency check generate an immediate interrupt request.
Mask register has no effect on those pins configured as outputs, those pins will not generate interrupt.
Interrupt Mask Register for Interrupt (IMASK)
Addr=13h; Reset Value=FFh
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
0
0
1
0
0
1
1
x
MTV
MPCM
MCF
MC3
MC2
MC1
MC0
For dynamic I/O configuration, MCn bits are the disable/enable interrupt related to the channel n.
MC3..0=1: Any I/O line of the related channel #n is disabled to generate interrupt independently of DMASK setting.
MC3..0=0: Any I/O line of the related channel #n is enabled to generate interrupt depending on DMASK setting.
For static I/O configuration, MCn bits are the interrupt mask bits related to CSn that are configured as I/O lines.
MC0=1: The corresponding I/O cannot generate interrupt independently of DMASK setting.
MC0=0: The corresponding I/O can generate interrupt if a change of status is detected depending of DMASK setting.
MC2=1: The corresponding I/O cannot generate interrupt independently of DATA3_L setting (bit 3..0).
MC2=0: The corresponding I/O can generate interrupt if a change of status is detected depending of DATA3_L
setting (bit 3..0).
MC3 and MC1 bit are not used in static mode.
Input lines with persistency check generate interrupt if the changed status remains stable longer than the time
programmed in the persistency check register PCHKA/B. Line without persistency check generate an immediate interrupt request.
Mask register has no effect on those pins configured as outputs, those pins will not generate interrupt
MCF=1: The corresponding alarm bit (CKF) doesn’t generate interrupt.
MCF=0: The corresponding alarm bit (CKF) can generate interrupt.
MTV=1: The corresponding alarm bit (TV) doesn’t generate interrupt.
MTV=0: The corresponding alarm bit (TV) can generate interrupt.
MPCM =1 : The IPCM interrupt is masked (generation disabled).
MPCM =0 : The IPCM interrupt is enabled (generation enabled).
18/45
STLC5048
Alarm Register (ALARM)
Addr=14h; Reset Value=01h
Read Only
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
0
POR
POR=0: No Power On Reset is detected during operation.
POR=1: A Power On Reset is detected during operation.
The ALARM register is cleared after reading operation only if signals (alarm cause) are inactive.
Configuration Register (CONF)
Addr=20h; Reset Value=BFh
BIt7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
0
1
0
0
0
0
0
RES
LIN
AMU
STA
PD3
PD2
PD1
PD0
RES=0 Normal Operation
RES=1 Device Reset: I/0n and Csn are all inputs, DX is H.I. (equivalent to Hw reset).
LIN=0 A or µ law PCM encoding
LIN=1
Linear encoding (16 bits), two’s complement.
AMU=0 µ law selection (all bits inverted)
AMU=1 A law selection (even bits inverted)
STA=0 CS0 to CS3 scan the four SLICs connected to the I/O control port, each CS has a 31.25µs repetition
time.
STA=1I/O are static, CS0 to CS3 are configured as generic static I/O
PD3..0=0 Codec 3..0 is active
PD3..0=1 Codec 3..0 is in Power Down. When one codec is in Power Down the corresponding VFRO output is
set to AGND and the corresponding transmit time slot on DX is set in H.I.
Command Enable register (COMEN)
Addr=21h; Reset Value=80h
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
0
1
0
0
0
0
1
PDR
0
0
0
E3
E2
E1
E0
The En bits enable a command on one or more channels. All enabled channels will receive the entered data. At
least one channel must be enabled before every command.
E0..3=0: commands disabled on the corresponding channel 0..3
E0..3=1: commands enabled on the corresponding channel 0..3
PDR = 0: RAM is enabled also in Power Down.
PDR = 1: RAM is disabled in Power Down. In this way it’s possible to reduce the power consumption in Power
Down.
19/45
STLC5048
Synchronous Check register (SYNCK)
Addr=23h; Reset Value=E4h
Read Only
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1
0
1
0
0
0
1
1
1
1
1
0
0
1
0
0
This register contains a fixed code (E4h) that can be read to check the synchronisation of the MCU interface.
DSP Status Register (CTRLACK)
Addr=25h; Reset Value=01h
Read Only
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1
0
1
0
0
1
0
1
0
0
0
0
0
0
INIT
CKEND
CKEND bit is 0 while the checksum calculation is performed: in the other time is always set to 1.
INIT bit becomes active (INIT = 1) after the DSP initialization. Normally it requires 70 us after the reset to be set to 1.
Checksum register (CKSUM)
Addr=26h; Reset Value=00h
Addr=27h; Reset Value=00h
Read Only
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1
0
1
0
0
1
1
0
CK7
CK6
CK5
CK4
CK3
CK2
CK1
CK0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1
0
1
0
0
1
1
1
CK15
CK14
CK13
CK12
CK11
CK10
CK9
CK8
The cheksum value is calculated every time the CKSTART instruction is performed and the result is available
after a proper delay (max 400 µs).
This register contains the cheksum value calculated on the contents of the following coefficient (each of 16 bits):
ZERO
KDF0_0 KDF0_1 KDF0_2 KDF1_0 KDF1_1 KDF1_2 KDF2_0 KDF2_1 KDF2_2 KDF3_0 KDF3_1 KDF3_2
AFE_CFF GRX0 GTX0 RFC0_0 ...... RFC0_16 XFC0_0 ...... XFC0_16 BFC0_0 ...... BFC0_25
ZFC0_0 ...... ZFC0_4 GRX1 GTX1 RFC1_0 ...... RFC1_16 XFC1_0 ...... XFC1_16 BFC1_0 ......BFC1_25
ZFC1_0 ...... ZFC1_4 GRX2 GTX2 RFC2_0 ......RFC2_16 XFC2_0 ...... XFC2_16 BFC2_0 ...... BFC2_25
ZFC2_0 ...... ZFC2_4 GRX3 GTX3 RFC3_0 ...... RFC3_16 XFC3_0 ...... XFC3_16 BFC3_0 ...... BFC3_25
ZFC3_0 ......ZFC3_4
20/45
STLC5048
Loopback Register (LOOPB)
Addr=2Ah; Reset Value=00h
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
1
0
1
1
0
1
0
DL3
DL2
DL1
DL0
AL3
AL2
AL11
AL0
DL3..0=0: Normal Operation
DL3..0=1: Codec #3..0 is set in Digital Loopback mode, this means that the receive PCM signal applied to the
programmed Receive Time Slot is transferred to the programmed Transmit Time Slot.
AL3..0=0: Normal Operation
AL3..0=1: Codec #3..0 is set in Analog Loopback mode, this means that the VFRO signal is transferred to the
VFXI input internally into the Codec.
When loopbacks are enabled the signal appears also at the corresponding VFRO output. It is possible to have
no signal on the VFRO output programming the GRX command to 00h in case of digital loopback.
Transmit Preamplifier Gain Register (TXG)
Addr=2Bh; Reset Value=00h
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
0
1
0
1
0
1
1
TG3
TG2
TG1
TG0
TG3..0=0: Transmit preamplifier gain ch. 3..0 = 0dB
TG3..0=1: Transmit preamplifier gain ch. 3..0 = 3.52dB
Overall transmit gain depends on combination of TXG and GTXn registers.
Receive Amplifier Gain Register (RXG)
Addr=2Ch; Reset Value=00h
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
0
1
0
1
1
0
0
R31
R30
R21
R20
R11
R10
R01
R00
Rn0=0,Rn1=0: Receive amp. gain ch #n = mute
Rn0=1,Rn1=0: Receive amp. gain ch #n = -12dB
Rn0=0,Rn1=1: Receive amp. gain ch #n = -6dB
Rn0=1,Rn1=1: Receive amp. gain ch #n = 0dB
Overall receive gain depends on the receive amplifier gain (R3..0) setting in RXG reg. and digital gain (GRXn
reg. setting).
21/45
STLC5048
SLIC Line Current Limit reg (ILIM)
Addr=2Dh; Reset Value=00h
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
0
1
0
1
1
0
1
0
0
0
D4
D3
D2
D1
D0
D4..0 = 0: Programmed value is 53
D4..0 = 1: Programmed value is 2
The step is 1.6 mA
This register allows to program a line current limitation from 2 to 53mA with a step equal to 1.6mA. These values
can be obtained using an external 15KOhm resistor in kit with STLC3080.
SLIC Off-Hook threshold register (ITH)
Addr=2Eh; Reset Value=00h
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
0
1
0
1
1
1
0
0
0
0
En
D3
D2
D1
D0
D3..0 = 0: Programmed value is 16 mA
D3..0 = 1: Programmed value is 1 mA
The step is equal to 1 mA.
En = 1 The DC SLIC programmability block is enabled (ITH and ILIM)
En = 0 The DC SLIC programmability block is disabled (ITH and ILIM)
This register allows to program a threshold value from 1 to 16 mA with a step equal to 1mA. These values can
be obtained using an external 12.5KOhm resistor in kit with STLC3080.
PCM Shift Register (PCMSH)
Addr=50h; Reset Value=00h
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
1
0
1
0
0
0
0
XS2
XS1
XS0
RS2
RS1
RS0
XS2..0:Effective start of the TX frame is the programmed values of clock pulses (0 to 7) after the FS rising edge.
RS2..0:Effective start of the RX frame is the programmed values of clock pulses (0 to 7) after the FS rising edge.
PCM Command register (PCMCOM)
Addr=51h; Reset Value=00h
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
1
0
1
0
0
0
1
RR
WR
PC1
PC0
TE
RPAB
TPB
TPA
22/45
STLC5048
TPA/B = These two bits are used to enable the DX outputs of the port A or/and B. According to the combination
of these two bits the enabled port will be as follows:
TPB
TPA
Description
0
0
Both Ports disabled
0
1
Port A enabled
1
0
Port B enabled
1
1
Both ports enabled
RPAB = 0: Port A enabled (DRA input selected)
RPAB = 1: Port B enabled (DRB input selected)
TE = 0: Transmit PCM data change on rising edge of MCLK
TE = 1: Transmit PCM data change on falling edge of MCLK
PC1-PC0 = Selection of the channel for the PCM access data via MCU.
PC0
PC1
Description
0
0
Channel #0 selected
1
0
Channel #1 selected
0
1
Channel #2 selected
1
1
Channel #3 selected
WR = 1: Setting this bit , receive PCM data writing via MCU (after A/µ decoding) is enabled on selected channel
and IPCM interrupt is generated every time FS signal becomes active, together to the set of the WRD bit in the
PCMCTRL register.
A data byte must be written every 125µs, if data is not replaced the old value is inserted again but the PMW bit
is set to 1 in the PCMCTRL register.
RR = 1: Setting this bit, transmit PCM data reading (after A/µ encoding) via MCU is enabled on selected channel
and IPCM interrupt is generated every time that data are available, together to the set of the RRD bit in the PCMCTRL register.
A data byte must be read every 125µS, if data is not read the new value is written in the PCM access register
but the POW bit is set to 1 in the PCMCTRL register.
Transmit Time Slot ch #0 (DXTS0)
Addr=52h; Reset Value=00h
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
1
0
1
0
0
1
0
EN0
T06
T05
T04
T03
T02
T01
T00
EN0=0:Selected transmit time slot on DX output is in H.I.
EN0=1:Selected transmit time slot on DX output is active carrying out the PCM encoded signal of VFXI0.
T06..0:Define time slot number (0 to 127) on which PCM encoded signal of VFXI0 is carried out.
If linear mode is selected (LIN=1 of CONF register) the 16 bits will be carried out as follows: the 8 most significant bits in the programmed time slot, the 8 least significant bits in the following time slot.
Example: if T06..T00=00:
TS0
15
14
13
12
TS1
11
10
9
8
7
6
5
4
3
2
1
0
23/45
STLC5048
Transmit Time Slot ch #1 (DXTS1)
Addr=53h; Reset Value=00h
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
1
0
1
0
0
1
1
EN1
T16
T15
T14
T13
T12
T11
T10
EN1=0: Selected transmit time slot on DX output is in H.I.
EN1=1: Selected transmit time slot on DX output is active carrying out the PCM encoded signal of VFXI1.
T16..0: Define time slot number (0 to 127) on which PCM encoded signal of VFXI1 is carried out.
If linear mode is selected (LIN=1 of CONF register) the 16 bits will be carried out as follows: the 8 most significant bits in the programmed time slot, the 8 least significant bits in the following time slot.
Example: if T16..T10=00:
TS0
15
14
13
12
TS1
11
10
9
8
6
5
4
3
7
2
1
0
Transmit Time Slot ch #2 (DXTS2)
Addr=54h; Reset Value=00h
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
1
0
1
0
1
0
0
EN2
T26
T25
T24
T23
T22
T21
T20
EN2=0: Selected transmit time slot on DX output is in H.I.
EN2=1: Selected transmit time slot on DX output is active carrying out the PCM encoded signal of VFXI2.
T26..0: Define time slot number (0 to 127) on which PCM encoded signal of VFXI2 is carried out.
If linear mode is selected (LIN=1 of CONF register) the 16 bits will be carried out as follows: the 8 most significant bits in the programmed time slot, the 8 least significant bits in the following time slot.
Example: if T26..T20=00:
TS0
15
14
13
12
TS1
11
10
9
8
6
5
4
3
7
2
1
0
Transmit Time Slot ch #3 (DXTS3)
Addr=55h; Reset Value=00h
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
1
0
1
0
1
0
1
EN3
T36
T35
T34
T33
T32
T31
T30
EN3=0: Selected transmit time slot on DX output is in H.I.
EN3=1: Selected transmit time slot on DX output is active carrying out the PCM encoded signal of VFXI3.
T36..0: Define time slot number (0 to 127) on which PCM encoded signal of VFXI3 is carried out.
If linear mode is selected (LIN=1 of CONF register) the 16 bits will be carried out as follows: the 8 most significant bits in the programmed time slot, the 8 least significant bits in the following timeslot.
24/45
STLC5048
Example: if T36..T30=00:
TS0
15
14
13
12
TS1
11
10
9
8
6
5
4
3
7
2
1
0
Receive Time Slot ch #0 (DRTS0)
Addr=56h; Reset Value=00h
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
1
0
1
0
1
1
0
EN0
R06
R05
R04
R03
R02
R01
R00
EN0=0: Disable reception of selected time slot.
EN0=1: Selected receive time slot on DR input is PCM decoded and transferred to VFRO0 output.
R06..0: Define receive time slot number (0 to 127) on carrying the PCM signal to be decoded and transferred
to VFRO0 output. If linear mode is selected (LIN=1 of CONF register) the 16 bits will be used as linear code as
follows: the 8 most significant bits in the programmed time slot, the 8 least significant bits in the following
timeslot.
Example: if R06..R00=00:
TS0
15
14
13
12
TS1
11
10
9
8
6
5
4
3
7
2
1
0
Receive Time Slot ch #1 (DRTS1)
Addr=57h; Reset Value=00h
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
1
0
1
0
1
1
1
EN1
R16
R15
R14
R13
R12
R11
R10
EN1=0: Disable reception of selected time slot.
EN1=1: Selected receive time slot on DR input is PCM decoded and transferred to VFRO1 output.
R16..0: Define receive time slot number (0 to 127) on carrying the PCM signal to be decoded and transferred
to VFRO1 output. If linear mode is selected (LIN=1 of CONF register) the 16 bits will be used as linear code as
follows: the 8 most significant bits in the programmed time slot, the 8 least significant bits in the following time
slot.
Example: if R16..R10=00:
TS0
15
14
13
12
TS1
11
10
9
8
6
5
4
3
7
2
1
0
Receive Time Slot ch #2 (DRTS2)
Addr=58h; Reset Value=00h
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
1
0
1
1
0
0
0
EN2
R26
R25
R24
R23
R22
R21
R20
25/45
STLC5048
EN2=0: Disable reception of selected time slot.
EN2=1: Selected receive time slot on DR input is PCM decoded and transferred to VFRO2 output.
R26..0: Define receive time slot number (0 to 127) on carrying the PCM signal to be decoded and transferred
to VFRO2 output.
If linear mode is selected (LIN=1 of CONF register) the 16 bits will be used as linear code as follows: the 8 most
significant bits in the programmed time slot, the 8 least significant bits in the following timeslot.
Example: if R26..R20=00:
TS0
15
14
13
12
TS1
11
10
9
8
6
5
4
3
7
2
1
0
Receive Time Slot ch #3 (DRTS3)
Addr=59h; Reset Value=00h
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
1
0
1
1
0
0
1
EN3
R36
R35
R34
R33
R32
R31
R30
EN3=0: Disable reception of selected time slot.
EN3=1: Selected receive time slot on DR input is PCM decoded and transferred to VFRO3 output.
R36..0: Define receive time slot number (0 to 127) on carrying the PCM signal to be decoded and transferred
to VFRO3 output. If linear mode is selected (LIN=1 of CONF register) the 16 bits will be used as linear code as
follows: the 8 most significant bits in the programmed time slot, the 8 least significant bits in the following
timeslot.
Example: if R36..R30=00:
TS0
15
14
13
12
TS1
11
10
9
8
6
5
4
3
7
2
1
0
PCMW Data Register (PCMWD)
Addr=5Ah; Reset Value=00h
Addr=5Bh; Reset Value=00h
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
1
0
1
1
0
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
1
0
1
1
0
1
1
D15
D14
D13
D12
D11
D10
D9
D8
This register is used to write receive PCM data via the MCU interface. Writing this register the IPCM interrupt
(if generated only by writing access) is automatically cleared.
In A/µ law only the first 8 bit are used. In linear code option both registers must be used.
26/45
STLC5048
PCMR Data Register (PCMRD)
Addr=5Ch; Reset Value=00h
Addr=5Dh; Reset Value=00h
Read only
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1
1
0
1
1
1
0
0
D7
D6
D5
D4
D3
D2
D1
D0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1
1
0
1
1
1
0
1
D15
D14
D133
D12
D11
D10
D9
D8
This register is used to read transmit PCM data via the MCU interface. Reading this register the IPCM interrupt
(if generated only by reading access) is automatically cleared.
In A/µ law only the first 8 bit are used. In linear code option both registers must be read, first the LSB and after
the MSB.
PCM Control Register (PCMCTRL)
Addr= 5Eh; Reset Value=00h
Read only
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1
1
0
1
1
1
1
0
RRD
WRD
POW
PMW
PMW = 1: Data is not written every FS while writing PCM access data is enabled.
POW = 1: Data is not read every FS while reading PCM access data is enabled.
WRD = 1: Device is waiting for PCM data insertion in PCMWD register. The bit is reset after writing at least one byte.
RRD = 1: Data are available on PCMRD register. The bit is reset after reading the two bytes of the register (first
the LSB and after the MSB).
Tone Generation register (TONEG)
Addr=60h; Reset Value=00h
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
1
1
0
0
0
0
0
T31
T30
T21
T20
T11
T10
T01
T00
Tn0=0,Tn 1=0: No tone is generated on ch #n
Tn0=1,Tn 1=0: A tone with 25Hz frequency is generated on ch #n.
Tn0=0,Tn 1=1: A tone with 1KHz frequency is generated on ch #n.
Tn0=1,Tn 1=1: A tone with 3KHz frequency is generated on ch #n.
This register allows the generation of a tone in the RX direction.
27/45
STLC5048
Coefficient State register (COEFST)
Addr= 61h; Reset Value=F0h
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
1
1
0
0
0
0
1
FD3
FD2
FD1
FD0
FR3
FR2
FR1
FR0
FR0..3=1: All channel filters and gain blocks are configured as defined in the ringing state
FR0..3=0: All channel filters and gain blocks are configured as defined with the programmed value if also the
corresponding FD bit is set to 0
FD0..3=1: All channel filters and gain blocks are configured as defined in the default state if also the corresponding FR bit is set to 0
FD0..3=0: All channel filters and gain blocks are configured as defined with the programmed value if also the
corresponding FR bit is set to 0
Software Revision ID Code (SWRID)
Addr=70h; Read only.
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
0
This register contains the DSP Software revision Code identifier.
Hardware Revision ID Code (HWRID)
Addr=71h; Read only.
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1
1
1
1
0
0
0
1
0
0
0
0
0
0
0
1
This register contains the Silicon revision Code identifier.
SINGLE BYTE INSTRUCTION
Name
Description
ID
REACOM
Realignment command
28h
CKSTART
Start Checksum
29h
Realignment Command (REACOM)
This single instruction is used to realign the MCU interface in case of out of synchronisation. This instruction
must be executed Nmax+1 times to be successfull.
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0
0
1
0
1
0
0
0
28/45
STLC5048
Start Checksum Calculation (CKSTART)
This single instruction is used to start the checksum calculation of the enetered data used to configure the device.
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0
0
1
0
1
0
0
1
COMMAND LIST
Name
Description
ID
BLKEN
Block enable
22h
KDF
KD Filter
30h
AFECFF
AFE KA Coefficient (*)
31h
T_OUT
Timeout value (*)
32h
GRX
Receive Gain
40h
GTX
Transmit Gain
41h
RFC
R Filter Coefficient
42h
XFC
X Filter Coefficient
43h
BFC
B Filter Coefficient
44h
ZFC
Z Filter Coefficient
45h
(*) For this two commands the bit set in the COMEN register are not considered.
COMMAND DESCRIPTION
Each command is transferred on every channel that has the proper bit in the COMEN register set to 1.
Block Enable command (BLKEN)
Reset Value=00h
The command is used to enable/disable the B, Z, R and X blocks
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
0
1
0
0
0
1
0
XE
RE
ZE
BE
BE=1: The B block is equal to an open circuit
BE=0: The B block is configured as defined in the Ringing state or with the programmed value
ZE=1: The Z block is equal to an open circuit
ZE=0: The Z block is configured as defined in the Ringing state or with the programmed value
RE=1: The R block is equal to a short circuit
RE=0: The R block is configured as defined in the Ringing state or with the programmed value
XE=1: The X block is equal to a short circuit
XE=0: The X block is configured as defined in the Ringing state or with the programmed value
29/45
STLC5048
KD Filter (KDF)
The register is used to set the 3 coefficients (each of 16 bits) of the KD filter of the channel #n.
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
0
1
1
0
0
0
0
.
..
AFE Coefficient (AFE_CFF)
Reset value = AA00h
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
0
1
1
0
0
0
1
KA31
KA30
KA21
KA20
KA11
KA10
KA01
KA00
TTX
KAn0, KAn1 = KA coefficient for Ch #n
According to the value of each couple of bits, the KA block is set in the following condition:
KAn1 KAn0
0
X
KA block disabled
1
0
KA set for low gain
1
1
KA set for high gain
When the application involves also the metering pulse signal the AFE of the STLC5048 must be adapted in order to manage also this signal. For this purpose is provided the TTX bit.
TTX = 0: the current application is not using the metering pulse signal
TTX = 1: the current application is using the metering pulse signal
Timeout value (T_OUT)
Reset Value=FFFFh
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
0
1
1
0
0
1
0
T7
T6
T5
T4
T3
T2
T1
T0
T15
T14
T13
T12
T11
T10
T9
T8
Reset value = Maximum value = FFFFh (2048 us)
To disable this function the T0 bit must be set to 0.
To enable this function the T0 bit must be set to 1; the time-out value is set by means of T<15..1> bits.
Time_out = (T_OUT[15:1]*62.5 + 31.24)ns
The minimum step is 62.5 ns.
30/45
STLC5048
Receive Gain (GRX)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
1
0
0
0
0
0
0
00h: Stop any received signal to reach the VFRO0 analog output. In order to open the impedance synthesis
feedback it’s necessary to mute the RX analog amplifier, as well.
>00h: Digital gain is inserted in the RX path equal to:
20Log[prog.value/32768]
The prog. value must be espressed in 16 bits signed format: maximum prog. value is equal to 7FFFh.
Transmit Gain (GTX)
00h:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
1
0
0
0
0
0
1
Stop any transmit signal, null level is transmitted in the corresponding timeslot on DX output.
>00h: Digital gain is inserted in the TX path equal to:
20Log[prog.value/32768]
The prog. value must be espressed in 16 bits signed format: maximum prog. value is equal to 7FFFh.
R Filter Coefficient (RFC)
The register is used to set the 17 coefficients (each of 16 bits) of the R filter of the channel #n.
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
1
0
0
0
0
1
0
.
.
X Filter Coefficient (XFC)
The register is used to set the 17 coefficients (each of 16 bits) of the X filter of the channel #n.
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
1
0
0
0
0
1
1
.
.
31/45
STLC5048
B Filter Coefficient (BFC)
The register is used to set the 26 coefficients (each of 16 bits) of the B filter of the channel #n.
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
1
0
0
0
1
0
0
.
.
Z Filter Coefficient (ZFC)
The register is used to set the 5 coefficients (each of 16 bits) of the Z filter of the channel #n.
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
1
0
0
0
1
0
1
.
.
32/45
STLC5048
ELECTRICAL CHARACTERISTCS
Typical value are for 25°C and nominal supply voltage. Minimum and maximum values are guaranteed over the
temperature 0-70°C range by production testing and supply voltage range shown in the Operating Ranges. Performances over -40 +85°C range are guaranteed by product characterisation unless otherwise specified.
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
DIGITAL INTERFACE
Vil
Input Voltage Low DI pins
0
0.2Vdd
V
Vih
Input Voltage High DI pins
0.8Vdd
5.5
V
Iil
Input Current Low DI pins
-10
10
µA
Iih
Input Current High DI pins
-10
10
µA
Ci
Input Capacitance (all dig. inp.)
5
Vol
Output Voltage Low DX, TSX pins Iol=3.2mA (other pins Iol=1mA)
Voh
Output Voltage High DX pin
Ioh=-3.2mA (other pins Iol=1mA)
pF
0
0.4
V
0.85Vdd
Vdd
V
Note: all digital input are 5V tolerant.
ANALOG INTERFACE
RIX
Transmit Input Amplifier Input
Impedance (VFXI)
1
MΩ
ROR
Receive Output Impedance
1
Ω
POWER DISSIPATION
Idd(pd)
Power down Current
10
15
mA
Idd(act)
Active Current
55
70
mA
PCM INTERFACE TIMING
f(MCLK)
Master Clock Frequency
1.536
1.544
2.048
4.096
8.192
MHz
Twmh
Period of MCLK high
38
ns
Twml
Period of MCLK low
38
ns
Trm
MCLK rise time
10
ns
10
ns
Tfm
MCLK fall time
Thbf
Hold Time MCLK Low to FSX/R
High or Low
10
ns
Tsfb
Setup time FSX/R High to MCLK Low
10
ns
Tdmd
Delay Time, MCLK High to Data Valid
Tdmz
Delay Time from MCLK(8) Low to
Data Output disabled
Tdfd
15
ns
40
ns
Delay Time, FSX High to Data
Valid if FSX rises later than MCLK
rising edge
15
ns
Tdmt
Delay Time, from MCLK and FSX
both high to TSX Low
20
ns
Tzmt
Delay time from MCLK(8) low to
TSX disabled
15
40
ns
Tsdm
Setup time, DR Valid to MCLK Low
5
ns
Thdm
Hold time, MCLK Low to DR
invalid
5
ns
15
33/45
STLC5048
ELECTRICAL CHARACTERISTCS (continued)
Figure 4.
TFM
TWMH
TRM
MCLK
1
2
THBF
THBF
TSFB
3
4
5
6
7
8
9
10
TWML
FSX
TDFD
TZMT
TDMD
DX
7
6
5
4
3
2
1
0
TDMT
TZMT
TDMT
TSX
TSFB
THBF
THBF
FSR
THDM
TSDM
DR
7
6
5
4
3
2
1
0
D94TL157
SERIAL CONTROL PORT TIMING
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
8
MHz
fcclk
Frequency of CCLK
twch
Period of CCLK High
Measured from VIH to VIH
40
ns
twcl
Period of CCLK Low
Measured from VIL to VIL
40
ns
trc
Rise time of CCLK
Measured from VIL to VIH
20
ns
tfc
Fall time of CCLK
Measured from VIH to VIL
20
ns
thcs
Hold time, CCLK low to CS low
10
ns
thsc
Hold time, CCLK low to CS high
10
ns
tssc
Setup time, CS transition to CCLK
Low
10
ns
tdsd
Delay time, CS low to CO data valid
tcso
CS off time
5
us
tsdc
Setup time, CI. Data in to CCLK low
10
ns
thcd
Hold time, CCLK low to CI invalid
10
ns
tdcd
Delay time, CCLK low to CO Data
Out Valid
tddz
Delay Time, CS or CCLK9 high to
CO high impedance
34/45
20
Pull up resistor = 1KOhm
Cload = 30pF
ns
30
ns
30
ns
STLC5048
ELECTRICAL CHARACTERISTCS (continued)
Figure 5.
tRC
CCLK
1
tHCS
2
tFC
3
4
5
tWCH
6
7
tSSC
8
tHSC
tSCS
tWCL
CS
tSDC
CI
7
6
5
4
3
tHCD
2
1
tCSO
0
tDSD
CO
7
tDCD
6
5
4
3
2
1
D00TL471
SLIC CONTROL INTERFACE TIMING (dynamic configuration)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
31.25
µs
Chip select pulse width
3.9
µs
tdcsl
Data out valid to CS low
1.95
ns
tscsh
Data out held after CS high
1.95
ns
tscsh
Set up time Data in to CS high
50
ns
thcsh
Hold time data in to CS high
10
ns
Tcs
Chip Select repetition rate
tcsw
Figure 6. SLIC Control port timing
tDIV
tDOA
tDII
tDON
31.25µs (32KHz)
CS1
CS2
CS3
CS4
IO
(OUT)
OUT
CH0
OUT
CH1
OUT
CH2
OUT
CH3
OUT
CH0
OUT
CH1
IO
(IN)
IN
CH0
IN
CH1
IN
CH2
IN
CH3
IN
CH0
IN
CH1
D99TL460
35/45
STLC5048
ELECTRICAL CHARACTERISTICS (continued)
TRANSMIT TRANSFER CHARACTERISTICS
(all tests are performed in absolute gain condition (TXG = GTXn = 0dB) unless otherwise specified).
Symbol
Parameter
Test Condition
Min.
Absolute level at 0 dBm0 are:
TXG = 0dB, GTXn = 0dB
GXA
Typ.
Max.
60
Unit
mVrms
Transmit gain Absolute accuracy
-0.15
0.15
dB
GXAG
Transmit gain variation with programmed
gain (within 3 dB from max dig. level)
-0.2
0.2
dB
GFX
Gain variation with frequency (relative to
gain at 1004Hz); 0dBm0 input signal
dB
50 Hz
60Hz
200Hz
300-3000Hz
3400Hz
4000Hz
4600Hz and above
-1.8
-0.15
-0.7
-20
-20
0
0.15
0
-14.0
-32.0
GAXT
Gain variation with temperature
-0.10
0.10
dB
GAXE
Gain variation with Supplies +/- 5%
0dBm0 Input Signal
-0.05
0.05
dB
GTX
QDX
Gain Tracking with Tone (1004Hz Mu
Law, 820Hz A Law) (1)
dB
GSX = 3 to -40dBm0
GSX = -40 to -50dBm0
GSX = -50 to -55dBm0
-0.2
-0.4
-1.2
0.2
0.4
1.2
Quantization Distortion with Tone
(1004Hz Mu Law, 820Hz ALaw)
dB
VFXI = +3dbm0
VFXI = 0 to -30dBm0
VFXI = -40 dBm0
VFXI = -50 to -55 dBm0
33
36
30
15
NCT
Transmit Noise C Message Weighted
(Mu and A Law)
12
dBrnCo
NPT
Transmit Noise Psophometric Weighted
@ 0dBr, Zadm=600Ohm (2)
-68
dBm0p
DAX
Absolute Delay (3)
587
µS
DPXM
DPXA
GSPX
B = 0, Z = 0, X = R = 1
462
Single Frequency Distortion
(Mu Law 0dBm0 Sinewave @ 1004Hz)
-46
Single Frequency Distortion
(A Law 0dBm0 Sinewave @ 820Hz)
-46
Out of Band Spurious Noise
dB
dB
61mVrms at VFXI
4200Hz to 72kHz
-39
dBm0
(1) VFXI=106mVrms, TXG=+3.52dB, GTX=-8.308dB (levels and gain condition eqivalent to 0dBr with Zadm = 600 Ohm on the application)
(2) TXG=+3.52dB, GTX=-8.308dB (gain condition eqivalent to 0dBr with Zadm = 600 Ohm on the application)
(3) The max value includes 125µsec for the time slot synchronization
36/45
STLC5048
ELECTRICAL CHARACTERISTICS (continued)
RECEIVE TRANSFER CHARACTERISTICS
(all tests are performed in absolute gain condition (RXG = GRXn = 0dB) unless otherwise specified).
Symbol
Parameter
Test Condition
Min.
Absolute levels at 0 dBm0 are:
RXG = 0dB, GRXn = 0dB
GRA
Typ.
Max.
547
Unit
mVrms
Transmit gain Absolute accuracy
-0.15
0.15
dB
GRAG
Receive Gain Variation with
programmed gain (within 3 dB from max
dig. level)
-0.2
0.2
dB
GFR
Gain variation with frequency (relative to
gain at 1004Hz); 0dBm0 input signal
GART
Gain variation with temperature
GARE
Gain variation with
Vcc=Vdd= 3.3V +/- 5%
0dBm0 Input Signal
GTR
dB
Below 200Hz
200Hz
300-3000Hz
3400Hz
4000Hz
-0.25
-0.15
-0.7
0.115
0.15
0.15
0
-14
0 to 70 °C
-0.10
0.10
dB
-0.05
0.05
dB
Gain Tracking with Tone (1004Hz Mu
Law, 820Hz ALaw)
dB
DR = 3 to -40dBm0
DR = -40 to -50dBm0
DR = -50 to -55dBm0
QDR
NCR
Receive Noise C Message Weighted
(Mu Law)
NPR
Receive Noise Psophometric Weighted
(A Law)
DAR
Absolute Delay (2)
GSPR
OBN
0.2
0.4
1.2
Quantization Distortion with Tone
(1004Hz Mu Law, 820Hz ALaw)
dB
DR
DR
DR
DR
DPR1
-0.2
-0.4
-1.2
= 3 dBm0
= 0 to -30dBm0
= -40 dBm0
= -50 to -55dBm0
33
36
30
15
8
B = Z = 0, X = R = 1
325
Single Frequency Distortion
(0dBm0 Sinewave @ 1004Hz)
Out of band spourious Noise
Out of Band Noise (1)
11
dBrnCo
-79
dBm0p
450
µs
dB
-46
0dBm0 DTMF tone at DR
-60
dB
0dBm0 180 to 3600Hz
Sinewave at DR
-43
dB
-48
-51
dBm
dBm
-70
dBm
Integral measure
from 3.4 to 128kHz
GTX = GRX = 0dB
GTX = 0dB; GRX = -7dB
Spectral measure
from 3.4 to 200kHz
in B/W = 30Hz
(1) Values related to the application including the external filter on RX. The maesure is referred to the signal replicas.
(2) As note 3 at page 36
37/45
STLC5048
ELECTRICAL CHARACTERISTCS (continued)
SUPPLY REJECTION AND CROSSTALK
Symbol
Parameter
Test Condition
0 to 70°C
Min.
Typ.
42
65
Max.
Unit
PSRR
Power Supply Rejection Ratio
1KHz, 50mVrms
CTX-R
Transmit to Receive Crosstalk (Input
signal 200Hz to 3450Hz at 0dBm0)
-76
dB
CTR-X
Receive to Transmit Crosstalk (Input
signal 200Hz to 3450Hz at 0dBm0)
-76
dB
CT-ICH
Inter Channel Crosstalk, TX and RX
direction.
Input 200 to 3450 Hz at 0dBm0 at VFXI
of one channel; all other VFXI inputs
and all DR inputs receive idle signal.
Output is measured at DX of the 3 idle
channels.
-78
dB
Input of 200 to 3450 Hz at 0dBm0 PCM
at DR on ione channel. All other DR
inputs and all VFXI inputs receive idle
signal. Output is measured at VFRO of
the 3 idle channels
Figure 7. Group Delay Distortion Mask
Delay
(µs)
600
500
400
Rx direction
300
200
100
0
Delay
(µs)
600
500
400
Tx direction
300
200
100
0
38/45
Rx
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
500
1000
1500
2000
2500
Tx
D02TL523
3000
f(Hz)
D02TL524
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
500
1000
1500
2000
2500
3000
f(Hz)
dB
STLC5048
APPENDIX A
STLC5048 absolute gains in kit with L3235N/STLC3080
Figure 8. STLC5048 in kit with STLC3080 AC application diagram.
TIP
STLC5048
DR
1
CHANNEL
FILTER
GRX
+
VFRO
RX
RP
2
Zadm
Iline
-1
DX
GTX
+
Z
SYNTHESIS
VFXI
CHANNEL
FILTER
CAC
RS
TX
RP
ILTF
1
RDC
Iline/100
ECO
CANCELING
RING
RS
8200Ω
D00TL472
Figure 9. STLC5048 in kit with L3235N AC application diagram.
TIP
STLC5048
DR
1
CHANNEL
FILTER
GRX
+
VFRO
RX
2
RP
Zadm
Iline
-1
DX
GTX
+
Z
SYNTHESIS
CHANNEL
FILTER
VFXI
TX
RPC
RP
CAC
IL
1
RS
4100Ω
D00TL473
Iline/50
ECO
CANCELING
RING
In Fig.8 is shown the application diagram of the STLC5048 in kit with the STLC3080 SLIC. The figure is related
to the AC path as the STLC5048 doesn't perform any DC processing.
The only DC feature performed by STLC5048 is the Off-Hook and Limitation Threshold programmability.
The same application diagram for the AC processing can be applied to the kit with the L3235N (as shown in Fig.
9): the only differences are the following:
The scaling factor of the Iline is 50
Rs value is 4.1 Kohm.
The imoedance synthesis is fully performed by STLC5048; the L3235N SLIC (or the STLC3080) used in kit with
the STLC5048 just splits the AC/DC component of Iline, scales it and traduces it into a voltage via RS.
As shown in Fig. 3, the scaled current is converted into a voltage through the external resistor Rs = 4100 Ohm
(8200 Ohm for the STLC3080): this value is fixed (i.e. independent on the administration): the attenuation between VLINE and VFXI is dependent on the administration.
Considering the TX gain we can proceed as follows for the gain calculation:
TXG = 0dB
GX = 0dB
39/45
STLC5048
(As reported in the absolute gain levels with 61Vrms at VFXI and GX=0dB, the DX output is 0dBm0).
For instance let's calculate which TX gain to program if +4.2dBr @ 600 Ohm is to be set:
VLINE = 0dBm @ 600Ohm
VLIN E 1
VFXI = ------------------- ⋅ ------ ⋅ 4100
600
50
In case of STLC3080 the scaling factor is 100 (instead of 50) while the Rs value is 8200 (instead of 4100) so
the result is the same.
VLINE 1
VFXI = ------------------- ⋅ ---------- ⋅ 8200
100
600
Refering to the formula (1), to have DX equal to 4.2dB with VLINE=0dBm GX must be set to GX = 4.2 - 4.78 =
-0.58dB.
Figure 10. Absolute gain in TX path.
1/100 for
STLC3080
GX
TXG
STLC5048
VFXI = (-Iline/50)*4100 for L3235N
VFXI = (-Iline/100)*8200 for STLC3080
40/45
VLINE
VFXI
DX
1/50
RS
4100Ω
(8200 for
STLC3080)
Iline
Zadm
L3235N
D00TL474
SERIAL
CONTROL
PORTS
VCC
CI
CO
VFXI3
VFRO3
VFXI2
VFRO2
VFXI1
VFRO1
IO15(CS3)
IO14(CS2)
IO13(CS1)
IO12(CS0)
IO11
0.1µF
17
7
ZB
4
1
6
0.1µF
CVSS
2
0.1µF
CVB
CS
VBAT
35
14
24
20
34
22
44
40
38
18
6
CS
39
29
2
GND
RP1
CGF
390nF
GKF
REF
LIM
VPOL
RTF
BASE
VREG
10µF
RT
1MΩ
RR
51K
VBAT
RLIM
9.1K
to 35K
TEXT
MJE350
D2
1N4007
RGF
39K
RP1
82Ω
82Ω
D1
1N4007
CAC
100µF
7
5
RING 40Ω
TIP
IL
CAC
3
VCC
40Ω
0.1µF
L3234
0.1µF
VBAT
L3235N
10
GND
VA
AGND
4.7µF
VSS
D98TL381B
VCC
VSS
13
3
32
28
27
25
31
9
43
11
12
CVCC
VCC
GDK
IO4
CCLK
SBY
PUNEG
IO3
RNG
IO2
IO1
OH
CTX 100nF
IO0
ZAC
150Ω
ZA
RX
TX
10nF
1M
100nF
ZS=4100Ω
VFXI0
SUB
10nF
VDD
0.1µF
2.2KΩ
VFRO0
VSS
VDD
BGND
STLC5048
VEE
VCC
VRING
CS
RES
INT
TSX
MCLK
FS
DR
DX
GND
0.1µF
VCC
V100
RP2 20Ω
CR
4.7µF
CF
390nF
RP2 20Ω
OVERVOLTAGE
PROTECTION
10µF
RF
39K
RING
TIP
STLC5048
STLC5048 Application Diagrams
APPENDIX B
Figure 11. STLC5048 plus L3235N/L324 kit application diagram
41/45
42/45
CAP
0.1µF
SERIAL
CONTROL
PORTS
PCM
INTERFACE
0.1µF
VDD
CAP
CI
CO
CCLK
CS
INT
M1
M0
TSX
MCLK
FS
DRB
DXB
DRA
DXA
SUB
VSS
VDD
GND
40
VBG
ILIM
47
ITH
53
6
46
48
43
42
38
39
53
29
62
24
23
22
21
20
19
35
33
VFXI3
TTX
TO OTHER
SLICs
Components
needed only for
metering pulse injection
VFRO3
VFXI2
VFRO2
VFXI1
VFRO1
CS3
CS2
CS1
CS0
IO5
RDA
17
41
22
18
19
20
21
CTTX
RTTX
VDD
24
9
26
CAC
29
RDC
25
RTH
RDC
RLIM
31
BGND
ITH
37
30
STLC3080
AGND
ILTF
10
VCC(5V)
VCC
CAC
VDD(3.3V)
23
42
8
2
1
7
6
5
4
3
44
43
TTXIN
CKRING
RES
CSIN
CSOUT
R1
R0
D2
D1
IO4
D0
IO3
DET
TX
IO2
TO OTHER SLICs
RX
ZB
RS
ZAC
MODE
RS
150Ω
GDK/AL
IO6
CTX 100nF
1M
100nF
10nF
ZAC1
IO1
IO0
VFXI0
10nF
2.2KΩ
VFRO0
IO11
IO10
58
57
59
IO8
IO7
VCC(3.3V)
IO9
60
61
28
34
STLC5048
VCC
5
49
VEE
VCC
7
4
3
54
27
12
13
14
16
15
10
11
41
8
9
0.1µF
RLIM
13
32
11
RP1
REF
CRT
CVB
RS2
RS1
VBAT
TO OTHER
SLICs
CRT
CREV
CSRV
VBAT
BASE
VREG
RT2
RT1
RING RP1
PCD
TIP
RELR
REL1
IREF
33
34
16
35
36
27
28
38
40
39
14
12
REL0
CREV
QEXT
VBAT
RP2
RP2
CSRV
VRING
RR
RT
D99TL459C
TIP
RING
BGND and AGND must be
shorthed together on the line card
VBAT
LCP
1511
VREL
STLC5048
Figure 12. STLC5048 plus STLC3080 application diagram.
STLC5048
APPENDIX C
Power Up Sequence
The DSP after an HW (M1=0) or SW reset (CONF[7]=1) or a Power-on reset (POR) has to perform the INIT
proram. To do it at least one channel must be set in active mode.
After that, (2 FS are required), the INIT bit in the CTRLACK register is set to 1 and the RAM can be written and
read. It must be noted that to program the device the MCLK and FS signals must be applied to the device.
Following, the correct sequence that must be used in order to program the device.
Power on sequence
wait 5 FS signals for PLL locking
CONF=BF
Sw Reset enabled after reset
write CONF=3F
Sw Reset disabled
write CONF=30
All Channel Active
wait 2 FS signals
read CTRLACK=03 Check INIT bit =1
Before to start the coefficent download, one or more channels must be selected using the COMEN register. The
download can be done keeping the device in Active mode (at least one channel active) or in Power Down mode
(all channels in Power Down). If the second choice is selected, the PDR bit in the COMEN register must be set
to 0 (internal RAM active also in Power Down mode).
43/45
STLC5048
mm
DIM.
MIN.
inch
TYP.
MAX.
A
MIN.
TYP.
1.60
A1
0.05
A2
1.35
B
C
0.063
0.15
0.002
0.006
1.40
1.45
0.053
0.055
0.057
0.18
0.23
0.28
0.007
0.009
0.011
0.12
0.16
0.20
0.0047 0.0063 0.0079
D
12.00
0.472
D1
10.00
0.394
D3
7.50
0.295
e
0.50
0.0197
E
12.00
0.472
E1
10.00
0.394
E3
7.50
0.295
L
0.40
0.60
L1
0.75
OUTLINE AND
MECHANICAL DATA
MAX.
0.0157 0.0236 0.0295
1.00
0.0393
TQFP64
0°(min.), 7°(max.)
K
D
D1
A
D3
A2
A1
48
33
49
32
0.10mm
E
E1
E3
B
B
Seating Plane
17
64
1
16
C
L
L1
e
K
TQFP64
44/45
STLC5048
ESD - The STMicroelectronics Internal Quality Standards set a target of 2 KV that each pin of the device should withstand in a series of tests
based on the Human Body Model (MIL-STD 883 Method 3015): with C = 100pF; R = 1500W and performing 3 pulses for each pin versus
VCC and GND.
Device characterization showed that, in front of the STMicroelectronics Internaly Quality Standards, pin 25 of STLC5048 withstand at least
1000V.
The above points are not expected to represent a pratical limit for the correct device utilization nor for its reliability in the field. Nonetheless
they must be mentionned in connection with the applicability of the different SURE 6 requirements to STLC5048.
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
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45/45