ETC AM79Q02JC

Am79Q02/021/031
Quad Subscriber Line Audio-Processing Circuit
(QSLAC™) Devices
DISTINCTIVE CHARACTERISTICS
Performs the functions of four codec/filters
Software programmable:
— SLIC input impedance
— Transhybrid balance
— Transmit and receive gains
— Equalization (frequency response)
— Digital I/O pins
— Programmable debouncing on one input
— Time slot assigner
— Programmable clock slot and PCM transmit clock
edge options
Standard microprocessor interface
A-law, µ-law, or linear coding
Single or Dual PCM ports available
— Up to 128 channels (PCLK at 8.192 MHz) per
PCM port
— Optional supervision on the PCM highway
1.536, 1.544, 2.048, 3.072, 3.088, 4.096, 6.144,
6.176, or 8.192 MHz master clock derived from
MCLK or PCLK
Built-in test modes with loopback, tone
generation, and µP access to PCM data
Low-power, 5.0 V CMOS technology
5.0 V only operation
Mixed state (analog and digital) impedance
scaling
Performance characteristics guaranteed over a
12 dB gain range
Real Time Data register with interrupt (open
drain or TTL output)
Supports multiplexed SLIC inputs
Broadcast state
256 kHz or 293 kHz chopper clock for Legerity
SLICs with switching regulator
Maximum channel bandwidth for V.34 modems
GENERAL DESCRIPTION
The Am79Q02/021/031 Quad Subscriber Line AudioProcessing Circuit (QSLAC) devices integrate the key
functions of analog linecards into high-performance,
very-programmable, four-channel codec-filter devices.
The QSLAC devices are based on the proven design
of Legerity’s reliable SLAC™ device families. The
advanced ar chitecture of the Q SLAC devic es
implements four independent channels and employs
digital filters to allow software control of transmission,
thus providing a cost-effective solution for the audioprocessing function of programmable linecards.
Advanced submicron CMOS technology makes the
Am79Q02/021/031 QSLAC devices economical, with
both the functionality and the low power consumption
needed in linecard designs to maximize linecard
density at minimum cost. When used with four Legerity
SLICs, a QSLAC device provides a complete softwareconfigurable solution to the BORSCHT functions.
Publication# 080147 Rev: H Amendment: /0
Issue Date: September 2001
TABLE OF CONTENTS
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Connection Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Transmission Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Attenuation Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Group Delay Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Variation of Gain with Input Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Total Distortion, Including Quantizing Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Discrimination against Out-of-Band Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Discrimination against 12- and 16 kHz Metering Signals . . . . . . . . . . . . . . . . . . . . . . . . . 18
Spurious Out-of-Band Signals at the Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Overload Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Switching Characteristics (PCM/MPI Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Auxiliary Output Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Input and Output Waveforms for AC Tests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Master Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Microprocessor Interface (Input Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Microprocessor Interface (Output Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PCM Highway Timing for XE = 0 (Transmit on Negative PCLK Edge) . . . . . . . . . . . . . . . 23
PCM Highway Timing for XE = 1 (Transmit on Positive PCLK Edge) . . . . . . . . . . . . . . . . 24
Operating the QSLAC Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Channel Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SLIC Control and Data Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Clock Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
E1 Multiplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Debounce Filters Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Real-Time Data Register Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Active State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Inactive State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Low Power State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Chopper Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Overview of Digital Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Two-Wire Impedance Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Frequency Response Correction and Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Transhybrid Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Gain Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2
Am79Q02/021/031 Data Sheet
Transmit Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Impedance Scaling Network (AISN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Speech Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signaling on the PCM Highway . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Robbed-Bit Signaling Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Default Filter Coefficients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command Description and Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microprocessor Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Summary of MPI Commands* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPI Command Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programmable Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Description of CSD Coefficients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
User Test States and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A-Law and µ-Law Companding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
33
34
34
34
35
35
35
36
36
36
38
39
56
56
57
58
60
61
64
LIST OF FIGURES
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Attenuation Distortion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Group Delay Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A-Law/µ-Law Gain Tracking with Tone Input (Both Paths) . . . . . . . . . . . . . . . .
A-Law/µ-Law Total Distortion with Tone Input (Both Paths) . . . . . . . . . . . . . . .
Discrimination Against Out-of-Band Signals . . . . . . . . . . . . . . . . . . . . . . . . . . .
Spurious Out-of-Band Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A/A Overload Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Mode Option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SLIC I/O, E1 Multiplex, and Real-Time Data Register Operation . . . . . . . . . . .
E1 Multiplex Internal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPI Real-Time Data Register or GCI Upstream SC Channel Data . . . . . . . . . .
QSLAC Device Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Robbed-Bit Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
14
15
16
17
18
19
26
28
29
30
32
36
LIST OF TABLES
Table 1
Table 2
Table 3
dBm0 Voltage Definitions with Unity Gain in X, R, GX, GR, AX, and AR . . . . . 13
A-Law: Positive Input Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
µ-Law: Positive Input Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
SLAC Products
3
BLOCK DIAGRAM
Quad SLAC Device
Dual/Single
PCM
Highway
Analog
VIN1
VOUT1
VIN2
VOUT2
VIN3
VOUT3
VIN4
VOUT4
DXA
Signal Processing
Channel 1 (CH 1)
DRA
Signal Processing
Channel 2 (CH 2)
Time Slot Assigner
(TSA)
TSCA
DXB
DRB
Signal Processing
Channel 3 (CH 3)
TSCB
Signal Processing
Channel 4 (CH 4)
VREF
SLIC
Clock
&
Reference
Circuits
CD11
CD21
C31
C41
C51
FS
PCLK
MCLK/E1
CD12
CD22
C32
C42
C52
CD13
CD23
C33
C43
C53
CD14
CD24
C34
C44
C54
CHCLK
SLIC
Interface
(SLI)
Microprocessor Interface
(MPI)
INT
CS
RST
DIO DCLK
Microprocessor
19256A-001
4
Am79Q02/021/031 Data Sheet
ORDERING INFORMATION
Standard Products
Legerity standard products are available in several packages and operating ranges. The order number (Valid
Combination) is formed by a combination of the elements below.
Am79Q02/021/031
J
C
TEMPERATURE RANGE
* C = Commercial (0°C to 70°C;
Relative Humidity = 15% to 95%)
PACKAGE TYPE
J = 44-Pin Plastic Leaded Chip Carrier (PL 044)
—Am79Q02/021 Only
32-Pin Plastic Leaded Chip Carrier (PL 032)
—Am79Q031
V = 44-Pin Thin Quad Flat Pack (PQT 044)
—Am79Q021 Only
DEVICE NUMBER/DESCRIPTION
Am79Q02/021/031
Quad Subscriber Line Audio-Processing Circuit (QSLAC) Device
Valid Combinations
Am79Q02
JC
Am79Q021
JC
Am79Q031
JC
Am79Q021
VC
Valid Combinations
Valid Combinations list configurations planned to
be supported in volume for this device. Consult
the local Legerity sales office to confirm availability of specific valid combinations, to check on newly released combinations, and to obtain additional
data on Legerity’s standard military–grade products.
Note:
* Functionality of the device from 0°C to +70°C is guaranteed by production testing. Performance from –40°C to +85°C
is guaranteed by characterization and periodic sampling of production units.
SLAC Products
5
CHCLK
5 4 3 2 1 44 43 42 41 40
CS
6
C31
C41
CD22
C32
C42
CD21
CD12
CD11
44-Pin PLCC
MCLK/E1
CONNECTION DIAGRAMS (PLCC PACKAGES)
Top View
VOUT1
7
39
DCLK
VIN1
VOUT2
8
38
DIO
9
37
TSCA
VIN2
VCCA
VREF
10
36
TSCB
35
DGND
34
PCLK
AGND
13
33
VIN3
VOUT3
14
32
VCCD
DXA
15
31
VIN4
16
30
DXB
FS
VOUT4
17
29
RST
11
Am79Q02JC
12
DRA
INT
DRB
C34
C44
CD14
CD24
C43
C33
CD23
CD13
18 19 20 21 22 23 24 25 26 27 28
19256A-003
DCLK
DIO
VIN2
10
36
TSCA
VCCA
11
35
DGND
34
PCLK
Am79Q021JC
AGND
VIN3
13
14
33
VCCD
32
DXA
VOUT3
15
31
FS
VIN4
16
17
30
RST
29
INT
VOUT2
MCLK/E1
CS
DCLK
6
28
DIO
VIN2
7
27
TSCA
VCCA
8
26
DGND
VREF
9
C44
C54
DRA
C34
CD24
C53
CD14
Am79Q031JC
25
PCLK
AGND
10
24
VCCD
VIN3
11
23
DXA
VOUT3
12
22
FS
VIN4
13
21
RST
18 19 20 21 22 23 24 25 26 27 28
CD23
C33
C43
CD21
29
19256A-005
14 15 16 17 18 19 20
Notes:
1. Pin 1 is marked for orientation.
2. RSVD = Reserved pin; should not be connected externally to any signal or supply.
Am79Q02/021/031 Data Sheet
INT
37
CD13
1 32 31 30
4 3
DRA
9
6
CD11
38
5
CD14
CD24
8
VOUT4
CD22
VIN1
VOUT2
VIN1
CD23
CS
CD13
39
VOUT4
7
12
2
2 1 44 43 42 41 40
VOUT1
VREF
CD12
VOUT1
MCLK/E1
C51
32-Pin PLCC
CD21
C31
C41
CD11
5 4 3
C52
CD22
C32
6
C42
CD12
44-Pin PLCC
19256A-004
CONNECTION DIAGRAM (TQFP PACKAGE)
Top View
MCLK/E1
C51
CD21
C31
C41
CD11
C52
CD22
C32
C42
CD12
44-Pin TQFP
44 43 42 41 40 39 38 37 36 35 34
VOUT1
1
33
CS
VIN1
VOUT2
2
32
3
31
DCLK
DIO
VIN2
4
30
TSCA
VCCA
5
29
DGND
VREF
6
28
PCLK
AGND
VIN3
7
8
27
VCCD
26
DXA
VOUT3
9
25
FS
10
11
24
RST
23
INT
VIN4
VOUT4
Am79Q021VC
C44
C54
DRA
C34
CD24
CD14
C53
CD23
C33
C43
CD13
12 13 14 15 16 17 18 19 20 21 22
19256A-023
Notes:
1. Pin 1 is marked for orientation.
2. RSVD = Reserved pin; should not be connected externally to any signal or supply.
SLAC Products
7
PIN DESCRIPTIONS
Pin Names
Type
Description
CD11–CD14,
CD21–CD24
Inputs/Outputs
Control and Data. CD1 and CD2 are TTL compatible programmable Input or Output (I/O)
ports. They can be used to monitor or control the state of SLIC or any other device associated with subscriber line interface. The direction, input or output, is programmed using MPI
Command 22. As outputs, CD1 and CD2 can be used to control relays, illuminate LEDs, or
perform any other function requiring a latched TTL compatible signal for control. The output
state of CD1 and CD2 is written using MPI Command 20. As inputs, CD1 and CD2 can be
processed by the QSLAC device (if programmed to do so). CD1 can be debounced before
it is made available to the system. The debounce time is programmable from 0 to 15 ms in
1 ms increments using MPI Command 45. CD2 can be filtered using the up/down counter
facility and programming the sampling interval using MPI Command 52.
Additionally, CD1 can be demultiplexed into two separate inputs using the E1 demultiplexing
function. The E1 demultiplexing function of the QSLAC device was designed to interface directly to Legerity SLICS supporting the ground key function. With the proper Legerity SLIC and
the E1 function of the QSLAC enabled, the CD1 bit can be demultiplexed into an Off-Hook/
Ring Trip signal and Ground Key signal. In the demultiplex mode, the second bit, Ground Key,
takes the place of the CD2 as an input. The demultiplexed bits can be debounced (CD1) or
filtered (CD2) as explained previously. A more complete description of CD1, CD2, debouncing, and filtering functions is contained in the Operating the QSLAC Device section on
page 25.
Once the CD1 and CD2 inputs are processed (Debounced, Filtered and/or Demultiplexed)
by the QSLAC device, the information can be accessed by the system in two ways: 1) on a
per channel basis along with C3, C4, and C5 of the specific channel using MPI Command
21, or 2) by using MPI Commands 16 and 17, which obtain the CD1 and CD2 bits from all
four channels simultaneously. This feature reduces the processor overhead and the time required to retrieve time-critical signals from the line circuits, such as off-hook and ring trip.
With this feature, hookswitch status and ring trip information, for example, can be obtained
from all four channels of a QSLAC device with one read command.
C31–C34,
C41–C44,
C51–C54
Inputs/Outputs
Control. C3, C4, and C5 are TTL-compatible programmable Input or Output (I/O) ports. They
can be used to monitor or control the state of SLIC or any other device associated with subscriber line interface. The direction, input or output, is programmed using MPI Command 22.
As outputs, C3, C4, and C5 can be used to control relays, illuminate LEDs, or perform any
other function requiring a latched TTL compatible signal for control. The output state of C3,
C4, and C5 is written using MPI Command 20. As inputs, C3, C4, and C5 can be accessed
by the system by using MPI Command 21.
The Am79Q021 QSLAC device contains a single PCM highway and five programmable I/Os
per channel (CD1, CD2, C3, C4, and C5) in a 44-pin PLCC or TQFP package. In the
Am79Q02 QSLAC device, the C51, C52, C53, and C54 I/Os are eliminated, enabling dual
PCM highways and a chopper clock output in a 44-pin PLCC or TQFP package. In the
Am79Q031 QSLAC device, the C31–C51, C32–C52, C33–C53, and C34–C54 I/Os are eliminated, enabling a single PCM highway and two control and data I/Os (CD1, CD2) per channel in a 32-pin PLCC package.
8
CHCLK
Output
Chopper Clock. This output provides a 256 kHz or a 292.57 kHz, 50% duty cycle, TTL-compatible clock for use by up to four SLICs with built-in switching regulators. The CHCLK frequency is synchronous to MCLK, but the phase relationship to MCLK is random. The chopper
clock is not available in all package types.
CS
Input
Chip Select. The Chip Select input (active Low) enables the device so that control data can
be written to or read from the part. The channels selected for the write or read operation are
enabled by writing 1 s to the appropriate bits in the Channel Enable Register of the QSLAC
device prior to the command. See EC1, EC2, EC3, and EC4 of the Command 14, page 42,
for more information. If Chip Select is held Low for 16 rising edges of DCLK, a hardware reset is executed when Chip Select returns High.
Am79Q02/021/031 Data Sheet
Pin Names
Type
Description
DCLK
Input
Data Clock. The Data Clock input shifts data into and out of the microprocessor interface of
the QSLAC device. The maximum clock rate is 4.096 MHz.
DIO
Input/Output
Data. Control data is serially written into and read out of the QSLAC device via the DIO pin,
with the most significant bit first. The Data Clock determines the data rate. DIO is high impedance except when data is being transmitted from the QSLAC device.
DRA/DRB
Inputs
PCM Data Receive A/B. The PCM data for channels 1, 2, 3, and 4 is serially received on either
the DRA or DRB port during user-programmed time slots. Data is always received with the
most significant bit first. For compressed signals, 1 byte of data for each channel is received
every 125 µs at the PCLK rate. In the Linear state, two consecutive bytes of data for each
channel are received every 125 µs at the PCLK rate. DRB is not available on all package types.
DXA/DXB
Outputs
PCM Data Transmit. The transmit data from channels 1, 2, 3, and 4 is sent serially out on
either the DXA or DXB port or both ports during user-programmed time slots. Data is always
transmitted with the most significant bit first. The output is available every 125 µs and the
data is shifted out in 8-bit (16-bit in Linear or PCM Signaling state) bursts at the PCLK rate.
DXA and DXB are High impedance between time slots, while the device is in the Inactive
state with no PCM signaling, or while the Cutoff Transmit Path bit (CTP) is on. DXB is not
available on all package types.
FS
Input
Frame Sync. The Frame Sync pulse is an 8 kHz signal that identifies Time Slot 0, Clock Slot
0 of a system’s PCM frame. The QSLAC device references individual time slots with respect
to this input, which must be synchronized to PCLK.
INT
Output
Interrupt. INT is an active Low output signal which is programmable as either TTL compatible or open drain. The INT output goes Low any time one of the input bits in the Real Time
Data register changes state and is not masked. It also goes Low any time new transmit data
appears if this interrupt is armed. INT remains Low until the appropriate register is read via
the microprocessor interface, or the QSLAC device receives either a software or hardware
reset. The individual CDxy bits in the Real Time Data register can be masked from causing
an interrupt by using Command 26 of the MPI. The transmit data interrupt must be armed
with a bit in the Operating Conditions register.
MCLK/E1
Input/Output
Master Clock (Input)/Enable CD1 Multiplex (Output). The Master Clock can be a 1.536 MHz,
1.544 MHz, or 2.048 MHz (times 1, 2, or 4) clock for use by the digital signal processor. If the
internal clock is derived from the PCM Clock Input (PCLK), this pin can be used as an E1 output to control Legerity SLICs having multiplexed hookswitch and ground-key detector outputs.
PCLK
Input
PCM Clock. The PCM clock determines the rate at which PCM data is serially shifted into or
out of the PCM ports. PCLK is an integer multiple of the frame sync frequency. The maximum clock frequency is 8.192 MHz and the minimum clock frequency is 128 kHz for dual
PCM highway versions and 256 kHz for single PCM highway versions. The minimum clock
rate must be doubled if Linear state or PCM signaling is used. PCLK frequencies between
1.03 MHz and 1.53 MHz are not allowed. Optionally, the digital signal processor clock can
be derived from PCLK rather than MCLK.
RST
Input
Reset. A logic Low signal at this pin resets the QSLAC device to its default state. The RST
pin may be tied to VCCD if it is not needed in the system.
TSCA,
TSCB
Outputs
Time Slot Control. The Time Slot Control outputs are open drain outputs (requiring pull-up
resistors to VCCD) and are normally inactive (High impedance). TSCA or TSCB is active
(Low) when PCM data is transmitted on the DXA or DXB pin respectively.
VIN1–VIN4
Inputs
Analog. The analog voice band signal is applied to the VIN input of the QSLAC device. The
VIN input is biased at VREF by a large internal resistor. The audio signal is sampled, digitally
processed and encoded, and then made available at the TTL-compatible PCM output (DXA
or DXB). If the digitizer saturates in the positive or negative direction, VIN is pulled by a reduced resistance toward AGND or VCCD, respectively. VIN1 is the input for channel 1, VIN2
is the input for channel 2, VIN3 is the input for channel 3, and VIN4 is the input for channel 4.
SLAC Products
9
Pin Names
Type
Description
VOUT1–
VOUT4
Outputs
Analog. The received digital data at DRA or DRB is processed and converted to an analog
signal at the VOUT pin. VOUT1 is the output from channel 1, VOUT2 is the output for channel
2, VOUT3 is the output from channel 3, and VOUT4 is the output for channel 4. The VOUT
voltages are referenced to VREF.
VREF
Output
Analog Voltage Reference. The VREF output is provided in order for an external 0.1 µF capacitor to be connected from VREF to ground, filtering noise present on the internal voltage
reference. VREF is buffered before it is used by internal circuitry. The voltage on VREF is
nominally 2.1 V, and the output resistance is 100 kΩ ±30%. The leakage current in the capacitor must be less than 20 nA.
Power Supply
AGND
Analog ground
DGND
Digital ground
VCCA
+5.0 V analog power supply
VCCD
+5.0 V digital power supply
bits are High, all channels enabled will receive the
programming infor mation wr itten; therefore, a
Broadcast state can be implemented by simply
enabling all channels in the device to receive the
information. The Channel Enable bits are contained in
the Channel Enable register, which is written and read
using Commands 14 and 15. The Broadcast state is
useful in initializing QSLAC devices in a large system.
Two separate power supply inputs are provided to
allow for noise isolation and proper power supply
decoupling techniques; however, the two pins have a
low impedance connection inside the part. For best
performance, all of the +5.0 power supply pins should
be connected together at the connector of the printed
circuit board, and all of the grounds should be
connected together at the connector of the printed
circuit board.
The user-programmable filters set the receive and
transmit gain, perform the transhybrid balancing
function, permit adjustment of the two-wire termination
impedance, and provide equalization of the receive and
transmit paths. All programmable digital filter
coefficients can be calculated using the AmSLAC4 or
WinSLAC™ software.
Data transmitted or received on the PCM highway can
be 8-bit companded code (with an optional 8-bit
signaling byte in the transmit direction) or 16-bit linear
code. The 8-bit codes appear 1 byte per time slot,
while the 16-bit code appears in two consecutive time
slots. The compressed PCM codes can be either 8-bit
companded A-law or µ-law. The PCM data is read from
and written to the PCM highway in user-programmable
time slots at rates of 128 kHz to 8.192 MHz. The
transmit clock edge and clock slot can be selected for
compatibility with other devices that can be connected
to the PCM highway.
FUNCTIONAL DESCRIPTION
The QSLAC device performs the codec/filter and twoto four-wire conversion functions required of the
s u b s c r i b e r l i n e i n t e r fa c e c i r c u i t r y
in
telecommunications equipment. These functions
involve converting audio signals into digital PCM
samples and converting digital PCM samples back into
audio signals. During conversion, digital filters are
used to band limit the voice signals. All of the digital
filtering is performed in digital signal processors
operating from a master clock, which can be derived
either from PCLK or MCLK.
Three configurations of the QSLAC device are
offered with single or dual PCM highways. The
Am79Q02 and Am79Q021 QSLAC devices with dual
and single PCM highways respectively are available
in the 44-pin packages. The Am79Q031JC QSLAC
device is a single PCM highway version in a 32-pin
PLCC package.
Four independent channels allow the QSLAC device to
function as four SLAC devices or two DSLAC ä
devices. For programming information, each channel
has its own enable bit (EC1, EC2, EC3, and EC4) to
allow individual channel programming. If more than
one Channel Enable bit is High or if all Channel Enable
10
PCM Highway
Programmable I/O
Chopper Clock
Dual
Four
Yes
44 PLCC/TQFP
Package
Am79Q02 JC
Single
Five
No
44 PLCC/TQFP
Am79Q021 JC (or VC)
Single
Two
No
32 PLCC
Am79Q031 JC
Am79Q02/021/031 Data Sheet
Part Number
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . –60°C < TA < +125°C
VCCA, Analog Supply . . . . . . . . . . . . . +5.0 V ±0.25 V
Ambient Operating Temperature –40°C < TA < +85°C
VCCA, Analog Supply . . . . . . . . . . . . . . VCCD ±10 mV
Ambient Relative Humidity . . . . . . . . . . . . 5% to 95%
VCCD, Digital Supply . . . . . . . . . . . . . +5.0 V ±0.25 V
(non-condensing)
DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V
VCCA with respect to AGND . . . . . . . .–0.4 V to +7.0 V
AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mV
VCCA with respect to VCCD . . . . . . . . . . . . . . ±50 mV
Ambient Temperature . . . . . . . . . . . 0°C < TA < +70°C
VCCD with respect to DGND. . . . . . . .–0.4 V to +7.0 V
Ambient Relative Humidity . . . . . . . . . . . 15% to 95%
VIN with respect to AGND . . .–0.4 V to (VCCA +0.4 V)
Operating Ranges define those limits between which
functionality of the device is guaranteed by production testing.
AGND with respect to DGND . . . . . . . . . . . . . . ±0.4 V
Other pins
with respect to DGND . . . . . –0.4 V to VCCD +0.4 V
Total combined CD1–C5 current per device:
Functionality of the device from 0°C to +70°C is guaranteed
by production testing. Performance from –40°C to +85°C is
guaranteed by characterization and periodic sampling of
production units.
Source from VCCD . . . . . . . . . . . . . . . . . . . . . 40 mA
Sink into DGND . . . . . . . . . . . . . . . . . . . . . . . . 40 mA
Latch-up immunity (any pin). . . . . . . . . . . . . ±100 mA
Stresses above those listed under Absolute Maximum
Ratings may cause permanent device failure. Functionality
at or above these limits is not implied. Exposure to
Absolute Maximum Ratings for extended periods may
affect device reliability.
SLAC Products
11
ELECTRICAL CHARACTERISTICS
Typical values are for TA = 25 °C and nominal supply voltages. Minimum and maximum values are over the
temperature and supply voltage ranges shown in Operating Ranges.
Symbol
VIL
VIH
IIL
VOL
VOH
IOL
VIR
VIOS
ZIN
IIP
IIN
ZOUT
IOUT
ZREF
VOR
VOOS
VOOSA
LINAISN
PD
CI
CO
PSRR
Parameter Descriptions
Input Low voltage
Input High voltage
Input leakage current
Output Low voltage
CD1–C5 (IOL = 4 mA)
CD1–C5 (IOL = 8 mA)
TSCA, TSCB (IOL =14 mA)
Other digital outputs (IOL = 2 mA)
Output High voltage
CD1–C5 (IOH = 4 mA)
CD1–C5 (IOH = 8 mA)
Other digital outputs (IOH = 400 µA)
Output leakage current (HI = Z state)
Analog input voltage range(AX = 0 dB)
(Relative to VREF)(AX = 6.02 dB)
Offset voltage allowed on VIN
Analog input impedance to VREF300 to 3400 Hz
Current into analog input for input voltages between
3.8 V and 5.0 V
Current out of analog input for input voltages between
0 V and 0.5 V
VOUT output impedance
VOUT output current (F< 3400 Hz)
VREF output impedance (F < 3400 Hz)
VOUT voltage range(AR = 0 dB)
(Relative to VREF)(AR = 6.02 dB)
VOUT offset voltage (AISN off)
VOUT offset voltage (AISN on)
Linearity of AISN circuitry (input = 0 dBm0)
Power dissipation
All channels active
1 channel active
All channels inactive, (in normal state)
All channels inactive (in low power state)
Input capacitance (Digital)
Output capacitance (Digital)
Power supply rejection ratio (1.02 kHz, 100 mVRMS, either path, GX = GR = 0 dB)
Min
Typ
2.0
–10
Max
0.8
Unit
+10
µA
0.4
0.8
0.4
0.4
Note
V
1
V
VCCD – 0.4 V
VCCD – 0.8 V
1
2.4
–10
10
±1.584
±0.792
µA
Vpk
–50
0.43
50
3.4
54
170
50
170
mV
MΩ
2
µA
1
–4
70
10
4
130
±1.584
±0.792
–40
–80
–0.25
40
Ω
mApk
kΩ
3
Vpk
40
80
0.25
200
70
18
6
15
15
2
260
130
25
12
mV
4
LSB
mW
5
pF
dB
Notes:
1. The CD1, CD2, C3–C5 outputs are resistive for less than a 0.8 V drop. Total current must not exceed absolute maximum ratings.
2. When the digitizer saturates, a resistor of 50 kΩ ±20 kΩ is connected either to DGND or to VCCD — (1 diode drop) as
appropriate to discharge the coupling capacitor.
3. When the QSLAC device is in the Inactive state, the analog output will present either a VREF DC output level through a 15 kΩ
resistor (VMODE = 0) or a high impedance (VMODE = 1).
4. If there is an external DC path from VOUT to VIN with a gain of GDC and the AISN has a gain of hAISN, then the output offset
will be multiplied by 1/[1–(hAISN • GDC)].
5. Power dissipation in the Inactive state is measured with all digital inputs at VIH = VCC and VIL = DGND and with no load
connected to VOUT1, VOUT2, VOUT3, or VOUT4.
12
Am79Q02/021/031 Data Sheet
Transmission Characteristics
Table 1. 0 dBm0 Voltage Definitions with Unity Gain in X, R, GX, GR, AX, and AR
Signal at Digital Interface
Transmit
Receive
A-law digital mW or equivalent (0 dBm0)
0.7804
0.7804
µ-law digital mW or equivalent (0 dBm0)
0.7746
0.7746
±22,827 peak linear coded sine wave
0.7804
0.7804
Unit
Vrms
When relative levels (dBm0) are used in any of the following transmission specifications, the specification holds for
any setting of the GX gain from 0 dB to 12 dB and the GR loss from 0 dB to 12 dB.
Description
Gain accuracy, D/A or A/D
Test Conditions
0 dBm0, 1014 Hz
AX = AR = 0 dB
0 to 85°C
–40°C
AX = +6.02 dB and/or
AR = –6.02 dB
0 to 85°C
–40°C
Gain accuracy digital-to-digital
Gain accuracy analog-to-analog
Attenuation distortion
Single frequency distortion
Idle channel noise
Analog out
300 Hz to 3 kHz
weighted
unweighted
Digital input = 0
A-law
Digital input = 0
µ-law
Analog VIN = 0 VAC
A-law
Analog VIN = 0 VAC
µ-law
0 dBm0
300 Hz to 3400 Hz
0 dBm0
300 Hz to 3400 Hz
0 dBm0
1014 Hz, Average
1014 Hz, Average
B = Z = 0; X = R = 1
Min
Typ
CrosstalkTX to RX
same channelRX to TX
Crosstalk between channels
TX or RX to TX
TX or RX to RX
End-to-end group delay
Unit
Note
–0.25
–0.30
+0.25
+0.30
–0.30
–0.40
–0.25
–0.25
–0.125
+0.30
+0.40
+0.25
+0.25
+0.125
–46
dB
–68
–55
–78
12
–68
16
–75
–75
dBm0p
dBm0
dBm0p
dBrnc0
dBm0p
dBrnc0
–76
–78
678
dBm0
4
µs
5
Digital looped back
Digital out
Max
0
0
1
2
3
3
3
3, 6
3
3, 6
dBm0
Notes:
1. Also see Figure 1 and Figure 2.
2. 0 dBm0 input signal, 300 Hz to 3400 Hz; measurement at any other frequency, 300 Hz to 3400 Hz.
3. No single frequency component in the range above 3800 Hz may exceed a level of –55 dBm0.
4. The weighted average of the crosstalk is defined by the following equation, where C(f) is the crosstalk in dB as a function of
frequency, fN = 3300 Hz, f1 = 300 Hz, and the frequency points (fj , j = 2..N) are closely spaced:
1----• C ( fj – 1 )
20
æ fj ö
+ 10
10
-÷
--------------------------------------------------------- • log ç -------è f j – 1ø
2
j
--------------------------------------------------------------------------------------------------æf ö
log ç ----N-÷
è f1 ø
å
Average = 20 • log
1----• C ( fj )
20
5. The End-to-End Group Delay is the sum of the transmit and receive group delays (both measured using the same time and
clock slot).
6. Typical values not tested in production.
SLAC Products
13
Attenuation Distortion
QSLAC Device Specification
2
Transmit curve 1.8 dB
Attenuation (dB)
Receive curve 1 dB
1
0.75 dB
0.125
0
Transmit only
– 0.125
200
Frequency (Hz)
300
3000
3400
19256A-006
Figure 1. Attenuation Distortion
Group Delay Distortion
For either transmission path, the group delay distortion is within the limits shown in Figure 2. The minimum value
of the group delay is taken as the reference. The signal level should be 0 dBm0.
420
QSLAC Device Specification
(Either Path)
Delay (µs)
150
90
0
500 600
1000
2600
Frequency (Hz)
Figure 2. Group Delay Distortion
14
Am79Q02/021/031 Data Sheet
2800
19256A-007
Variation of Gain with Input Level
The gain deviation relative to the gain at –10 dBm0 is within the limits shown in Figure 3 for either transmission path
when the input is a sine wave signal of frequency 1014 Hz.
QSLAC Device Specification
1.5
0.55
0.25
Gain
dB
0
–55
–50
–40
–10
0
+3
Input
Level
dBm0
–0.25
–0.55
–1.5
19256A-008
a. A-law
QSLAC Device
Specification
1.4
0.45
0.25
Gain
dB
0
–55
–50
–37
–10
0
+3
Input
Level
dBm0
–0.25
–0.45
–1.4
19256A-009
b. µ-law
Figure 3. A-law/µ-law Gain Tracking with Tone Input (Both Paths)
SLAC Products
15
Total Distortion, Including Quantizing Distortion
The signal-to-total distortion will exceed the limits shown in Figure 4 for either transmission path when the input is
a sine wave signal of frequency 1014 Hz.
QSLAC Device
Specification
35.5 Signal-to-Total
Distortion (dB)
35.5
30
25
–45 –40 –30
0
+3
Input Level (dBm0)
19256A-010
a. A-law
QSLAC Device
Specification
35.5 Signal-to-Total
Distortion (dB)
35.5
31
27
–45 –40 –30
0
+3
Input Level (dBm0)
19256A-011
b. µ-law
Figure 4. A-law/µ-law Total Distortion with Tone Input (Both Paths)
16
Am79Q02/021/031 Data Sheet
Discrimination against Out-of-Band Input Signals
When an out-of-band sine wave signal with frequency and level A is applied to the analog input, there may be
frequency components below 4 kHz at the digital output which are caused by the out-of-band signal. These
components are at least the specified dB level below the level of a signal at the same output originating from a
1014 Hz sine wave signal with a level of A dBm0 also applied to the analog input. The minimum specifications are
shown in the following table.
Frequency of Out-of-Band Signal
Amplitude of Out-of-Band Signal
Level below A
16.6 Hz < f < 45 Hz
–25 dBm0 < A ≤ 0 dBm0
18 dB
45 Hz < f < 65 Hz
–25 dBm0 < A ≤ 0 dBm0
25 dB
65 Hz < f < 100 Hz
–25 dBm0 < A ≤ 0 dBm0
10 dB
3400 Hz < f < 4600 Hz
–25 dBm0 < A ≤ 0 dBm0
see Figure 5
4600 Hz < f < 100 kHz
–25 dBm0 < A ≤ 0 dBm0
32 dB
0
QSLAC Device Specification
–10
–20
Level (dB)
–28 dBm
–30
–32 dB, –25 dBm0 < input < 0 dBm0
–40
–50
3.4
4.0
4.6
19256A-012
Frequency (kHz)
Note:
The attenuation of the waveform below amplitude A between
3400 Hz and 4600 Hz is given by the formula:
π ( 4000 – f )
Attenuation (db) = 14 – 14 sin -------------------------1200
Figure 5. Discrimination Against Out-of-Band Signals
SLAC Products
17
Discrimination against 12- and 16-kHz Metering Signals
If the QSLAC device is used in a metering application where 12-kHz or 16-kHz tone bursts are injected onto the
telephone line toward the subscriber, a portion of those tones may also appear at the VIN terminal. These
out-of-band signals may cause frequency components to appear below 4 kHz at the digital output. For a 12 kHz or
16 kHz tone, the frequency components below 4 kHz will be reduced from the input by at least 70 dB. The sum of
the peak metering and signal voltages must be within the analog input voltage range.
Spurious Out-of-Band Signals at the Analog Output
With PCM code words representing a sine wave signal in the range of 300 Hz to 3400 Hz at a level of 0 dBm0 applied
to the digital input, the level of the spurious out-of-band signals at the analog output is less than the limits shown below.
Frequency
Level
4.6 kHz to 40 kHz
–32 dBm0
40 kHz to 240 kHz
–46 dBm0
240 kHz to 1 MHz
–36 dBm0
With code words representing any sine wave signal in the range 3.4 kHz to 4.0 kHz at a level of 0 dBm0 applied to
the digital input, the level of the signals at the analog output are below the limits in Figure 6. The amplitude of the
spurious out-of-band signals between 3400 Hz and 4600 Hz is given by the formula:
π ( f – 4000 )
A = – 14 – 14 sin ---------------------------- dBm0
1200
0
QSLAC Device Specification
–10
–20
Level (dBm0)
–28 dB
–30
–32 dB
–40
–50
3.4
4.0
4.6
Frequency (kHz)
19256A-013
Figure 6. Spurious Out-of-Band Signals
18
Am79Q02/021/031 Data Sheet
Overload Compression
Figure 7 shows the acceptable region of operation for input signal levels above the reference input power (0 dBm0).
The conditions for this figure are: (1) 1.2 dB < GX ≤ 12 dB; (2) –12 dB ≤ GR < –1.2 dB; (3) PCM output connected
to PCM input; and (4) measurement analog-to-analog.
9
8
7
6
Fundamental
Output Power
5
(dBm0)
Acceptable
Region
4
3
2.6
2
1
1
2
3
4
5
6
7
8
9
Fundamental Input Power (dBm0)
19256A-014
Figure 7. A/A Overload Compression
SLAC Products
19
SWITCHING CHARACTERISTICS over operating range (unless otherwise noted)
Min and max values are valid for all digital outputs with a 150 pF load, except CD1–C5 with a 30 pF load.
Microprocessor Interface
No.
Symbol
Parameter
Min
Typ
Max
1
tDCY
Data clock period
244
2
tDCH
Data clock High pulse width
97
3
tDCL
Data clock Low pulse width
97
4
tDCR
Rise time of clock
25
5
tDCF
Fall time of clock
25
6
tICSS
Chip select setup time, Input state
70
7
tICSH
Chip select hold time, Input state
0
8
tICSL
Chip select pulse width, Input state
9
tICSO
Chip select off time, Input state
2.5
10
tIDS
Input data setup time
30
11
tIDH
Input data hold time
30
12
tOLH
SLIC output latch valid
13
tOCSS
Chip select setup time, Output state
70
t DCY –10
14
tOCSH
Chip select hold time, Output state
0
t DCH –20
15
tOCSL
Chip select pulse width, Output state
16
tOCSO
Chip select off time, Output state
17
tODD
Output data turn on delay
18
tODH
Output data hold time
19
tODOF
Output data turn off delay
20
tODC
Output data valid
0
21
tRST
Reset pulse width
50
Units
Note
ns
t DCY –10
t DCH –20
8t DCY
µs
1000
1
ns
8t DCY
µs
2.5
50
0
50
1
2
ns
50
µs
PCM Interface
PCLK not to exceed 8.192 MHz.
Pull-up resistors of 360 Ω are attached to TSCA and TSCB.
No.
20
Symbol
Parameter
Min
Typ
Max
22
tPCY
PCM clock period
122
23
tPCH
PCM clock High pulse width
48
24
tPCL
PCM clock Low pulse width
48
25
tPCF
Fall time of clock
26
tPCR
Rise time of clock
27
tFSS
FS setup time
25
28
tFSH
FS hold time
50
30
tTSD
Delay to TSC valid
5
80
31
tTSO
Delay to TSC off
5
80
32
tDXD
PCM data output delay
5
70
33
tDXH
PCM data output hold time
5
70
34
tDXZ
PCM data output delay to High-Z
5
70
35
tDRS
PCM data input setup time
25
36
tDRH
PCM data input hold time
5
Units
3
15
15
Am79Q02/021/031 Data Sheet
t PCY –50
ns
4
4,5
6
Master Clock
No.
Symbol
Parameter
Min
37
AMCY
Master clock accuracy
38
tMCR
Rise time of clock
39
tMCF
Fall time of clock
40
tMCH
MCLK High pulse width
48
41
tMCL
MCLK Low pulse width
48
Typ
–100
Max
Units
+100
ppM
Note
15
15
ns
Auxiliary Output Clocks
No.
Symbol
Parameter
Chopper clock frequency
Min
CHP = 0
CHP = 1
Typ
256
292.57
42
fCHP
43
fE1
E1 output frequency (CMODE = EE1 = 1)
4.923
44
tE1
E1 pulse width (CMODE = EE1 = 1)
31.25
Max
Units
Note
kHz
µs
Notes:
1. If CFAIL = 1 (Command 23), GX, GR, Z, B1, X, R, and B2 coefficients must not be written or read without first deactivating
all channels or switching them to default coefficients; otherwise, a chip select off time of 25 µs is required. If the low power
state (LPM = 1, Command 14) is selected and MCLK is also lost, this minimum chip select off time increases to 75 µs.
2. The first data bit is enabled on the falling edge of CS or on the falling edge of DCLK, whichever occurs last.
3. The PCM clock frequency must be an integer multiple of the frame sync frequency. The maximum allowable PCM clock
frequency is 8.192 MHz. The actual PCM clock rate is dependent on the number of channels allocated within a frame. The
minimum clock frequency is 128 kHz in Companded state and 256 kHz in Linear state, PCM Signaling state. The minimum
PCM clock rates should be doubled for parts with only one PCM highway in order to allow simultaneous access to all four
channels.
4. TSC is delayed from FS by a typical value of N • tPCY , where N is the value stored in the time/clock-slot register.
5. tTSO is defined as the time at which the output achieves the Open Circuit state.
6. There is a special conflict detection circuitry that will prevent high-power dissipation from occurring when the DXA or DXB
pins of two QSLAC devices are tied together and one QSLAC device starts to transmit before the other has gone into a
High-impedance state.
SWITCHING WAVEFORMS
Input and Output Waveforms for AC Tests
2.4
2.0
0.8
0.45
Test
Points
2.0
0.8
19256A-015
Master Clock Timing
37
40
VIH
VIL
41
39
SLAC Products
38
19256A-016
21
Microprocessor Interface (Input Mode)
1
2
5
VIH
VIH
DCLK
VIL
VIL
7
3
9
4
CS
6
8
11
10
Data
Valid
DI/O
Data
Valid
Data
Valid
12
Data
Valid
Outputs
C5–C1
Data
Valid
21108-019
Microprocessor Interface (Output Mode)
VIH
VIL
DCLK
14
13
16
CS
15
20
18
17
DI/O
Three-State VOH
VOL
Data
Valid
19
Data
Valid
Data
Valid
Three-State
21108A-020
22
Am79Q02/021/031 Data Sheet
PCM Highway Timing for XE = 0 (Transmit on Negative PCLK Edge)
Time Slot Zero
Clock Slot Zero
22
26
25
VIH
PCLK
VIL
23
24
27
28
FS
30
31
TSCA/
TSCB
32
33
34
VOH
DXA/DXB
First Bit
VOL
35
DRA/DRB
First
Bit
VIH
Second
Bit
VIL
SLAC Products
36
21108A-021
23
PCM Highway Timing for XE = 1 (Transmit on Positive PCLK Edge)
Time Slot Zero
Clock Slot Zero
22
26
25
VIH
PCLK
VIL
23
24
27
28
FS
30
31
TSCA/
TSCB
32
33
34
VOH
DXA/DXB
First Bit
VOL
35
VIH
DRA/DRB
First
Bit
36
Second
Bit
VIL
21108A-022
24
Am79Q02/021/031 Data Sheet
OPERATING THE QSLAC DEVICE
The following sections describe the operation of the
four independent channels of the QSLAC device. The
des cr i pti on is va li d fo r c hann el 1 , 2, 3, or 4;
consequently, the channel subscripts have been
dropped. For example, VOUT refers to either VOUT1,
VOUT2, VOUT3, or VOUT4.
Power-Up Sequence
T h e r e c o m m e n d e d Q S L AC d ev i c e p ow e r - u p
sequence is to apply:
1. VCC and ground
multiple channel addressing is accomplished without
increasing the number of I/O pins on the device. The
Broadcast state can be further enhanced by providing
the ability to select many chips at once; however, care
must be taken never to enable more than one chip in
the Read state. This can lead to an internal bus
contention, in which excess power is dissipated. (Bus
contention will not damage the device.) Most control
commands defined for the DSLAC device are
compatible with the QSLAC device, thereby minimizing
the impact to existing system software.
2. Signal connections and Low on RST
SLIC Control and Data Lines
3. High on RST
The QSLAC device has up to five SLIC digital interface
pins per channel (CD1–C5). Each of these pins can be
programmed as either an input or an output using the
I/O Direction register (Commands 22 and 23) (see
Figure 9). The output latches can be written with
Command 20; however, only those bits programmed
as outputs will actually drive the pins. The inputs can
be read with Command 21. If a pin is programmed as
an output, the data read from it will be the contents of
the output latch. It is recommended that any of the
SLIC input/output data points, which are to be
programmed as outputs, be written to their desired
state via Command 21 before writing the data which
configures them as outputs with the I/O direction
register Command 22. This ensures that when the
output is activated, it is already in the correct state, and
will prevent unwanted data from being driven from the
SLIC output pins.
The software initialization should then include:
1. Wait 1 ms.
2. Select master clock frequency and source
(Commands 12 and 13). This should turn off the
CFAIL bit (Command 23) within 400 µs. While the
CFAIL bit is on, normal programming can proceed,
but no channels should be activated.
3. Program filter coefficients and other parameters as
required.
4. Activate (Command 5).
If the power supply (VCCD) falls below approximately
1.0 V, the device is reset and will require complete
reprogramming with the above sequence. A reset may
be initiated by connection of a logic Low to the RST
pin, or if chip select (CS) is held low for 16 rising edges
of DCLK, a hardware reset is generated when CS
returns high. The RST pin may be tied to VCCD if it is
not used in the system.
Channel Enable Register
A channel enable register has been implemented in
the QSLAC device in order to reduce the effor t
required to address individual or multiple channels of
the QSLAC device. The register is written using MPI
Command 14. Each bit of the register is assigned to
one unique channel, bit 0 for channel 1, bit 1 for
channel 2, bit 2 for channel 3, and bit 3 for channel 4.
The channel or channels are enabled when their
corresponding enable bits are High. All enabled
channels will receive the data written to the QSLAC
device. This enables a Broadcast state (all channels
enabled) to be implemented simply and efficiently, and
Clock Mode Operation
The QSLAC device operates with multiple clock
signals. The master clock (MCLK) is used for internal
timing including operation of the digital signal
processing and may be derived from either the MCLK
or PCLK source. The allowed frequencies are listed
under Commands 12 and 13.
The PCM clock (PCLK) is used for PCM timing and is
an integer multiple of the frame sync frequency. The
internal device clock (MCLK) can be optionally derived
from the PCLK source by setting the CMODE bit (bit 4,
Commands 12 and 13, 46/47h) to one. In this mode,
the MCLK/E1 pin is free to be used as an E1 signal
output. Clock mode options and E1 output functions
are shown in Figure 8.
SLAC Products
25
.
MCLK/E1
PCLK
(= 0)
Time
Slot
Assigner
(= 1)
E1
(= 1)
(= 0)
CMODE
(= 1)
EE1
÷N
DSP
Engine
(= 0)
CSEL
E1
Pulses
E1P
Notes:
1. CMODE = Command 12, 13
Bit 4
2. CSEL = Command 12, 13
Bits 0–3
3. EE1 = Command 45, 46
Bit 7
4. E1P = Command 45, 46
Bit 6
Figure 8. Clock Mode Option
E1 Multiplex Operation
The QSLAC device can multiplex input data from the
CD1 SLIC I/O pin into two separate status bits per
channel (CD1 and CD1B bits in the SLIC Input/Output
register, Commands 52/53h, and CDA and CDB bits in
the Real Time Data register, Commands 4D/4Fh)
using the E1 multiplex mode. This multiplex mode
provides the means to accommodate dual detect
states when connected to an Legerity SLIC device,
which also supports ground-key detection in addition
to loop detect. Legerity SLICs that support ground-key
detect use their E1 pin as an input to switch the SLIC’s
single detector (DET) output between internal loop
detect or ground-key detect comparators. Using the E1
multiplex mode, a single QSLAC device can monitor
both loop detect and ground-key detect states of all
four connected SLICs without additional hardware.
Although normally used for ground key detect, this
multiplex function can also be used for monitoring
other signal states.
The E1 multiplex mode is selected by setting the EE1
bit (bit 7, Command C8/C9h) and CMODE bit (bit 4,
Command 46/47h) in the QSLAC device. The CMODE
bit must be selected (CMODE=1) for the master clock
to be derived from PCLK so that the MCLK/E1 pin can
be used as an output for the E1 signal. The multiplex
mode is then turned on by setting the EE1 bit. With the
26
E1 multiplex mode enabled, the QSLAC device
generates the E1 output signal. This signal is a
31.25 µ s (1/32 kHz) duration pulse occurring at a
4.923 kHz (64 kHz/13) rate. The polarity of this E1
output is selected by the E1P bit (bit 6, Command C8/
C9h) allowing this multiplex mode to accommodate all
SLICs regardless of their E1 high/low logic definition.
Figure 9 shows the SLIC Input/Output register, I/O
pins, E1 multiplex hardware operation for one QSLAC
device channel. It also shows the operation of the Real
Time Register. The QSLAC device E1 output signal
connects directly to the E1 inputs of all four connected
SLICs and is used by those SLICs to select an internal
comparator to route to the SLIC’s DET output. This E1
signal is also used internally by the QSLAC device for
controlling the multiplex operation and timing.
The CD1 and CD1B bits of the SLIC Input/Output
register are isolated from the CD1 pin by transparent
latches. When the E1 pulse is off, the CD1 pin data is
routed directly to the CD1 bit of the SLIC I/O register
and changes to the CD1B bit of that register are
disabled by its own latch. When E1 pulses on, the CD1
latch holds the last CD1 state in its register. At the
same time, the CD1B latch is enabled, which allows
CD1 pin data to be routed directly to the CD1B bit.
Am79Q02/021/031 Data Sheet
Therefore, during this multiplexing, the CD1 bit always
has loop-detect status and the CD1B bit always has
ground-key detect status.
Thi s multiplexin g state changes a lmost
instantaneously within the QSLAC device but the SLIC
device may require a slightly longer time period to
respond to this detect state change before its DET
output settles and becomes valid. To accommodate
this delay difference, the internal signals within the
QSLAC device are isolated by 15.625 µ s before
allowing any change to the CD1 bit and CD1B bit
latches. This operation is further described by the E1
multiplex timing diagram in Figure 9. In this timing
diagram, the E1 signal represents the actual signal
presented to the E1 output pin. The GK Enable pulse
allows CD1 pin data to be routed through the CD1B
latch. The LD Enable pulse allows CD1 pin data to be
routed through the CD1 latch. The uncertain states of
the SLIC’s DET output, and the masked times where
that DET data is ignored are shown in this timing
diagram. Using this isolation of masked times, the CD1
and CD1B registers are guaranteed to contain
accurate representations of the SLIC detector output.
SLAC Products
27
SLIC I/O Register
MPI Command 20, 21
D
—
Q
— CD1B C5
C4
C3 CD2 CD1
EN/HOLD
*
CD1
CD2
C3
C4
C5
D
I/O Direction
Register
MPI Command 22
Q
EN/HOLD
*
Output Latch
1
Ground Key Filter
(time set via
Commands 52, 53)
GK Enable
Debounce
(time set via
Commands 45, 46)
(Channel 1
Shown)
EE1 Bit
E1 Source
(Internal)
{
Delay
Same for
Channels
2, 3, 4
See Figure 10
for details
Real Time
Data Register
(Command 16, 17)
E1P
INT
MUX
LD Enable
SLIC Output
Data Register
MPI Command 20
MCLK/E1
0
CDB4 CDA4 CDB3 CDA3 CDB2 CDA2 CDB1 CDA1
ATI
(CMD 28, 29, Bit 3)
Interrupt Mask
Register
(Command 26, 27)
MCDB4 MCDA4 MCDB3 MCDA3 MCDB2 MCDA2 MCDB1 MCDA1
Note:
* Transparent latches: When enable input is high, Q output follows D input. When enable input
goes low, Q output is latched at last state.
Figure 9. SLIC I/O, E1 Multiplex and Real-Time Data Register Operation
28
Am79Q02/021/031 Data Sheet
Pulse Period 203.125 µs
4.923 kHz (64 kHz/13) pulse rate
31.25 µs
E1
15.625 µs 15.625 µs
GK Enable
LD Enable
15.625 µs
DET Output
from SLIC
(CD1 Pin Input)
CD1 Pin
Input Data
Contains
Valid LD
Status
CD1
Register
Operation
Tracks
DET State
CD1B
Register
Operation
Contains
Valid GK
Status
CD1 Pin
State
Ignored
CD1 Pin
State
Ignored
Tracks
DET State
Hold Last State
Hold Last State
Tracks
DET State
Contains
Valid LD
Status
Hold Last State
Figure 10. E1 Multiplex Internal Timing
Debounce Filters Operation
Each channel is equipped with two debounce filter
circuits to buffer the logic status of the CD1 and CD2/
CD1B bits of the SLIC I/O Data Register (Commands
20 and 21, 52/53h) before providing filtered bit’s
outputs to the Real-Time Data Register (Commands
16 and 17, 4D/4Fh). One filter is used only for the CD1
bit. The other filter acts upon either the CD1B bit if E1
multiplexing is enabled, or on the CD2 bit if the
multiplexing is not enabled.
The CD1 bit normally contains SLIC loop detect
status. The CD1 debouncing time is programmable
with the Debounce Time Register (Commands 45 and
46, C8/C9h), and even though each channel has its
own filter, the programmed value is common to all four
channels. This debounce filter is initially clocked at the
frame sync rate of 125 µ s, and any occurrence of
changing data at this sample rate resets a
programmable counter. This programmable counter is
clocked at a 1 ms rate, and the programmed count
value of 0 to 15 ms, as defined by the Debounce Time
Register, must be reached before updating the CDA bit
of the Real Time Data register with the CD1 state.
Refer to Figure 11a for this filter’s operation.
The ground-key filter (Figure 11b) provides a buffering
of the signal, normally ground key detect, which
appears in the CDB bit of the Real Time Data Register.
Each channel has its own filter, and each filter’s time
can be individually programmed. The input to the filter
comes from either the CD2 bit of the SLIC I/O Data
Register (Command 20 and 21, 52/53h), when E1
multiplexing is not enabled, or from the CD1B bit of
that register when E1 multiplexing is enabled. The
feature debounces ground-key signals before passing
them to the Real Time Data Register, although signals
other than ground-key status can be routed to the CD2
pin and then through the registers.
The ground-key debounce filter operates as a dutycycle detector and consists of an up/down counter
which can range in value between 0 and 6. This six-state
counter is clocked by the GK timer at the sampling
period of 1–15 ms, as programmed by the value of the
four GK bits (GK3, GK2, GK1, GK0) of the Ground-Key
Filter Data register (Commands 52 and 53, E8/E9h).
This sampling period clocks the counter, which buffers
the CD2/CD1B bit’s status before it is valid for
presenting to the CDB bit of the Real Time Data
Register. When the sampled value of the ground-key (or
CD2) input is high, the counter is incremented by each
clock pulse. When the sampled value is low, the counter
is decremented. Once the counter increments to its
maximum value of 6, it sets a latch whose output is
routed to the corresponding CDB bit. If the counter
decrements to its minimum value of 0, this latch is
cleared and the output bit is set to zero. All other times,
the latch (and the CDB status) remains in its previous
state without change. It therefore takes at least six
consecutive GK clocks with the debounce input
remaining at the same state to effect an output change.
If the GK bit value is set to zero, the buffering is
bypassed and the input status is passed directly to CDB.
SLAC Products
29
Q
D
CD1
Debounce Counter
D
Q
D
Q
D
Q
CK
EN/HOLD
*
DSH0–DSH3
Debounce Period
(0–15 ms)
8
CDA
Q
RST
FS
(8 kHz)
Notes:
* Transparent latch: Output follows input when EN is high; output holds last state when EN is low
Debounce Counter: Output goes high after counting to programmed (DSH) number of 1 ms clocks;
Counter is reset for CD1 input changes at 125 µs sample period.
DSH0–DSH3 programmed value is common for all 4 channels, but debounce counter is separate per channel
a. Loop Detect Debounce Filter
MUX
CD2 or CD1B
GK=0
GK0–GK3
Ground-Key
Sampling Interval
(1–15 ms)
CDB
UP/DN
Q
GK=0
GK
1 kHz
RST
Clock Divider
(1–15 ms
clock output)
Six-State
Up/Down
Counter
Notes:
Programmed value of GK0–GK3 determines clock rate (1–15 ms) of six-state counter.
If GK value = 0, counter is bypassed and no buffering occurs.
Six-state up/down counter: Counts up when input is high; counts down when input is low.
Output goes and stays high when maximum count is reached;
output goes and stays low when counts down to zero.
b. Ground-Key Filter
Figure 11. MPI Real-Time Data Register or GCI Upstream SC Channel Data
30
Am79Q02/021/031 Data Sheet
Real-Time Data Register Operation
Active State
To obtain time-critical data such as off/on-hook and
ring trip information from the SLIC with a minimum of
processor time and effort, the QSLAC device contains
an 8-bit Real Time Data register. This register contains
CDA and CDB bits from all four channels. The CDA bit
for each channel is a debounced version of the CD1
input. The CDA bit is normally used for switchhook.
The CDB bit for each channel normally contains the
CD2 input bit; however, if the E1 multiplex operation is
enabled, the CDB bit will contain the debounced value
of the CD1B bit. CD1 and CD2 can be assigned to offhook, ring trip, ground key signals, or other signals.
Frame sync is needed for the debounce and the
ground key signals. If Frame sync is not provided, the
real-time register will not work. The register is read
using MPI Commands 16 and 17 (4D/4Fh), and may
be read at any time regardless of the state of the
Channel Enable Register. This allows off/on-hook, ring
trip, or ground key information for all four channels to
be obtained from the QSLAC device with one read
operation versus one read per channel. If these data
bits are not used for supervision information, they can
be accessed on an individual channel basis in the
same way as C3–C5; however, CD1 and CD1B will not
be debounced.
Each channel of the QSLAC device can operate in
either the Active (operational) or Inactive (standby)
state. In the Active state, individual channels of the
QSLAC device can transmit and receive PCM or linear
data and analog information. The Active state is
required when a telephone call is in progress. The
activate command (MPI Command 5), puts the
selected channel(s) into this state (see channel enable
register). Bringing a channel of the QSLAC device into
the Active state is only possible through the MPI.
Interrupt
In addition to the Real Time Data register, an interrupt
signal has been implemented in the QSLAC device.
The interrupt signal is an active Low output signal
which pulls Low whenever the unmasked CD bits
change state (Low to High or High to Low); or
whenever the transmit PCM data changes on a
channel in which the Arm Transmit Interrupt (ATI) bit is
on. The interrupt control is shown in Figure 9. The
interrupt remains Low until the appropriate register is
read. This output can be programmed as TTL or open
drain. When an interrupt is generated, all of the
unmasked bits in the Real Time Data register latch and
remain latched until the interrupt is cleared. The
interrupt is cleared by reading the register with
Command 17, by writing to the interrupt mask register
(Command 26), or by a reset. If any of the inputs to the
unmasked bits in the Real Time Data register are
different from the register bits when the interrupt is
cleared, a new interrupt is immediately generated with
the new data latched into the Real Time Data register.
For this reason, the interrupt logic in the controller
should be level-sensitive rather than edge-sensitive.
Inactive State
All channels of the QSLAC device are forced into the
Inactive (standby) state by a power-up or hardware
reset. Individual channels can be programmed into
this state by the deactivate command (Command 1) or
by the software reset command (Command 2). Power
is disconnected from all nonessential circuitry while
the MPI remains active to receive commands. The
analog output is tied to VREF through a resistor whose
value depends on the VMODE bit. All circuits that
contain programmed information retain their data in
the Inactive state.
Low Power State
If the Low Power state is turned on by setting LPM = 1
(Command 14), the internal clock speed substantially
reduces when all four channels are deactivated. When
this happens, the CFAIL bit is set to 1, and if MCLK
also is lost, the microprocessor interface requires a
minimum of 75 ms off time between commands.
Chopper Clock
On the Am79Q02JC there is a chopper clock output to
drive the switching regulator on some Legerity SLICs.
The clock frequency is selectable as 256 or 292.57 kHz
by the CHP bit (Command 12). The chopper output
must be turned on with the ECH bit (Command 45).
Reset States
The QSLAC device can be reset by application of
power, by an active Low on the hardware Reset pin
(RST), by a hardware reset command, or by CS Low
for 16 or more rising edges of DCLK. This resets the
QSLAC device to the following state:
1. A-law companding is selected.
2. Default B, X, R, and Z filter values are selected and
the AISN is set to zero.
3. Default digital gain blocks (GX, GR) are selected.
The analog gains, AX and AR, are set to 0 dB.
Interrupt Mask Register
The Real Time Data register data bits can be masked
from causing an interrupt to the processor using the
interrupt mask register. The mask register can be
written or read via the MPI Commands 26 and 27.
4. SLIC I/Os (CD1–C5) are set to the Input state.
5. All of the test states in the Operating Conditions
register are turned off (0’s).
6. All four channels are in the Inactive (standby) state.
SLAC Products
31
7. Transmit time slots and receive time slots are set to
0, 1, 2, and 3 for channels 1, 2, 3, and 4,
respectively. The clock slots are set to 0, with
transmit on the negative edge.
16. The E1 Multiplex state is turned off and the polarity
is set for high going pulses.
17. No signalling on the PCM highway.
SIGNAL PROCESSING
Overview of Digital Filters
8. DXA port is selected for all channels.
9. DRA port is selected for all channels.
Several of the blocks in the signal processing section
are user programmable. These allow the user to
optimize the performance of the QSLAC device for the
system. Figure 12 shows the QSLAC device signal
processing and indicates the programmable blocks.
10. The master clock frequency selected is 8.192 MHz
and is programmed to come from PCLK.
11. All four channels are selected in the Channel
Enable register.
12. Any pending interrupts are cleared, all interrupts
are masked, and the Interrupt Output state is set to
open drain.
The advantages of digital filters are:
13. The supervision debounce time is set to 8 ms.
14. The previously programmed B, Z, X, R, GX, and
GR filters are unchanged.
15. The chopper clock frequency is set to 256 kHz but
the chopper clock is turned off.
High reliability
No drift with time or temperature
Unit-to-unit repeatability
Superior transmission performance
Flexibility
Maximum possible bandwidth for V.34 modems
High Pass Filter (HPF)
*
VIN
AX
Full
Digital
Loop
back
(FDL)
+
GX
X
*
*
Compressor
LPF
& HPF
TSA
Loopback
(TLB)
AISN
Z
*
*
B
*
Cutoff Receive
Path (CRP)
+
VOUT
Decimator
Decimator
ADC
Cutoff
Transmit
Path
(CTP)
TSA
Digital
TX
*
AR
Interpolator
DAC
+
Interpolator
VREF
*
Expander
LPF
GR
R
*
* Receive
Lower
Gain (RG)
0
TSA
Digital
RX
1 kHz Tone
(TON)
programmable blocks
21108-027
Figure 12. QSLAC Device Block Diagram
32
Am79Q02/021/031 Data Sheet
Two-Wire Impedance Matching
Transmit Signal Processing
Two feedback paths on the QSLAC device synthesize
the two-wire input impedance of the SLIC by providing
a programmable feedback path from VIN to VOUT. The
Analog Impedance Scaling Network (AISN) is a
programmable analog gain of –0.9375 to +0.9375 from
VIN to VOUT . The Z filter is a programmable digital
filter providing an additional path and programming
flexibility over the AISN in modifying the transfer
function from VIN to VOUT. Together, the AISN and the
Z-Filter enable the user to synthesize virtually all
required SLIC input impedances.
In the transmit path (A/D), the analog input signal (VIN)
is A/D converted, filtered, companded (for A-law or
µ-law), and made available to the PCM highway in
A-law, µ-law, or linear form. If linear form is selected, the
16-bit data will be transmitted in two consecutive time
slots starting at the programmed time slot. The signal
processor contains an ALU, RAM, ROM, and control
logic to implement the filter sections. The B, X, and GX
blocks are user-programmable digital filter sections
with coefficients stored in the coefficient RAM, while
AX is an analog amplifier that can be programmed for
0 dB or 6.02 dB gain. The B, X, and GX filters can also
b e op e ra te d f r om an a l t er n a te s e t o f de fa u lt
coefficients stored in ROM (Commands 24 and 25).
Frequency Response Correction and
Equalization
The QSLAC device contains programmable filters in
the receive (R) and transmit (X) directions that may be
programmed for line equalization and to correct any
attenuation distortion caused by the Z filter.
Transhybrid Balancing
The QSLAC device’s programmable B filter is used to
adjust transhybrid balance. The filter has a single pole
IIR section (BIIR) and an eight-tap FIR section (BFIR),
both operating at 16 kHz.
Gain Adjustment
T h e Q S L AC d ev i c e ’s t r a n s m i t p a t h h a s t w o
programmable gain blocks. Gain block AX is an analog
gain of 0 dB or 6.02 dB (unity gain or gain of 2.0),
located immediately before the A/D converter. GX is a
digital gain block that is programmable from 0 dB to
+12 dB, with a worst-case step size of 0.1 dB for gain
settings below +10 dB, and a worst-case step size of
0.3 dB for gain settings above +10 dB. The filters
provide a net gain in the range of 0 dB to 18 dB.
The QSLAC device receive path has two programmable
loss block s. GR is a digital los s bl ock that is
programmable from 0 dB to 12 dB, with a worst-case
step size of 0.1 dB. Loss block AR is an analog loss of
0 dB or 6.02 dB (unity gain or gain of 0.5), located
immediately after the D/A converter. This provides a net
loss in the range of 0 dB to 18 dB.
An additional 6 dB attenuation is provided as part of
GR, which can be inserted by setting the RG bit of
Command 70/71h. This allows writing of a single bit to
introduce 6 dB of attenuation into the receive path without
having to reprogram GR. This 6 dB loss is implemented
as part of GR and the total receive path attenuation must
remain in the specified 0 to –12 dB range. If the RG bit is
set, the programmed value of GR must not introduce
more than an additional 6 dB attenuation.
The decimator reduces the high input sampling rate to
16 kHz for input to the B, GX, and X filters. The X filter
is a six-tap FIR section which is part of the frequency
response correction network. The B filter operates on
samples from the receive signal path in order to
provide transhybrid balancing in the loop. The highpass filter rejects low frequencies such as 50 Hz or
60 Hz, and may be disabled.
Transmit PCM Interface
The transmit PCM interface transmits a 16-bit linear
code (when programmed) or an 8-bit compressed code
from the digital A-law/µ-law compressor. Transmit logic
controls the transmission of data onto the PCM
highway through output port selection and time/clock
slot control circuitry. The linear data requires two
consecutive time slots, while a single time slot is
required for A-law/µ-law data.
In the PCM Signaling state (SMODE = 1), the transmit
time slot following the A-law or µ-law data is used for
signaling information. The two time slots form a single
16-bit data block.
The frame sync (FS) pulse identifies time slot 0 of the
transmit frame and all channels (time slots) are
referenced to it. The logic contains userprogrammable Transmit Time Slot and Transmit Clock
Slot registers.
The Time Slot register is 7 bits wide and allows up to
128 8-bit channels (using a PCLK of 8.192 MHz) in
each frame. This feature allows any clock frequency
between 128 kHz and 8.192 MHz (2 to 128 channels)
in a system. The data is transmitted in bytes, with the
most significant bit first.
The Clock Slot register is 3 bits wide and may be
programmed to offset the time slot assignment by 0 to
7 PCLK periods to eliminate any clock skew in the
system. An exception occurs when division of the
PCLK frequency by 64 kHz produces a nonzero
remainder, R, and when the transmit clock slot is
greater than R. In that case, the R-bit fractional time
SLAC Products
33
slot after the last full time slot in the frame will contain
random information and will have the TSC output
turned on. For example, if the PCLK frequency is
1.544 MHz (R = 1) and the transmit clock slot is greater
than 1, the 1-bit fractional time slot after the last full
time slot in the frame will contain random information,
and the TSC output will remain active during the
fractional time slot. In such cases, problems can be
avoided by not using the last time slot.
The frame sync (FS) pulse identifies time slot 0 of the
receive frame, and all channels (time slots) are
referenced to it. The lo gic co nta ins userprogrammable Receive Time Slot and Receive Clock
Slot registers. The Time Slot register is 7 bits wide and
allows up to 128 8-bit channels (using a PCLK of
8.192 MHz) in each frame. This feature allows
a n y c l o c k f r e q u e n c y b e t w e e n 128 kHz and
8.192 MHz (2 to 128 channels) in a system.
The PCM data may be user programmed for output
onto either the DXA or DXB por t or both por ts
simultaneously. Correspondingly, either TSCA or
TSCB or both are Low during transmission.
The Clock Slot register is 3 bits wide and can be
programmed to offset the time slot assignment by 0 to
7 PCLK periods to eliminate any clock skews in the
system. An exception occurs when division of the
PCLK frequency by 64 kHz produces a nonzero
remainder (R), and when the receive clock slot is
greater than R. In that case, the last full receive time
slot in the frame is not usable. If the PCLK frequency
is 1.544 MHz (R=1/8, or 1 clock slot within a time slot),
the receive clock slot can be only 0 or 1 if the last time
slot is to be used. The PCM data can be programmed
for input from the DRA or DRB port.
The DXA/DXB and TSCA/TSCB outputs can be
programmed to change either on the negative or
positive edge of PCLK.
Tr a n s m i t d a t a c a n a l s o b e r e a d t h r o u g h t h e
microprocessor interface using Command 47.
Receive Signal Processing
In the receive path (D/A), the digital signal is expanded
(for A-law or µ-law), filtered, converted to analog, and
passed to the VOUT pin. The signal processor
contains an ALU, RAM, ROM, and Control logic to
implement the filter sections. The Z, R, and GR blocks
are user-programmable filter sections with their
coefficients stored in the coefficient RAM, while AR is an
analog amplifier which can be programmed for a 0 dB or
6.02 dB loss. The Z, R, and GR filters can also be
operated from an alternate set of default coefficients
stored in ROM (Commands 24 and 25).
The low-pass filter band limits the signal. The R filter is
composed of a six-tap FIR section operating at a 16 kHz
sampling rate and a one-tap IIR section operating at
8 kHz. It is part of the frequency response correction
network. The Analog Impedance Scaling Network
(AISN) is a user-programmable gain block providing
feedback from VIN to VOUT to emulate different SLIC
input impedances from a single exter nal SLIC
impedance. The Z filter provides feedback from the
transmit signal path to the receive path and is used to
modify the effective input impedance to the system.
The interpolator increases the sampling rate prior to
D/A conversion.
Analog Impedance Scaling Network (AISN)
The AISN is in the QSLAC device to scale the value of
the external SLIC impedance. Scaling this external
impedance with the AISN (along with the Z filter) allows
matching of many different line conditions using a
single impedance value. Linecards can meet many
different specifications without any hardware changes.
The AISN is a programmable transfer function connected
from VIN to VOUT for each QSLAC device channel. The
AISN transfer function alters the input impedance of the
SLIC device to a new value (ZIN):
Z IN = ZSL • ( 1 – G44 • h AISN ) ⁄ ( 1 – G 440 • h AISN )
where G440 is the SLIC echo gain into an open circuit,
G44 is the SLIC echo gain into a short circuit, and ZSL
is the SLIC input impedance without the QSLAC device.
The gain can be varied from –0.9375 to +0.9375 in 31
steps of 0.0625. The AISN gain is determined by the
following equation:
4
h AISN
æ
ö
i
= 0.0625 ç
AISN i • 2 ÷ – 16
ç
÷
èi = 0
ø
å
Receive PCM Interface
where AISNi = 0 or 1
The receive PCM interface logic controls the reception
of data bytes from the PCM highway, transfers the data
to the A-law/µ-law expansion logic for compressed
signals, and then passes the data to the receive path of
the signal processor. If the data received from the PCM
highway is programmed for linear code, the A-law/µ-law
expansion logic is bypassed and the data is presented
to the receive path of the signal processor directly. The
linear data requires two consecutive time slots, while
the A-law or µ-law data requires a single time slot.
There are two special cases to the formula for hAISN:
1) a value of AISN = 00000 will specify a gain of 0 (or
cutoff), and 2) a value of AISN = 10000 is a special
case where the AISN circuitry is disabled and VOUT is
connected internally to VIN with a gain of 0 dB. This
allows a Full Digital Loopback state where an input
digital PCM signal is completely processed through
the receive section, looped back, processed through
the transmit section, and output as digital PCM data.
34
Am79Q02/021/031 Data Sheet
During this test, the VIN input is ignored and the VOUT
output is connected to VREF.
Speech Coding
The A/D and D/A conversion follows either the A-law
or the µ-l aw stand ard as defin ed i n ITU-T
Recommendation G.711. A-law or µ-law operation is
programmed using MPI Commands 24 and 25.
Alternate bit inversion is performed as part of the A-law
coding. The QSLAC device provides linear code as an
option on both the transmit and receive sides of the
device. Linear code is selected using MPI Commands
24 and 25. Two successive time slots are required for
linear code operation. The linear code is a 16-bit two’scomplement number which appears sign bit first on the
PCM highway. Linear code occupies two time slots.
Signaling on the PCM Highway
If the SMODE bit is set in the Configuration register,
each data point occupies two consecutive time slots.
The first time slot contains A-law or µ-law data and the
second time slot will have the following information:
Bit 7:
Debounced CD1 bit (usually hookswitch)
Bit 6:
CD2 bit or CD1B bit
Bits 5–3: Reserved
Bit 2:
CFAIL
Bits 1–0: Reserved
Bit 7 of the signaling byte will appear immediately after
bit 0 of the data byte. A-law or µ-law Companded state
must be specified in order to put signaling information
on the PCM highway. The signaling time slot remains
active, even when the channel is deactivated.
Robbed-Bit Signaling Compatibility
The QSLAC device supports robbed bit signaling
compatibility. Robbed bit signaling allows periodic use
of the least significant bit (LSB) of the receive path
PCM data to be used to carry signaling information. In
this scheme, separate circuitry within the line card or
system intercepts this bit out of the PCM data stream
and uses this bit to control signaling functions within
the system. The QSLAC device does not perform any
processing of any of the robbed bits during this
operation; it simply allows for the robbed bit presence
by performing the LSB substitution.
If the RBE bit is set, then the robbed-bit signaling
compatibility mode is enabled. Robbed-bit signaling is
only available in the µ-law companding mode of the
device. Also, only the receive (digital-to-analog) path is
involved. There is no change of operation to the transmit
path and PCM data coming out of the QSLAC device will
always contain complete PCM byte data for each time
slot, regardless of robbed-bit signaling selection.
In the absence of actual PCM data for the affected time
slots, there is an uncertainty of the legitimate value of
this bit to accurately reconstruct the analog signal.
This bit can always be assumed to be a 1 or 0; hence,
the reconstructed signal is correct half the time.
However, the other half of the time, there is an
unacceptable reconstruction error of a significance
equal to the value weighting of the LSB. To reduce this
error and provide compatibility with the robbed bit
signaling scheme, when in the robbed-bit signaling
mode, the QSLAC device ignores the LSB of each
received PCM byte and replace its value in the
expander with a value of half the LSB’s weight. This
then guarantees the reconstruction is in error by only
half this LSB weight. In the expander, the eight bits of
the companded PCM byte are expanded into linear
PCM data of several more bits within the internal signal
processing path of the device. Therefore, accuracy is
not limited to the weight of the LSB, and a weight of
half this value is realizable.
When this robbed-bit mode is selected, not every
frame contains bits for signaling, and therefore not
every byte requires its LSB substituted with the halfLSB weight. This substitution only occurs for valid
PCM time slots within frames for which this robbed bit
has been designated. To determine which time slots
are affected, the device monitors the frame sync (FS)
pulse. The current frame is a robbed-bit frame and this
half-LSB value is used only when this criteria is met:
The RBE bit is set, and
The device is in the µ-law companding mode, and
The current frame sync pulse (FS) is two PCLK
cycles long, and
The previous frame sync pulse (FS) was not two
PCLK cycles long.
The frame sync pulse is sampled on the falling edge of
PCLK. As shown in Figure 13, if the above criteria is
met, and if FS is high for two consecutive falling edges
of PCLK then low for the third falling edge, it is
considered a robbed-bit frame. Otherwise, it is a
normal frame.
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35
PCLK
Notice that these default coefficient values are retained
in a read-only memory area within the QSLAC device,
and those values cannot be read back using any data
commands. When the device is selected to use default
coefficients, it obtains those values directly from the
read-only memory area, where the coefficient read
operations access the programmable random access
data memory only. If an attempt is made to read back
any filter values without those values first being written
with known programmed data, the values read back
are totally random and do not represent the default or
any other values.
FS
COMMAND DESCRIPTION AND FORMATS
Microprocessor Interface Description
PCLK
FS
Normal Frame (Not Robbed-Bit)
A microprocessor can program and control the QSLAC
device using the MPI. Data programmed previously
can be read out for verification.
Robbed-Bit Frame
Figure 13. Robbed-Bit Frame
Default Filter Coefficients
The QSLAC device contains an internal set of default
coefficients for the programmable filters. These coefficients were determined to allow reasonable system
performance for initial power-up non-programmed situations, such as may exist before a system processor
has opportunity to program any coefficients.
The default filter coefficients are calculated assuming
an Am7920 SLIC with 50 Ω protection resistors, a
178 kΩ transversal impedance (ZT), and a 90.5 kΩ receive impedance (ZRX). This SLIC has a transmit gain
of 0.5 (GTX) and a current gain of 500 (K1). The transmit relative level is set to +0.28 dBr, and the receive relative level is set to –4.39 dBr. The equalization filters (X
and R) are not optimized. The balance filter was designed to give acceptable balance into a variety of impedances. The nominal input impedance was set to
815 Ω. If the SLIC circuit differs significantly from this
design, the default filters cannot be used and must be
replaced by programmed coefficients.
To obtain this above-system response, the default filter
coefficients are set to produce these values:
GX gain = +6 dB, GR gain = –8.984 dB
AX gain = 0 dB, AR gain = 0 dB
R filter: H(z) = 1, X filter: H(z) = 1
Z filter: H(z) = 0, B filter H(z) = 0
Commands assign values to the following channel
parameters:
Transmit time slot
Receive time slot
Transmit clock slot
Receive clock slot
Transmit gain
Receive loss
B-filter coefficients
X-filter coefficients
R-filter coefficients
Z-filter coefficients
AISN coefficient
Read/Write SLIC Input/Output
SLIC Input/Output Direction
Select A-law, µ-law, or linear code
Select Transmit PCM Port A or B or both
Select Receive PCM Port A or B
Programmed/Default B filter
Programmed/Default Z filter
Programmed/Default X filter
Programmed/Default R filter
Programmed/Default GX filter
Programmed/Default GR filter
Enable/disable AX amplifier
Enable/disable AR amplifier
Select test states
Select Active or Inactive (standby) state
Commands are provided to read values from the
following channel monitors:
SLIC status
Transmit PCM data
AISN = cutoff
36
Am79Q02/021/031 Data Sheet
Commands are provided to assign values to the
following global chip parameters:
Transmit PCM Clock Edge
Interrupt Output Drive state
Chopper Clock Frequency
Select Signaling on the PCM Highway
Select Master Clock Frequency
Channel Enable register
Debounce Time for CD1
Enable E1 Output
E1 Polarity
Commands are provided to read values from the
following global chip status monitors:
Real Time Data register
Power Interruption Bit
Clock Failure Bit
Interrupt Mask register
Revision Code Number
The following description of the MPI (Microprocessor
Interface) is valid for channel 1–4. If desired, multiple
channels may be programmed simultaneously with
identical information by setting multiple Channel
Enable bits. Channel enables are contained in the
Channel Enable register and written or read using MPI
Commands 14 and 15. If multiple Channel Enable bits
are set for a read operation, only data from the first
enabled channel will be read.
The MPI physically consists of a serial data input/
output (DIO), a data clock (DCLK), and a chip select
(CS). Individual Channel Enable bits EC1, EC2, EC3,
and EC4 are stored internally in the Channel Enable
register of the QSLAC device. The serial input consists
of 8-bit commands which may be followed with
additional bytes of input data, or may be followed by
the QSLAC device sending out bytes of data. All data
input and output is MSB (D7) first and LSB (D0) last.
All data bytes are read or written one at a time, with CS
going High for at least a minimum off period before the
next byte is read or written. Only a single channel
should be enabled during read commands.
All commands that require additional input data to the
device must have the input data as the next N words
written into the device (for example, framed by the next
N transitions of CS). Program all unused bits as 0 to
ensure compatibility with future parts. All commands
that are followed by output data will cause the device
to output data for the next N transitions of CS going
L ow. Th e Q S L AC d ev i c e w i l l n o t a c c e p t a ny
commands until all the data has been shifted out. The
output values of unused bits are not specified.
An MPI cycle is defined by transitions of CS and
DCLK. If the CS lines are held in the High state
between accesses, the DCLK may run continuously
with no change to the internal control data. Using this
method, the same DCLK may be run to a number of
QSLAC devices and the individual CS lines will select
the appropriate device to access. Between command
s equ enc e s, D CLK c an s tay i n th e Hi gh st ate
indefinitely with no loss of internal control information
regardless of any transitions on the CS lines. Between
bytes of a multibyte read or write command sequence,
DCLK can also stay in the High state indefinitely. DCLK
can stay in the Low state indefinitely with no loss of
internal control information, provided the CS lines
remain at a High level.
If a low period of CS contains less than 8 positive
DCLK transitions, it will be ignored. If it contains 8–15
positive transitions, only the last 8 transitions matter. If
it contains 16 or more positive transitions, it will cause
a hardware reset in the part. If the chip is in the middle
of a read sequence when CS goes Low, data will be
present at the DIO pin even if DCLK has no activity.
SLAC Products
37
SUMMARY OF MPI COMMANDS*
Number
Hex
Description
1
00
Deactivate (Standby Mode)
2
02
Software Reset
3
04
Hardware Reset
4
06
No Operation
Activate (Operational Mode)
5
0E
6,7
40/41
Write/Read Transmit Time Slot and PCM Highway Selection
8,9
42/43
Write/Read Receive Time Slot and PCM Highway Selection
10,11
44/45
Write/Read REC & TX Clock Slot and TX Edge
12,13
46/47
Write/Read Configuration Register
14,15
4A/4B
Write/Read Channel Enable & Operating Mode Register
16
4D
Read Real Time Data Register
17
4F
Read Real Time Data Register and Clear Interrupt
18,19
50/51
Write/Read AISN and Analog Gains
20,21
52/53
Write/Read SLIC Input/Output Register
22,23
54,55
Write/Read SLIC Input/Output Direction and Status Bits
24,25
60/61
Write/Read Operating Functions
26,27
6C/6D
Write/Read Interrupt Mask Register
28,29
70/71
Write/Read Operating Conditions
30
73
31,32
80/81
Read Revision Code Number (RCN)
Write/Read GX Filter Coefficients
33,34
82/83
Write/Read GR Filter Coefficients
35,36
84/85
Write/Read Z Filter Coefficients (FIR and IIR)
37, 38
86/87
Write/Read B1 Filter Coefficients (FIR)
39, 40
88/89
Write/Read X Filter Coefficients
41, 42
8A/8B
Write/Read R Filter Coefficients
43, 44
96/97
Write/Read B2 Filter Coefficients (IIR)
45, 46
C8/C9
Write/Read Debounce Time Register
47
CD
Read Transmit PCM Data
48, 49
98/99
Write/Read Z Filter Coefficients (FIR only)
50, 51
9A/9B
Write/Read Z Filter Coefficients (IIR only)
52,53
E8/E9h
Write/Read Ground Key Filter Sampling Interval
Note:
*All codes not listed are reserved by Legerity and should not be used.
38
Am79Q02/021/031 Data Sheet
MPI COMMAND STRUCTURE
This section details each MPI command. Each command is shown along with the format of any additional data bytes
that follow. For details of the filter coefficients of the form Cxymxy, refer to the General Description of CSD Coefficients
section on page 56.
Unused bits are indicated by “RSVD”; 0’s should be written to them, but 0’s are not guaranteed when they are read.
*Default field values are marked by an asterisk. A hardware reset forces the default values.
1.
Deactivate (Standby State)
MPI Command
(00h)
Command
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
In the Deactivated mode:
All programmed information is retained.
The Microprocessor Interface (MPI) remains active.
The PCM inputs are disabled and the PCM outputs are high impedance unless
signaling on the PCM highway is programmed (SMODE = 1).
The analog output (VOUT) is disabled and biased at 2.1 V.
The channel status (CS) bit in the SLIC I/O Direction and Channel Status Register is
set to 0.
2.
Software Reset
MPI Command
(02h)
Command
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
1
0
The action of this command is identical to that of the RST pin except that it only operates on the
channels selected by the Channel Enable Register and it does not change clock slots, time slots,
PCM highways, or global chip parameters. See the note under the hardware reset command
that follows.
3.
Hardware Reset
MPI Command
(04h)
Command
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
1
0
0
Hardware reset is equivalent to pulling the RST on the device Low. This command does not
depend on the state of the Channel Enable Register.
Note: The action of a hardware reset is described in Reset States on page 31 of the section Operating
the QSLAC Device.
SLAC Products
39
4.
No Operation
MPI Command
(06h)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
1
1
0
Command
5.
Activate Channel (Operational Mode)
MPI Command
(0Eh)
Command
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
1
1
1
0
This command places the device in the Active mode and sets CSTAT = 1. No valid PCM data
is transmitted until after the second FS pulse is received following the execution of the Activate
command.
6, 7. Write/Read Transmit Time Slot and PCM Highway Selection
MPI Command
(40/41h)
R/W = 0: Write
R/W = 1: Read
D7
Command
I/O Data
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
0
0
0
R/W
TPCM
TTS6
TTS5
TTS4
TTS3
TTS2
TTS1
TTS0
Transmit PCM Highway
TPCM = 0*
TPCM = 1
Transmit on Highway A (see TAB in Commands 10, 11)
Transmit on Highway B (see TAB in Commands 10, 11)
Transmit Time Slot
TTS = 0–127
Time Slot Number (TTS0 is LSB, TTS6 is MSB)
PCM Highway B is not available on the Am79Q021/031 QSLAC devices.
* Power Up and Hardware Reset (RST) Value = 00h, 01h, 02h, 03h for Channels 1, 2, 3, and 4,
respectively.
8, 9. Write/Read Receive Time Slot and PCM Highway Selection
MPI Command
(42/43h)
R/W = 0: Write
R/W = 1: Read
D7
Command
I/O Data
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
0
0
1
R/W
RPCM
RTS6
RTS5
RTS4
RTS3
RTS2
RTS1
RTS0
Receive PCM Highway
RPCM = 0*
RPCM = 1
Receive on Highway A
Receive on Highway B
Receive Time Slot
RTS = 0–127
Time Slot Number (RTS0 is LSB, RTS6 is MSB)
PCM Highway B is not available on the Am79Q021 and the Am79Q031 QSLAC devices.
* Power Up and Hardware Reset (RST) Value = 00h, 01h, 02h, 03h for Channels 1, 2, 3, and 4,
respectively.
40
Am79Q02/021/031 Data Sheet
10, 11. Write/Read Transmit Clock Slot, Receive Clock Slot, and Transmit Clock Edge
MPI Command
(44/45h)
R/W = 0: Write
R/W = 1: Read
D7
Command
I/O Data
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
0
1
0
R/W
TAB
XE
RCS2
RCS1
RCS0
TCS2
TCS1
TCS0
Transmit on A and B
TAB = 0*
TAB = 1
Transmit data on highway selected by TPCM (See Commands 6,7
on page 40).
Transmit data on both highways A and B
Transmit Edge
XE = 0*
XE = 1
Transmit changes on negative edge of PCLK
Transmit changes on positive edge of PCLK
Receive Clock Slot
RCS = 0*–7
Receive Clock Slot number
Transmit Clock Slot
TCS = 0*–7
Transmit Clock Slot number
The XE bit and the clock slots apply to all four channels; however, they cannot be written or read
unless at least one channel is selected in the Channel Enable Register.
* Power Up and Hardware Reset (RST) Value = 00h.
12, 13. Write/Read Configuration Register
MPI Command
(46/47h)
R/W = 0: Write
R/W = 1: Read
Command
I/O Data
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
0
1
1
R/W
INTM
CHP
SMODE
CMODE
CSEL3
CSEL2
CSEL1
CSEL0
Interrupt Mode
INTM = 0
INTM = 1*
TTL-compatible output
Open drain output
Chopper Clock Control
CHP = 0*
CHP = 1
Chopper Clock is 256 kHz (2048/8 kHz)
Chopper Clock is 292.57 kHz (2048/7 kHz)
PCM Signaling Mode
SMODE = 0*
SMODE = 1
No signaling on PCM highway
Signaling on PCM highway
Clock Source Mode
CMODE = 0
CMODE = 1*
MCLK used as master clock; no E1 multiplexing allowed
PCLK used as master clock; E1 multiplexing allowed if enabled in
commands 49, 50.
The master clock frequency can be selected by CSEL. The master clock frequency selection
affects all channels.
SLAC Products
41
Master Clock Frequency
CSEL = 0000
CSEL = 0001
CSEL = 0010
CSEL = 0011
CSEL = 01xx
CSEL = 10xx
CSEL = 11xx
CSEL = 1010*
1.536 MHz
1.544 MHz
2.048 MHz
Reserved
Two times frequency specified above (2 x 1.536 MHz,
2 x 1.544 MHz, or 2 x 2.048 MHz)
Four times frequency specified above (4 x 1.536 MHz,
4 x 1.544 MHz, or 4 x 2.048 MHz)
Reserved
8.192 MHz is the default
These commands do not depend on the state of the Channel Enable Register.
* Power Up and Hardware Reset (RST) Value = 9Ah.
14, 15. Write/Read Channel Enable and Operating Mode Register
MPI Command
(4A/4B)
R/W = 0: Write
R/W = 1: Read
D7
Command
I/O Data
RSVD
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
1
0
1
R/W
RSVD
RBE
VMODE
LPM
EC4
EC3
EC2
EC1
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
Robbed-bit Mode
RBE = 0*
RBE = 1
Robbed-bit Signaling mode is disabled.
Robbed-bit Signaling mode is enabled on PCM receiver if µ-law is
selected.
VOUT Mode
VMODE = 0*
VMODE = 1
VOUT = VREF through a resistor when channel is deactivated
VOUT high impedance when channel is deactivated.
Low Power Mode
LPM = 0*
LPM = 1
Low Power mode off
Low Power mode on while all channels are inactive
Channel Enable 4
EC4 = 0
EC4 = 1*
Disabled, Channel 4 cannot receive commands
Enabled, Channel 4 can receive commands
Channel Enable 3
EC3 = 0
EC3 = 1*
Disabled, Channel 3 cannot receive commands
Enabled, Channel 3 can receive commands
Channel Enable 2
EC2 = 0
EC2 = 1*
Disabled, Channel 2 cannot receive commands
Enabled, Channel 2 can receive commands
Channel Enable 1
EC1 = 0
EC1 = 1*
Disabled, Channel 1 cannot receive commands
Enabled, Channel 1 can receive commands
* Power Up and Hardware Reset (RST) Value = 0Fh.
42
Am79Q02/021/031 Data Sheet
16, 17. Read Real-Time Data Register
MPI Command
(4D/4Fh)
C = 0: Do not clear interrupt
C = 1: Clear interrupt
This register writes/reads real-time data with or without clearing the interrupt.
D7
Command
Output Data
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
1
1
C
1
CDB4
CDA4
CDB3
CDA3
CDB2
CDA2
CDB1
CDA1
Real Time Data
CDA1
CDB1
CDA2
CDB2
CDA3
CDB3
CDA4
CDB4
Debounced data bit 1 on Channel 1
Data bit 2 or multiplexed data bit 1 on Channel 1
Debounced data bit 1 on Channel 2
Data bit 2 or multiplexed data bit 1 on Channel 2
Debounced data bit 1 on Channel 3
Data bit 2 or multiplexed data bit 1 on Channel 3
Debounced data bit 1 on Channel 4
Data bit 2 or multiplexed data bit 1 on Channel 4
This command does not depend on the state of the Channel Enable Register.
18, 19. Write/Read AISN and Analog Gains
MPI Command
(50/51h)
R/W = 0: Write
R/W = 1: Read
Command
I/O Data
RSVD
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
0
0
R/W
RSVD
AX
AR
AISN4
AISN3
AISN2
AISN1
AISN0
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
Transmit Analog Gain
AX = 0*
AX = 1
0 dB gain
6.02 dB gain
Receive Analog Loss
AR = 0*
AR = 1
0 dB loss
6.02 dB loss
AISN coefficient
AISN = 0* – 31 See below (Default value = 0)
The Impedance Scaling Network (AISN) gain can be varied from –0.9375 to 0.9375
in multiples of 0.0625. The gain coefficient is decoded using the following equation:
h AISN = 0.0625 [ ( 16 • AISN4 + 8 • AISN3 + 4 • AISN2 + 2 • AISN1 + AISN0 ) – 16 ]
where hAISN is the gain of the AISN. A value of AISN = 10000 turns on the Full Digital
Loopback mode and a value of AISN = 0000* indicates a gain of 0 (cutoff).
* Power Up and Hardware Reset (RST) Value = 00h.
SLAC Products
43
20, 21. Write/Read SLIC Input/Output Register
MPI Command
(52/53h)
R/W = 0: Write
R/W = 1: Read
Command
I/O Data
RSVD
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
0
1
R/W
RSVD
RSVD
CD1B
C5
C4
C3
CD2
CD1
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
Pins CD1, CD2, and C3 through C5 are set to 1 or 0. The data appears latched on the CD1,
CD2, and C3 through C5 SLIC I/O pins, provided they were set in the Output mode (see
Command 22). The data sent to any of the pins set to the Input mode is latched, but does not
appear at the pins. The CD1B bit is only valid if the E1 Multiplex mode is enabled (EE1 = 1).
* Power Up and Hardware Reset (RST) Value = 00h
22, 23. Write/Read SLIC Input/Output Direction, Read Status Bits
MPI Command
(54/55h)
D7
D6
D5
D4
D3
D2
D1
D0
Command
0
1
0
1
0
1
0
R/W
Input Data
RSVD
CSTAT
CFAIL
IOD5
IOD4
IOD3
IOD2
IOD1
RSVD
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
Channel Status (Read status only, write as 0)
CSTAT = 0
CSTAT = 1
Channel is inactive (Standby mode).
Channel is active.
Clock Fail (Read status only, write as 0)
CFAIL* = 0
The internal clock is synchronized to frame synch.
CFAIL = 1
The internal clock is not synchronized to frame synch.
* The CFAIL bit is independent of the Channel Enable Register.
I/O Direction (Read/Write)
IOD5 = 0*
IOD5 = 1
IOD4 = 0*
IOD4 = 1
IOD3 = 0*
IOD3 = 1
IOD2 = 0*
IOD2 = 1
IOD1 = 0*
IOD1 = 1
C5 is an input
C5 is an output
C4 is an input
C4 is an output
C3 is an input
C3 is an output
CD2 is an input
CD2 is an output
CD1 is an input
CD1 is an output
Pins CD1, CD2, and C3 through C5 are set to Input or Output modes individually. Pins C3–C5
are not available on the Am79Q031 QSLAC device, and C5 is available only on the Am79Q021
QSLAC device.
* Power Up and Hardware Reset (RST) Value = 00h
44
Am79Q02/021/031 Data Sheet
24, 25. Write/Read Operating Functions
MPI Command
(60/61h)
R/W = 0: Write
R/W = 1: Read
D7
Command
I/O Data
D6
D5
D4
D3
D2
D1
D0
0
1
1
0
0
0
0
R/W
C/L
A/µ
EGR
EGX
EX
ER
EZ
EB
Linear Code
C/L = 0*
C/L = 1
Compressed coding
Linear coding
A-law or µ-law
A/µ = 0*
A/µ = 1
A-law coding
µ-law coding
EGR = 0*
EGR = 1
Default GR filter enabled
Programmed GR filter enabled
EGX = 0*
EGX = 1
Default GX filter enabled
Programmed GX filter enabled
EX = 0*
EX = 1
Default X filter enabled
Programmed X filter enabled
ER = 0*
ER = 1
Default R filter enabled
Programmed R filter enabled
EZ = 0*
EZ = 1
Default Z filter enabled
Programmed Z filter enabled
EB = 0*
EB = 1
Default B filter enabled
Programmed B filter enabled
GR Filter
GX Filter
X Filter
R Filter
Z Filter
B Filter
* Power Up and Hardware Reset (RST) Value = 00h.
SLAC Products
45
26, 27. Write/Read Interrupt Mask Register
MPI Command
(6C/6Dh)
R/W = 0: Write
R/W = 1: Read
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
0
1
1
0
R/W
MCDB4
MCDA4
MCDB3
MCDA3
MCDB2
MCDA2
MCDB1
MCDA1
Command
I/O Data
Mask CD Interrupt
MCDxy = 0
CDxy bit is NOT MASKED
MCDxy = 1*
CDxy bit is MASKED
x
Bit number (A or B)
y
Channel number (1 through 4)
Masked: A change does not cause the Interrupt Pin to go Low.
This command does not depend on the state of the Channel Enable Register.
* Power Up and Hardware Reset (RST) Value = FFh.
28, 29. Write/Read Operating Conditions
MPI Command
(70/71h)
R/W = 0: Write
R/W = 1: Read
Command
I/O Data
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
1
0
0
0
R/W
CTP
CRP
HPF
RG
ATI
ILB
FDL
TON
Cutoff Transmit Path
CTP = 0*
CTP = 1
Transmit path connected
Transmit path cut off
Cutoff Receive Path
CRP = 0*
CRP = 1
Receive path connected
Receive path cutoff (see note)
High Pass Filter
HPF = 0*
HPF = 1
Transmit Highpass filter enabled
Transmit Highpass filter disabled
Lower Receive Gain
RG = 0*
RG = 1
6 dB loss not inserted
6 dB loss inserted
Arm Transmit Interrupt
ATI = 0*
ATI = 1
Transmit Interrupt not Armed
Transmit Interrupt Armed
Interface Loopback
ILB = 0*
ILB = 1
TSA loopback disabled
TSA loopback enabled
Full Digital Loopback
FDL = 0*
FDL = 1
Full digital loopback disabled
Full digital loopback enabled
1 kHz Receive Tone
TON = 0*
TON = 1
1 kHz receive tone off
1 kHz receive tone on
* Power Up and Hardware Reset (RST) Value = 00h.
The B Filter is disabled during receive cutoff.
46
Am79Q02/021/031 Data Sheet
30. Read Revision Code Number (RCN)
MPI Command
(73h)
D7
Command
I/O Data
D6
D5
D4
D3
D2
D1
D0
0
1
1
1
0
0
1
1
RCN7
RCN6
RCN5
RCN4
RCN3
RCN2
RCN1
RCN0
This command returns an 8-bit number (RCN) describing the revision number of the QSLAC
device. This command does not depend on the state of the Channel Enable Register.
31, 32. Write/Read GX Filter Coefficients
MPI Command
(80/81h)
R/W = 0: Write
R/W = 1: Read
Command
D7
D6
1
0
D5
D4
0
0
D3
D2
0
0
D1
D0
0
R/W
I/O Data Byte 1
C40
m40
C30
m30
I/O Data Byte 2
C20
m20
C10
m10
The coefficient for the GX filter is defined as:
H GX = 1 + ( C10 • 2
– m10
{ 1 + C20 • 2
– m20
[ 1 + C30 • 2
– m30
( 1 + C40 • 2
– m40
)]} )
Power Up and Hardware Reset (RST) Values = A9F0 (Hex) (HGX = 1.995 (6 dB)).
Note: The default value is contained in a ROM register separate from the programmable coefficient RAM.
There is a filter enable bit in Operating Functions Register to switch between the default and programmed
values.
33, 34. Write/Read GR Filter Coefficients
MPI Command
(82/83h)
R/W = 0: Write
R/W = 1: Read
Command:
D7
D6
1
0
D5
D4
0
0
D3
D2
0
0
D1
D0
1
R/W
I/O Data Byte 1
C40
m40
C30
m30
I/O Data Byte 2
C20
m20
C10
m10
The coefficient for the GR filter is defined as:
H GR = C10 • 2
– m10
{ 1 + C20 • 2
– m20
[ 1 + C30 • 2
– m30
( 1 + C40 • 2
– m40
)]}
Power Up and Hardware Reset (RST) Values = 23A1 (Hex) (HGR = 0.35547 (–8.984 dB)).
See note under Commands 31 and 32.
SLAC Products
47
35, 36. Write/Read Z Filter Coefficients (FIR and IIR)
MPI Command
(84/85h)
R/W = 0: Write
R/W = 1: Read
This command writes and reads both the FIR and IIR filter sections simultaneously.
Command
D7
D6
1
0
D5
D4
0
0
D3
D2
0
1
D1
D0
0
R/W
I/O Data Byte 1
C40
m40
C30
m30
I/O Data Byte 2
C20
m20
C10
m10
I/O Data Byte 3
C41
m41
C31
m31
I/O Data Byte 4
C21
m21
C11
m11
I/O Data Byte 5
C42
m42
C32
m32
I/O Data Byte 6
C22
m22
C12
m12
I/O Data Byte 7
C43
m43
C33
m33
I/O Data Byte 8
C23
m23
C13
m13
I/O Data Byte 9
C44
m44
C34
m34
I/O Data Byte 10
C24
m24
C14
m14
I/O Data Byte 11
C45
m45
C35
m35
I/O Data Byte 12
C25
m25
C15
m15
I/O Data Byte 13
C26
m26
C16
m16
I/O Data Byte 14
C47
m47
C37
m37
I/O Data Byte 15
C27
m27
C17
m17
The Z-transform equation for the Z filter is defined as:
Hz ( z ) = z0 + z1 • z
–1
+ z2 • z
–2
+ z3 • z
–3
+ z4 • z
–4
–1
z 5 • z6 • z7 • z
+ -------------------------------------–1
1 – z7 • z
Sample rate = 32 kHz
For i = 0 to 5 and 7
z i = C1i • 2
– m1i
z 6 = C16 • 2
{ 1 + C2i • 2
– m16
– m2i
{ 1 + C26 • 2
[ 1 + C3i • 2
– m26
– m3i
( 1 + C4i • 2
– m4i
)]}
}
Power Up and Hardware Reset (RST) Values = 0190 0190 0190 0190 0190 0190 01 0190 (Hex)
(Hz(z) = 0)
See note under Commands 31 and 32.
Note: Z6 is used for IIR filter scaling only. Its value is typically greater than zero but less than or equal to
one. The input to the IIR filter section is first increased by a gain of 1/Z6, improving dynamic range and
avoiding truncation limitations through processing within this filter. The IIR filter output is then multiplied
by Z6 to normalize the overall gain. Z5 is the actual IIR filter gain value defined by the programmed
coefficients, but it also includes the initial 1/Z6 gain. The theoretical effective IIR gain, without the Z6 gain
and normalization, is actually Z5/Z6.
48
Am79Q02/021/031 Data Sheet
37, 38. Write/Read B1 Filter Coefficients
MPI Command
(86/87h)
R/W = 0: Write
R/W = 1: Read
Command
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
0
1
1
R/W
I/O Input Data Byte 1
C32
m32
C22
m22
I/O Input Data Byte 2
C12
m12
C33
m33
I/O Input Data Byte 3
C23
m23
C13
m13
I/O Input Data Byte 4
C34
m34
C24
m24
I/O Input Data Byte 5
C14
m14
C35
m35
I/O Input Data Byte 6
C25
m25
C15
m15
I/O Input Data Byte 7
C36
m36
C26
m26
I/O Input Data Byte 8
C16
m16
C37
m37
I/O Input Data Byte 9
C27
m27
C17
m17
I/O Input Data Byte 10
C38
m38
C28
m28
I/O Input Data Byte 11
C18
m18
C39
m39
I/O Input Data Byte 12
C29
m29
C19
m19
I/O Input Data Byte 13
C310
m310
C210
m210
I/O Input Data Byte 14
C110
m110
RSVD
RSVD
The Z-transform equation for the B filter is defined as:
–2
HB( z ) = B2 • z
+ … + B9 • z
–9
– 10
B 10 • z
+ ----------------------------–1
1 – B 11 • z
Sample rate = 16 kHz
The coefficients for the FIR B section and the gain of the IIR B section are defined as:
For i = 2 to 10,
B i = C1i • 2
– mli
[ 1 + C2i • 2
– m2i
( 1 + C3i • 2
– m3i
)]
The feedback coefficient of the IIR B section is defined as:
B 11 = C111 • 2
– m111
{ 1 + C211 • 2
– m211
[ 1 + C311 • 2
– m311
( 1 + C411 • 2
– m411
)]}
Refer to Commands 43, 44 for programming of the B11 coefficients.
Power Up and Hardware Reset (RST) Values = 36 AB B8 22 93 AB 2B 6C 46 2C 63 B6 9F 60 (Hex)
( H B ( z ) = – 0.254 • z
–2
– 0.891 • z
+ 0.014 • z
–8
–3
– 0.656 • z
+ 0.013 • z
–9
–4
– 0.090 • z
–5
+ 0.013 • z
–6
+ 0.017 • z
–7
– 10
0.016 • z
+ ----------------------------------------)
–1
1 – 0.97656 • z
See note under Commands 31 and 32.
RSVD
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
SLAC Products
49
39, 40. Write/Read X Filter Coefficients
MPI Command
(88/89h)
R/W = 0: Write
R/W = 1: Read
Command
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
1
0
0
R/W
I/O Input Data Byte 1
C40
m40
C30
m30
I/O Input Data Byte 2
C20
m20
C10
m10
I/O Input Data Byte 3
C41
m41
C31
m31
I/O Input Data Byte 4
C21
m21
C11
m11
I/O Input Data Byte 5
C42
m42
C32
m32
I/O Input Data Byte 6
C22
m22
C12
m12
I/O Input Data Byte 7
C43
m43
C33
m33
I/O Input Data Byte 8
C23
m23
C13
m13
I/O Input Data Byte 9
C44
m44
C34
m34
I/O Input Data Byte 10
C24
m24
C14
m14
I/O Input Data Byte 11
C45
m45
C35
m35
I/O Input Data Byte 12
C25
m25
C15
m15
The Z-transform equation for the X filter is defined as:
Hx ( z ) = x0 + x1 z
–1
+ x2 z
–2
+ x3 z
–3
+ x4 z
–4
+ x5 z
–5
Sample rate = 16 kHz
For i = 0 to 5, the coefficients for the X filter are defined as:
Xi = C1i • 2
– m1i
{ 1 + C2i • 2
– m2i
[ 1 + C3i • 2
– m3i
( 1 + C4i • 2
– m4i
) ]}
Power Up and Hardware Reset (RST) Values = 0111 0190 0190 0190 0190 0190 (Hex)
(Hx(z) = 1)
See note under Commands 31 and 32.
50
Am79Q02/021/031 Data Sheet
41, 42. Write/Read R Filter Coefficients
MPI Command
(8A/8Bh)
R/W = 0: Write
R/W = 1: Read
Command
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
1
0
1
R/W
I/O Input Data Byte 1
C46
m46
C36
m36
I/O Input Data Byte 2
C26
m26
C16
m16
I/O Input Data Byte 3
C40
m40
C30
m30
I/O Input Data Byte 4
C20
m20
C10
m10
I/O Input Data Byte 5
C41
m41
C31
m31
I/O Input Data Byte 6
C21
m21
C11
m11
I/O Input Data Byte 7
C42
m42
C32
m32
I/O Input Data Byte 8
C22
m22
C12
m12
I/O Input Data Byte 9
C43
m43
C33
m33
I/O Input Data Byte 10
C23
m23
C13
m13
I/O Input Data Byte 11
C44
m44
C34
m34
I/O Input Data Byte 12
C24
m24
C14
m14
I/O Input Data Byte 13
C45
m45
C35
m35
I/O Input Data Byte 14
C25
m25
C15
m15
HR = H IIR • H FIR
The Z-transform equation for the IIR filter is defined as:
–1
1–z
H IIR = --------------------------------–1
1 – ( R6 • z )
Sample rate = 8 kHz
The coefficient for the IIR filter is defined as:
R 6 = C16 • 2
– ml6
{ 1 + C26 • 2
– m26
[ 1 + C36 • 2
– m36
( 1 + C46 • 2
– m46
)]}
The Z-transform equation for the FIR filter is defined as:
H FIR ( z ) = R 0 + R 1 z
–1
+ R2 z
–2
+ R3 z
–3
+ R4 z
–4
+ R5 z
–5
Sample rate = 16 kHz
For i = 0 to 5, the coefficients for the R2 filter are defined as:
R i = C1i • 2
– m1i
{ 1 + C2i • 2
– m2i
[ 1 + C3i • 2
– m3i
( 1 + C4i • 2
– m4i
)]}
Power Up and Hardware Reset (RST) Values = 2E01 0111 0190 0190 0190 0190 0190 (Hex)
(HFIR (z) = 1, R6 = 0.9902)
See note under Commands 31 and 32.
SLAC Products
51
43, 44. Write/Read B2 Filter Coefficients (IIR)
MPI Command
(96/97h)
R/W = 0: Write
R/W = 1: Read
Command
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
1
0
1
1
R/W
I/O Data Byte 1
C411
m411
C311
m311
I/O Data Byte 2
C211
m211
C111
m111
This function is described in Write/Read B1 Filter Coefficients (FIR) on page 49.
Power Up and Hardware Reset (RST) Values = AC01 (Hex) (B11 = 0.97656)
See note under Commands 31 and 32.
45, 46. Write/Read Debounce Time Register**
MPI Command
(C8/C9h)
R/W = 0: Write
R/W = 1: Read
Command
I/O Data
D7
D6
D5
D4
D3
D2
D1
D0
1
1
0
0
1
0
0
R/W
EE1
E1P
DSH3
DSH2
DSH1
DSH0
RSVD
ECH
Enable E1
EE1 = 0*
EE1 = 1
E1 multiplexing turned off
E1 multiplexing turned on
E1 Polarity
E1P = 0*
E1 is a high-going pulse
E1P = 1
E1 is a low-going pulse
There is no E1 output unless CMODE = 1.
Debounce for Switchhook
DSH = 0–15
Debounce period in ms
DSH contains the debouncing time (in ms) of the CD1 data (usually switchhook)
entering the Real Time Data register described earlier. The input data must remain
stable for the debouncing time in order to change the appropriate real time bit.
RSVD
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
Enable Chopper
ECH = 0*
ECH = 1
Chopper output (CHCLK) turned off
Chopper output (CHCLK) turned on
* Power Up and Hardware Reset (RST) Value = 20h.
** This command applies to all channels and does not depend on the state of the Channel
Enable Register.
52
Am79Q02/021/031 Data Sheet
47. Read Transmit PCM Data
MPI Command
(CDh)
D7
Command
D6
D5
D4
D3
D2
D1
D0
1
1
0
0
1
1
0
1
Output Data Byte 1
XDAT7
XDAT6
XDAT5
XDAT4
XDAT3
XDAT2
XDAT1
XDAT0
Output Data Byte 2
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
Upper Transmit Data
XDAT contains A-law or µ-law transmit data in Companded mode.
XDAT contains upper data byte in Linear mode with sign in XDAT7.
48, 49. Write/Read FIR Z Filter Coefficients (FIR only)
MPI Command
(98/99h)
R/W = 0: Write
R/W = 1: Read
This command writes and reads only the FIR filter section without affecting the IIR.
Command
D7
D6
1
0
D5
D4
0
1
D3
D2
1
0
D1
D0
0
R/W
I/O Data Byte 1
C40
m40
C30
m30
I/O Data Byte 2
C20
m20
C10
m10
I/O Data Byte 3
C41
m41
C31
m31
I/O Data Byte 4
C21
m21
C11
m11
I/O Data Byte 5
C42
m42
C32
m32
I/O Data Byte 6
C22
m22
C12
m12
I/O Data Byte 7
C43
m43
C33
m33
I/O Data Byte 8
C23
m23
C13
m13
I/O Data Byte 9
C44
m44
C34
m34
I/O Data Byte 10
C24
m24
C14
m14
The Z-transform equation for the Z filter is defined as:
Hz ( z ) = z0 + z1 • z
–1
+ z2 • z
–2
+ z3 • z
–3
+ z4 • z
–4
–1
z 5 • z6 • z7 • z
+ -------------------------------------–1
1 – z7 • z
Sample rate = 32 kHz
For i = 0 to 5 and 7
z i = C1i • 2
z 6 = C16 • 2
– m1i
– m16
{ 1 + C2i • 2
– m2i
{ 1 + C26 • 2
[ 1 + C3i • 2
– m26
– m3i
( 1 + C4i • 2
– m4i
)]}
}
Power Up and Hardware Reset (RST) Values = 0190 0190 0190 0190 0190 0190 01 0190 (Hex)
(Hz(z) = 0)
See note under Commands 31 and 32.
Note: Z6 is used for IIR filter scaling only. Its value is typically greater than zero but less than or equal to
one. The input to the IIR filter section is first increased by a gain of 1/Z6, improving dynamic range and
avoiding truncation limitations through processing within this filter. The IIR filter output is then multiplied
by Z6 to normalize the overall gain. Z5 is the actual IIR filter gain value defined by the programmed
coefficients, but it also includes the initial 1/Z6 gain. The theoretical effective IIR gain, without the Z6 gain
and normalization, is actually Z5/Z6.
SLAC Products
53
50, 51. Write/Read IIR Z Filter Coefficients (IIR only)
MPI Command
(9A/9Bh)
R/W = 0: Write
R/W = 1: Read
This command writes/reads the IIR filter section only, without affecting the FIR.
Command
D7
D6
1
0
D5
D4
0
1
D3
D2
1
0
D1
D0
1
R/W
I/O Data Byte 11
C45
m45
C35
m35
I/O Data Byte 12
C25
m25
C15
m15
I/O Data Byte 13
C26
m26
C16
m16
I/O Data Byte 14
C47
m47
C37
m37
I/O Data Byte 15
C27
m27
C17
m17
The Z-transform equation for the Z filter is defined as:
Hz ( z ) = z0 + z1 • z
–1
+ z2 • z
–2
+ z3 • z
–3
+ z4 • z
–4
–1
z 5 • z6 • z7 • z
+ -------------------------------------–1
1 – z7 • z
Sample rate = 32 kHz
For i = 0 to 5 and 7
z i = C1i • 2
– m1i
z 6 = C16 • 2
{ 1 + C2i • 2
– m16
– m2i
{ 1 + C26 • 2
[ 1 + C3i • 2
– m26
– m3i
( 1 + C4i • 2
– m4i
)]}
}
Power Up and Hardware Reset (RST) Values = 0190 0190 0190 0190 0190 0190 01 0190 (Hex)
(Hz(z) = 0)
See note under Commands 31 and 32.
Note: Z6 is used for IIR filter scaling only. Its value is typically greater than zero but less than or equal to
one. The input to the IIR filter section is first increased by a gain of 1/Z6, improving dynamic range and
avoiding truncation limitations through processing within this filter. The IIR filter output is then multiplied
by Z6 to normalize the overall gain. Z5 is the actual IIR filter gain value defined by the programmed
coefficients, but it also includes the initial 1/Z6 gain. The theoretical effective IIR gain, without the Z6 gain
and normalization, is actually Z5/Z6.
54
Am79Q02/021/031 Data Sheet
52, 53. Write/Read Ground Key Filter
MPI Command
(E8/E9h)
R/W = 0: Write
R/W = 1: Read
Command
I/O Data
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
0
1
0
0
R/W
RSVD
RSVD
RSVD
RSVD
GK3
GK2
GK1
GK0
Filter Ground Key
GK = 0–15
Filter sampling period in 1 ms
GK contains the filter sampling time (in ms) of the CD1B data (usually Ground Key) or CD2
entering the Real Time Data register described earlier. A value of 0 disables the Ground Key
filter for that particular channel.
Power Up and Hardware Reset (RST) Value = 00h.
RSVD
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
SLAC Products
55
PROGRAMMABLE FILTERS
General Description of CSD Coefficients
Mi = the number of shifts = Mi ≤ Mi + 1
Bi = sign = ±1
N = number of CSD coefficients.
The filter functions are performed by a series of
multiplications and accumulations. A multiplication
occurs by repeatedly shifting the multiplicand and
summing the result with the previous value at that
summation node. The method used in the QSLAC
device is known as Canonic Signed Digit (CSD)
multiplication and splits each coefficient into a series
of CSD coefficients.
hi in Equation 4 represents a decimal number, broken
down into a sum of successive values of:
Each programmable FIR filter section has the following
general transfer function:
HF ( z ) = h 0 + h 1 z
–1
+ h2 z
–2
+ … + hn z
–n
The transfer function for the IIR part of Z and B filters:
Equation 2
The transfer function of the IIR part of the R filter is:
–1
– M1
+ B2 2
– M2
+ … + BN 2
– MN
±1.0 multiplied by 1, or 1/2, or 1/4 … 1/128 …
When M1 is 0, the value is a binary 1 in front of the
decimal point, that is, no shift. If M2 is also 0, the result
is another binary 1 in front of the decimal point, giving
a total value of binary 10 in front of the decimal point
(i.e., a decimal value of 2.0). The value of N, therefore,
determines the range of values the coefficient hi can
take (e.g., if N = 3 the maximum and minimum values
are ±3, and if N = 4 the values are between ±4).
Equation 3
The values of the user-defined coefficients (h i) are
assigned via the MPI. Each of the coefficients (hi) is
defined in the following general equation:
h i = B1 2
2)
The coefficient hi in Equation 4 is a value made up of
N binary 1s in a binary register where the left part
represents whole numbers, the right part decimal
fractions, and a decimal point separates them. The first
binary 1 is shifted M1 bits to the right of the decimal
point; the second binary 1 is shifted M2 bits to the right
of the decimal point; the third binary 1 is shifted M3 bits
to the right of the decimal point, and so on.
where the number of taps in the filter = n + 1.
1–z
HI ( z ) = ------------------------------–1
1 – h( n + 1) z
±1.0 multiplied by 2–0, or 2–1, or 2–2 … 2–7 …
The limit on the negative powers of 2 is determined by
the length of the registers in the ALU.
Equation 1
1
HI ( z ) = ------------------------------–1
1 – h( n + 1) z
1)
Equation 4
where:
Detailed Description of QSLAC Device Coefficients
The CSD coding scheme in the QSLAC device uses a value called mi, where m1 represents the distance shifted
right of the decimal point for the first binary 1. m2 represents the distance shifted to the right of the previous binary
1, and m3 represents the number of shifts to the right of the second binary 1. Note that the range of values
determined by N is unchanged. Equation 4 is now modified (in the case of N = 4) to:
hi = B1 2
– m1
h i = C1 • 2
+ B2 2
– m1
– m2
+ B3 2
– m3
+ C1 • C 2 • 2
+ B4 2
– ( m1 + m2 )
Equation 5
– m4
+ C1 • C 2 • C 3 • 2
– ( m1 + m2 + m3 )
+ C1 • C2 • C3 • C4 • 2
– ( m1 + m2 + m3 + m4 )
Equation 6
h i = C1 • 2
– m1
{ 1 + C2 • 2
– m2
[ 1 + C3 • 2
– m3
( 1 + C4 • 2
– m4
)] }
where:
M1 = m1
M2 = m1 + m2
M3 = m1 + m2 + m3
M4 = m1 + m2 + m3 + m4
56
B1 = C1
B2 = C1 • C2
B3 = C1 • C2 • C3
B4 = C1 • C2 • C3 • C4
Am79Q02/021/031 Data Sheet
Equation 7
In the QSLAC device, a coefficient, hi, consists of N CSD
coefficients, each being made up of 4 bits and formatted
as Cxy mxy, where Cxy is 1 bit (MSB) and mxy is 3 bits.
Each CSD coefficient is broken down as follows:
User Test States and Operating Conditions
The QSLAC device supports testing by providing test
states and special operating conditions as shown in
Figure 9 (see Operating Conditions register).
Cxy
is the sign bit (0 = positive, 1 = negative).
mxy
is the 3-bit shift code. It is encoded as a binary
number as follows:
000:
0 shifts
001:
1 shifts
010:
2 shifts
011:
3 shifts
100:
4 shifts
101:
5 shifts
110:
6 shifts
111:
7 shifts
Lower Receive Gain (LRG): When LRG = 1, an extra
6.02 dB of loss is inserted into the receive path.
y
is the coefficient number (the i in hi).
Arm Transmit Interrupt (ATI) and Read Transmit
PCM Data: The read transmit PCM data command,
Command 47, can be used to read transmit PCM data
through the microprocessor interface. If the ATI bit is
set, an interrupt will be generated whenever new
transmit data appears in the channel and will be
cleared when the data is read. When combined with
Tone Generation and Loopback states, this allows the
microprocessor to test channel integrity.
Cutoff Transmit Path (CTP): When CTP = 1, DX and
TSC are high impedance and the transmit time slot
does not exist. This state takes precedence over the
TSA Loopback (TLB) and Full Digital Loopback (FDL)
states.
Cutoff Receive Path (CRP): When CRP = 1, the
receive signal is forced to 0 just ahead of the low pass
filter (LPF) block. This state also blocks Full Digital
Loopback (FDL), the 1 kHz receive tone, and the Bfilter path.
High Pass Filter Disable (HPF): When HPF = 1, all
of the high pass and notch filters in the transmit path
are disabled.
x is the position of this CSD coefficient within the hi
coefficient. The most significant binary 1 is represented
by x = 1. The next most significant binar y 1 is
represented by x = 2, and so on.
Thus, C13 m13 represents the sign and the relative
shift position for the first (most significant) binary 1 in
the 4th (h3) coefficient.
The number of CSD coefficients, N, is limited to 4 in
the GR, GX, R, X, and Z filters; 4 in the IIR part of the
B filter; 3 in the FIR part of the B filter; and 2 in the
post-gain factor of the Z-IIR filter. The GX filter
coefficient equation is slightly different from the other
filters.
h iGX = 1 + h i
Equation 8
Please refer to the section detailing the commands for
complete details on programming the coefficients.
TSA Loopback (TLB): When TLB = 1, data from the
TSA receive path is looped back to the TSA transmit
path. Any other data in the transmit path is overwritten.
Full Digital Loopback (FDL): When FDL = 1, the
VOUT output is turned off and the analog output voltage is routed to the input of the receive path, replacing
the voltage from VIN. The AISN path is temporarily
turned off. This test state can also be entered by writing the code 10000 into the AISN register.
1 kHz Receive Tone (TON): When TON = 1, a 1 kHz
digital milliwatt is injected into the receive path,
replacing any receive signal from the TSA.
SLAC Products
57
A-Law and µ-Law Companding
Table 2 and Table 3 show the companding definitions used for A-law and µ-law PCM encoding.
Table 2. A-Law: Positive Input Values
1
Segment
Number
2
3
4
# Intervals Value at
x Interval
Segment
Size
End Points
Decision
Value
Number n
5
6
7
Character
Signal pre
Quantized
Decision Inversion of
Value (at
Even
Bits
Value xn
Decoder
(See Note 1)
Output) yn
Bit No.
8
Decoder
Output
Value No.
12345678
4096
7
(128)
(4096)
127
3968
113
2176
112
2048
16 x 128
11111111
4032
128
2112
113
1056
97
528
81
264
65
132
49
66
33
1
1
See Note 2
2048
11110000
See Note 2
6
16 x 64
1024
97
1088
96
1024
11100000
See Note 2
5
16 x 32
512
81
544
80
512
11010000
See Note 2
4
16 x 16
256
65
272
64
256
11000000
See Note 2
3
16 x 8
128
49
136
48
128
10110000
See Note 2
2
16 x 4
64
33
68
32
64
10100000
See Note 2
1
32 x 2
1
2
0
0
10000000
Notes:
1. 4096 normalized value units correspond to TMAX = 3.14 dBm0.
2. The character signals are obtained by inverting the even bits of the signals of column 6. Before this inversion, the character
signal corresponding to positive input values between two successive decision values numbered n and n+1 (see column 4)
is 128+n, expressed as a binary number.
x
+x
2
n–1
n
3. The value at the decoder output is y n = ---------------------- , for n = 1,...127, 128.
4. x128 is a virtual decision value.
5. Bit 1 is a 0 for negative input values.
58
Am79Q02/021/031 Data Sheet
Table 3. µ-Law: Positive Input Values
1
Segment
Number
2
3
# Intervals Value at
x Interval
Segment
Size
End Points
4
Decision
Value
Number n
5
6
7
Character
Signal pre
Quantized
Decision Inversion of
Value (at
Even
Bits
Value xn
Decoder
(See Note 1)
Output) yn
Bit No.
8
Decoder
Output
Value No.
12345678
8159
8
(128)
(8159)
127
7903
113
4319
112
4063
16 x 256
10000000
8031
127
4191
112
2079
96
1023
80
495
64
231
48
99
32
33
16
11111110
2
1
11111111
0
0
See Note 2
4063
10001111
See Note 2
7
16 x 128
2015
97
2143
96
2015
10011111
See Note 2
6
16 x 64
991
81
1055
80
991
10101111
See Note 2
5
16 x 32
479
65
511
64
479
10111111
See Note 2
4
16 x 16
223
49
239
48
223
11001111
See Note 2
3
16 x 8
95
33
103
32
95
11011111
See Note 2
2
16 x 4
31
17
35
16
31
11101111
See Note 2
1
15 x 2
2
3
1
1
0
0
1x1
Notes:
1. 8159 normalized value units correspond to TMAX = 3.17 dBm0.
2. The character signal corresponding to positive input values between two successive decision values numbered n and n+1
(see column 4) is 255-n, expressed as a binary number.
x
+x
n+1
n
- , for n = 1, 2,...127.
3. The value at the decoder is y0 = x0 = 0 for n = 0, and y n = ----------------------
4. x128 is a virtual decision value.
2
5. Bit 1 is a 0 for negative input values.
SLAC Products
59
APPLICATIONS
The QSLAC device performs a programmable codec/
filter function for four telephone lines. It interfaces to the
telephone lines through an Legerity SLIC device or a
transformer with external buffering. The QSLAC device
provides latched digital I/O to control and monitor four
SLICs and provides access to time-critical information,
like off/on-hook and ring trip, for all four channels via a
single read operation. When various country or
transmission requirements must be met, the QSLAC
device enables a single SLIC design for multiple
applications. The line characteristics (such as apparent
impedance, attenuation, and hybrid balance) can be
modified by programming each QSLAC device
channel’s coefficients to meet desired performance. The
QSLAC device requires an external buffer to drive
transformer SLICs.
Connection to a PCM back plane is implemented by
means of a simple buffer chip. Several QSLAC devices
can be tied together in one bus interfacing the back
plane through a single buffer. An intelligent bus
interface chip is not required because each QSLAC
device provides its own buffer control (TSXA/B). The
Q S L AC d ev i c e i s c o n t r o l l e d t h r o u g h t h e
microprocessor interface, either by a microprocessor
on the linecard or by a central processor.
Controlling the SLIC
The A m79 Q0 21 Q S LAC dev ic e ha s fi ve TTL compatible I/O pins (CD1, CD2, C3 to C5) for each
channel. The Am79Q031 QSLAC device has only CD1
and CD2 available. The outputs are programmed using
Command 19, and the status is read back using
Command 20. CD1 and CD2 for all four channels can
be read back using Command 16. The direction of the
I/O pins (input or output) is specified by programming
the SLIC I/O direction register (Commands 21 and 22).
Default Filter Coefficients
The default filter coefficients were calculated assuming an
Am7920 SLIC with 50 Ω protection resistors, a 178 kΩ
transversal impedance (ZT ), and a 90.5 k Ω receive
impedance (ZRX). This SLIC has a transmit gain of 0.5
(GTX) and a current gain of 500 (K1). The transmit
relative level was set to +0.28 dBr, and the receive
60
relative level was set to –4.39 dBr. The equalization
filters (X and R) were not optimized. The balance filter
was designed to give acceptable balance into a variety
of impedances. The nominal input impedance was set
to 815 Ω. If the SLIC circuit differs significantly from this
design, the default filters cannot be used and must be
replaced by programmed coefficients.
Calculating Coefficients with WinSLAC Software
The WinSLAC software is a program that models the
QSLAC device, the line conditions, the SLIC, and the
linecard components to obtain the coefficients of the
programmable filters of the QSLAC device and some
of the transmission performance plots.
The following parameters relating to the desired line
conditions and the components/circuits used in the
linecard are to be provided as input to the program:
1. Line impedance or the balance impedance of the
line is specified by the local PTT.
2. Desired two-wire impedance that is to appear at the
linecard terminals of the exchange.
3. Tabular data for templates describing the frequency
response and attenuation distortion of the design.
4. Relative analog signal levels for both the transmit
and receive two-wire signals.
5. Component values and SLIC device selection for
the analog portion of the line circuits.
6. Two-wire return loss template is usually specified
by the local PTT.
7. Four-wire return loss template is usually specified
by the local PTT.
The output from the WinSLAC program includes the
coefficients of the GR, GX, Z, R, X, and B filters as
well as transmission performance plots of two-wire
return loss, receive and transmit path frequency
responses, and four-wire return loss.
The software supports the use of the Legerity SLICs or
allows entry of a SPICE netlist describing the behavior
of any type of SLIC circuit.
Am79Q02/021/031 Data Sheet
PHYSICAL DIMENSIONS
PL032
Dwg rev AH; 10/99
SLAC Products
61
PL044
Dwg rev. AN; 8/99
62
Am79Q02/021/031 Data Sheet
PQT044
Dwg rev AS; 08/99
SLAC Products
63
REVISION SUMMARY
Revision B to Revision C
•
In the Connection Diagrams section, “INT” was changed to “INT” for Am79Q021JC and Am79Q021VC.
•
“Frame sync” information was added to the first paragraph on page 31.
Revision C to Revision D
•
Minor changes were made to the data sheet style and format to conform to Legerity standards.
•
Deleted the Am79Q02VC package and all references to it.
•
The physical dimensions (PL032, PL044, and PQT044) were added to the Physical Dimensions section.
•
In the Pin Description table, the second sentence was deleted from the MCLK/E1 row and the second to last
sentence was deleted from the PCLK row.
•
On page 20, row 29 was deleted.
•
On pages 23–24, the reference to “29” was deleted.
•
In the Clock Mode Operation section on page 25, the second to last sentence was deleted.
Revision D to Revision E
•
Page 59, Table 3, changed values in column 7.
Revision E to Revision F
•
All the physical dimensions were updated.
Revision F to Revision G
•
Page 28, deleted “Old Flag (CMD 47, Bit 0)” from Figure 9.
•
Page 53, “47. Read Transmit PCM Data”. Changed last row, last column from OLD to RSVD. Deleted text “Old
Data Flag...”
•
Electrical characteristics table: “pk” added to units for Iout.
Revision G to Revision H
•
64
In the “Functional Description” section, deleted “VC” as an option for the Am79Q02 QSLAC device in the table
listing the different configurations available.
Am79Q02/021/031 Data Sheet
Notes:
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cost of our customers' products. By combining process, design, systems architecture, and a complete set of
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The contents of this document are provided in connection with Legerity, Inc. products. Legerity makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product
descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights
is granted by this publication. Except as set forth in Legerity's Standard Terms and Conditions of Sale, Legerity assumes no liability whatsoever,
and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness
for a particular purpose, or infringement of any intellectual property right.
Legerity's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the
body, or in other applications intended to support or sustain life, or in any other application in which the failure of Legerity's product could create
a situation where personal injury, death, or severe property or environmental damage may occur. Legerity reserves the right to discontinue or
make changes to its products at any time without notice.
© 2001 Legerity, Inc.
All rights reserved.
Trademarks
Legerity, the Legerity logo and combinations thereof, DSLAC, QSLAC, SLAC, and WinSLAC are trademarks of Legerity, Inc.
Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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Austin, TX 78744-1812
ATLANTA
6465 East Johns Crossing, Suite 400
Duluth, GA USA 30097
MainLine: 770-814-4252
Fax: 770-814-4253
AUSTIN
4509 Freidrich Lane
Austin, TX USA 78744-1812
MainLine: 512-228-5400
Fax: 512-228-5510
BOSTON
6 New England Executive Park Suite 400
Burlington, MA USA 01803
MainLine: 781-229-7320
Fax: 781-272-3706
CHICAGO
8770 W. Bryn Mawr, Suite 1300
Chicago, IL USA 60631
MainLine: 773-867-8034
Fax: 773-867-2910
DALLAS
4965 Preston Park Blvd., Suite 280
Plano, TX USA 75093
MainLine: 972-985-5474
Fax: 972-985-5475
HUNTSVILLE
600 Boulevard South, Suite 104
Huntsville, AL USA 35802
MainLine: 256-705-3504
Fax: 256-705-3505
IRVINE
1114 Pacifica Court, Suite 250
Irvine, CA USA 92618
MainLine: 949-753-2712
Fax: 949-753-2713
NEW JERSEY
3000 Atrium Way, Suite 270
Mt. Laurel, NJ USA 08054
MainLine: 856-273-6912
Fax: 856-273-6914
OTTAWA
600 Terry Fox Drive
Ottawa, Ontario, Canada K26 4B6
MainLine: 613-599-2000
Fax: 613-599-2002
RALEIGH
2500 Regency Parkway, Suite 226
Cary, NC USA 27511
MainLine: 919-654-6843
Fax: 919-654-6781
SAN JOSE
1740 Technology Drive, Suite 290
San Jose, CA USA 95110
MainLine: 408-573-0650
Fax: 408-573-0402
Telephone: (512) 228-5400
Fax: (512) 228-5510
North America Toll Free: (800) 432-4009
Worldwide Sales Offices
Asia
Europe
HONG KONG
Units 2401-2, 24th Floor
Jubilee Centre, 18 Fenwick Street
Wanchai, Hong Kong
MainLine: 852-2864-8300
Fax: 852-2866-1323
BELGIUM
Baron Ruzettelaan 27
8310 Brugge
Belgium
MainLine: 32-50-28-88-10
Fax: 32-50-27-06-44
KOREA
135-090 18th Fl., Kyoung Am Bldg
157-26, Samsung-dong, Kangnam-ku
Seoul, Korea
MainLine: 82-2-565-5951
Fax: 82-2-565-3788
FRANCE
7, Avenue G. Pompidou
Suite 402
92300 Levallois-Perret, France
MainLine: 33-1-47-48-2206
Fax: 33-1-47-48-2568
SHANGHAI
Shanghai P.O. Box 232022
Shanghai PR China 200232
MainLine: 86-21-54233253
Fax: 86-21-54233254
GERMANY
Elisabethstrasse 89-91
80797 München, Germany
MainLine: 49-89-5908-0
Fax: 49-89-5908-1308
SHENZHEN
Room 310, Tower 9
Jinxiu Street 30 Futian District
Shenzhen, PR China 518040
MainLine: 86-755-3706-667
Fax: 86-755-3706-520
ITALY
Via F. Rosselli 3/2
20019 Settimo Mse, Milano Italy
MainLine: 39-02-3355521
Fax: 39-02-33555232
SINGAPORE
Serangoon Central Post Office
P.O. Box 537
Singapore 915502
MainLine: 65-2803267
Fax: 65-2855869
TOKYO
Shinjuku NS Bldg. 5F
2-4-1 Nishi Shinjuku, Shinjuku-ku
Tokyo, Japan 163-0805
MainLine: 81-3-5339-2011
Fax: 81-3-5339-2012
SWEDEN
Frösundaviks Allé 15, 4tr
SE-16970 Solna
Sweden
MainLine: 46-8-509-045-45
Fax: 46-8-509-046-36
UK
Regus House, Windmill Hill Business Park
Whitehill Way
SN5 6QR Swindon
Wiltshire UK
MainLine: 44-(0)1793-441408
Fax: 44-(0)1793-441608
To download or order product literature, visit our website at www.legerity.com.
To order literature in North America, call: (800) 572-4859 or 512-349-3193
or email: [email protected]
To order literature in Europe or Asia, call: 44-0-1179-341607
or email: Europe — [email protected]
Asia — [email protected]