STMICROELECTRONICS STW5098T

STw5098
Dual low power asynchronous stereo audio Codec
with integrated power amplifiers
Features
■
Dual 20 bit audio resolution, 8kHz to 96kHz
independent rate ADC and DAC
■
Dual I2S or PCM digital interfaces for dual
master
■
Sustain complex voice and audio flow with or
without mixing
■
I2C/SPI compatible control I/F
■
Asynchronous sampling ADC and DAC: they
do not require oversampled clock and
information on the audio data sampling
frequency (fs). Jitter tolerant fs
■
Wide master clock range: from 4MHz to 32MHz
■
Stereo headphones drivers, handsfree
loudspeaker driver, line out drivers
■
Mixable analog line inputs
■
Voice filters: 8/16kHz with voice channel filters
■
Automatic gain control for microphone and linein inputs
■
Frequency programmable clock outputs
■
Multibit Σ∆ modulators with data weighted
averaging ADC and DAC
■
DSP functions for bass-treble-volume control,
mute, mono/stereo selection, voice channel
filters, de-emphasis filter and dynamic
compression
■
93 dB dynamic range ADC, 0.001% THD with
full scale output @ 2.7V
■
95 dB dynamic range DAC, 0.02% THD
performance @ 2.7V over 16Ω load
STw5098
LFBGA 6x6x1.4 (112 pins)
VFBGA 5x5x1 (112 pins)
Description
STw5098 is a dual low power asynchronous
stereo audio CODEC device with headphones
amplifiers for high quality audio listening and
recording.
Two I2S/PCM digital interfaces are available, one
per master for example Bluetooth and Application
Processor, enabling concurrent audio and voice
flow between Network and user.
The STw5098 control registers are accessible
through a selectable I2C-bus compatible or SPI
compatible interface.
Applications
■
Digital cellular telephones with application
processor such as mp3 or gaming and
Bluetooth concurrent application
April 2007
Rev 1
1/85
www.st.com
1
Contents
STw5098
Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2
Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5
2/85
4.1
Naming convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3
Device programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.4
Power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.5
Master clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.6
Data rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.7
Clock generators and master mode function . . . . . . . . . . . . . . . . . . . . . . 20
4.8
Audio digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.9
Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.10
Analog output drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.11
Analog mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.12
AD paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.13
DA paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.14
Analog-only operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.15
Automatic Gain Control (AGC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.16
Interrupt request: IRQ pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.17
Headset plug-in and push-button detection . . . . . . . . . . . . . . . . . . . . . . . 26
4.18
Microphone biasing circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.1
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.2
Supply and power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.3
Gains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.4
DSP control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.5
Analog functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
STw5098
6
Contents
5.6
Digital audio interfaces master mode and clock generators . . . . . . . . . . . 41
5.7
Digital audio interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.8
Digital filters, software reset and master clock control . . . . . . . . . . . . . . . 45
5.9
Interrupt control and control interface SPI out mode . . . . . . . . . . . . . . . . 46
5.10
AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Control interface and master clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.1
Control interface I2C mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.2
Control interface SPI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.3
Master clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
7
Audio interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8
Timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
9
Operative ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10
11
9.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.2
Operative supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.3
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.4
Typical power dissipation by entity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
10.1
Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
10.2
AMCK with sinusoid input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
10.3
Analog interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
10.4
Headset plug-in and push-button detector . . . . . . . . . . . . . . . . . . . . . . . . 64
10.5
Microphone bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
10.6
Power supply rejection ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
10.7
LS and EAR gain limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Analog input/output operative ranges . . . . . . . . . . . . . . . . . . . . . . . . . 66
11.1
Analog levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
11.2
Microphone input levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
11.3
Line output levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
11.4
Power output levels HP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3/85
Contents
STw5098
11.5
Power output levels LS and EAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
12
Stereo audio ADC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
13
Stereo audio DAC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
14
AD to DA mixing (sidetone) specifications . . . . . . . . . . . . . . . . . . . . . . 71
15
Stereo analog-only path specifications . . . . . . . . . . . . . . . . . . . . . . . . 72
16
ADC (TX) & DAC (RX) specifications with voice filters selected . . . . . 73
17
Typical performance plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
18
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
18.1
LFBGA 6x6x1.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
18.2
VFBGA 5x5x1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
19
Application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
20
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
21
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4/85
STw5098
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
STw5098 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Control register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
CR0 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
CR1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
CR2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
CR3 and CR4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
CR5 and CR6 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
CR7 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
CR8 and CR9 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
CR10 and CR11 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
CR12 and CR13 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
CR14 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
CR15 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
CR16 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
CR17 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
CR18 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
CR19 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
CR21-20 and CR24-23 description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
CR22 and CR25 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
CR26 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
CR27 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
CR28 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
CR29 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
CR30 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
CR31 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
CR32 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
CR33 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
CR 34 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
CR 35 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Control interface timing with I²C format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Control interface signal timing with SPI format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
AMCK timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Audio interface signal timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Operative supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Typical power dissipation, no master clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Typical power dissipation with master clock AMCK = 13 MHz . . . . . . . . . . . . . . . . . . . . . . 61
Digital interfaces specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
AMCK with sinusoid input specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Analog interface specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Headset plug-in and push-button detector specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Microphone bias specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Power supply rejection ratio specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
LS and EAR gain limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Reference full scale analog levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Microphone input levels, absolute levels at pins connected to preamplifiers . . . . . . . . . . . 66
Microphone input levels, absolute levels at pins connected to the line-in amplifiers . . . . . 66
5/85
List of tables
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
6/85
STw5098
Absolute levels at OLP/OLN, ORP/ORN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Absolute levels at HPL - HPR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Absolute levels at 1EARP-1EARN and 2LSP - 2LSN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Stereo audio ADC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Stereo audio DAC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
AD to DA mixing (sidetone) specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Stereo analog-only path specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
ADC (TX) & DAC (RX) specifications with voice filters selected. . . . . . . . . . . . . . . . . . . . . 73
Dimensions of LFBGA 6x6x1.4 112 4R11x11. 0.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Dimensions of VFBGA 5x5x1.0 112 balls 0.4 mm pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
STw5098
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
STw5098 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power up block diagram: example shown for one entity . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Plug-in and push-button detection application note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Control interface I2C format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Control interface: I2C format timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Control interface SPI format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Control interface: SPI format timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Audio interfaces formats: delayed, left and right justified . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Audio interfaces formats: DSP, SPI and PCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Audio interface timings: master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Audio interface timing: slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
A.C. testing input-output waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Bass treble control, de-emphasis filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Dynamic compressor transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
ADC audio path measured filter response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
ADC in band audio path measured filter response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
DAC digital audio filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
DAC in band digital audio filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
ADC 96 kHz audio path measured filter response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
ADC 96 kHz audio in-band measured filter response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
ADC voice TX path measured filter response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
ADC voice TX path measured in-band filter response . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
DAC voice (RX) digital filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
DAC voice (RX) in-band digital filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
ADC path FFT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
ADC S/N versus input-level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
DAC path FFT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
DAC S/N versus input-level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Analog path FFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Analog path S/N versus input-level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
LFBGA 6x6x1.4 112 4R11x11 0.5 drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
VFBGA 5x5x1.0 112 0.4 drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
STw5098 application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7/85
Overview
1
STw5098
Overview
●
Dual 20 bit audio resolution, 8kHz to 96kHz independent rate ADC and DAC
●
Dual I2S/PCM digital interfaces for dual master
●
Sustain complex voice and audio flow with or without mixing
●
Two I2C/SPI compatible independent control interfaces
●
Asynchronous sampling ADC and DAC that do not require oversampled clock and
information on the audio data sampling frequency (fs). Jitter tolerant fs
●
Wide master clock range from 4MHz to 32MHz
●
Two stereo headphones drivers, hand free loudspeaker driver, line out drivers
●
Mixable analog line inputs
●
Voice filters: 8/16kHz with voice channel filters
●
Automatic gain control for microphone and line-in inputs
●
Four programmable master/slave serial audio data interfaces: I2S, SPI, PCM
compatible and other formats
●
Frequency programmable clock outputs
●
Multibit Σ∆ modulators with data weighted averaging ADC and DAC
●
Four DSP functions for bass-treble-volume control, mute, mono/stereo selection, voice
channel filters, de-emphasis filter and dynamic compression
●
93 dB dynamic range ADC, 0.001% THD with full scale with full scale output @ 2.7V
●
95 dB dynamic range DAC, 0.02% THD performance @ 2.7V over 16Ω load
Analog inputs
●
Selectable stereo differential or single-ended microphone amplifier inputs with 51dB
range programmable gain
●
2 microphone biasing output
●
Microphone plug-in and push-button detection input
●
Selectable stereo differential or single-ended line inputs with 38dB range
programmable gain
Analog output drivers
8/85
●
2 Stereo headphones outputs. driving capability: 40mW (0.1% THD) over 16Ω with
40dB range programmable gain
●
Common mode voltage headphones driver (phantom ground)
●
1 Balanced loudspeaker output with driving capability up to 500mW (VCCLS>3.5V; 1%
THD) over 8Ω with 30dB range programmable gain
●
1 Balanced earphone output with driving capability up to 125mW
●
Transient suppression filter during power up and power down
●
Balanced/unbalanced stereo line outputs with 1 kΩ driving capability
STw5098
Pinout
2
Pinout
Figure 1.
Pin assignment
1
2
3
4
5
6
7
8
9
10
11
GND
1SCLK
1AD_OCK
2SDA/SDIN
1DA_OCK
1AD_CK
2AS/CSB
2AD_DATA
2AD_SYNC
1DA_SYNC
1DA_DATA
2HDET
2SCLK
2AD_OCK
1CMOD
2DA_OCK
2DA_CK
AMCK
VCC
2DA_SYNC
2DA_DATA
GND
VCCA
1HDET
VCCA
2CMOD
1SDA/SDIN
2AD_CK
1AD_DATA
1AD_SYNC
2IRQ
2MBIAS
1MBIAS
2AUX1L
1AUX1L
1MICLN
VCC
VCCIO
1DA_CK
1AS/CSB
1IRQ
VCCA
1AUX1R
2AUX1R
2AUX3L
1AUX3L
1MICLP
2MICLN
2CAPLINEIN
1MICRN
2AUX3R
2MICRN
2CAPMIC
1CAPMIC
GNDA
2MICLP
1CAPLINEIN
1MICRP
1AUX3R
2MICRP
1AUX2LN
2AUX2LN
1LINEINL
2LINEINL
GNDA
1AUX2RP
1AUX2RN
2AUX2RN
1AUX2LP
2AUX2LP
2OLN
GNDCM
1HPR
2ORN
2LINEINR
2AUX2RP
1OLN
1OLP
2OLP
2HPL
1VCMHP
VCCLS
2ORP
1ORN
1LINEINR
GNDCM
VCCP
1HPL
2VCMHPS
VCCLS
GNDP
GNDP
VCCLS
1ORP
GNDP
VCCP
GNDP
1VCMHPS
2VCMHP
2LSPS
2LSP
2CAPLS
2LSNS
VCCP
2HPR
A
B
C
D
E
F
G
1EARPS
1EARP
VCCP
H
1CAPEAR
1EARN
J
1EARNS
K
2LSN
L
9/85
Pinout
Table 1.
STw5098
STw5098 pin description
Position
Type
Pin name
Description
A1
P
GND
Ground pin for the digital section
A2
DI
1SCLK
Control interface serial clock input
A3
DO
1AD_OCK
Oversampled clock out from AD clock generator
A4
DIOD
2SDA/SDIN
Control interface serial data input-output in I2C mode (SDA), control
interface serial data input in SPI mode (SDIN).
A5
DO
1DA_OCK
Oversampled clock out from DA clock generator
A6
DIO
1AD_CK
Serial data clock for stereo A/D converter
A7
DI
2AS/CSB
Control interface address select in I2C mode (AS).
Interface enable signal in SPI mode (CSB).
A8
DO
2AD_DATA
Serial data out for stereo A/D converter
A9
DIO
2AD_SYNC
Frame sync for stereo A/D converter
A10
DIO
1DA_SYNC
Frame sync for stereo D/A converter
A11
DI
1DA_DATA
Serial data In for stereo D/A converter
B1
AI
2HDET
Headset detection input
(microphone plug-in and push-button detection)
B2
DI
2SCLK
Control interface serial clock input
B3
DO
2AD_OCK
Oversampled clock out from AD clock generator
B4
DI
1CMOD
Control interface type selector I2C-bus mode or SPI mode
B5
DO
2DA_OCK
Oversampled clock out from DA clock generator
B6
DIO
2DA_CK
Serial data clock for stereo D/A converter
B7
DI
AI
AMCK
Master clock input. Accepted range 4 MHz to 32 MHz.
AMCK is a digital square wave
AMCK is an analog sinewave (Section 10.2 on page 62)
B8
P
VCC
Power supply pin for the digital section.
Operating range: from 1.71 V to 2.7 V
B9
DIO
2DA_SYNC
Frame sync for stereo D/A converter
B10
DI
2DA_DATA
Serial data in for stereo D/A converter
B11
P
GND
Ground pin for the digital section
C1
P
VCCA
Power supply pin for the analog section.
Standard operating range: from 2.7V to 3.3V
Low voltage (LV) range: from 2.4V to 2.7V
C2
AI
1HDET
Headset detection input
(microphone plug-in and push-button detection)
C3
P
VCCA
Power supply pin for the analog section.
Standard operating range: from 2.7V to 3.3V
Low voltage (LV) range: from 2.4V to 2.7V
C4
DI
2CMOD
Control interface type selector I2C-bus mode or SPI mode.
10/85
STw5098
Table 1.
Pinout
STw5098 pin description
Position
Type
Pin name
Description
C5
DIOD
1SDA/SDIN
Control interface serial data input-output in I2C mode (SDA). Control
interface serial data input in SPI mode (SDIN).
C6
DIO
2AD_CK
Serial data clock for stereo A/D converter
C7
DO
1AD_DATA
Serial data out for stereo A/D converter
C8
DIO
1AD_SYNC
Frame sync for stereo A/D converter
C9
DO
2IRQ
Programmable interrupt output. Active low signal.
C10
AO
2MBIAS
Microphone biasing pin. Fixed voltage reference
C11
AO
1MBIAS
Microphone biasing pin. Fixed voltage reference
D1
AI
2AUX1L
Left and right channel single ended pins for microphone or line input
D2
AI
1AUX1L
Left and right channel single ended pins for microphone or line input
D3
AI
1MICLN
Left and right channel differential pins for microphone input
D4
P
VCC
Power supply pin for the digital section.
Operating range: from 1.71V to 2.7V
D5
P
VCCIO
Power supply pin for the digital I ⁄ O buffers.
Operating ranges: from 1.2V to 1.8V and from 1.71V to VCC
D6
DIO
1DA_CK
Serial data clock for stereo D/A converter
D7
DI
1AS/CSB
Control interface address select in I2C mode (AS)
Interface enable signal in SPI mode (CSB)
D8
DO
1IRQ
Programmable interrupt output. Active low signal.
D9
P
VCCA
Power supply pin for the analog section.
Standard operating range: from 2.7V to 3.3V
Low voltage (LV) range: from 2.4V to 2.7V
D10
AI
1AUX1R
Left and right channel single ended pins for microphone or line input
D11
AI
2AUX1R
Left and right channel single ended pins for microphone or line input
E1
AI
2AUX3L
Left and right channel single ended pins for microphone or line input
E2
AI
1AUX3L
Left and right channel single ended pins for microphone or line input
E3
AI
1MICLP
Left and right channel differential pins for microphone input
E4
AI
2MICLN
Left and right channel differential pins for microphone input
E8
AI
2CAPLINEIN
A capacitor must be connected between CAPLINEIN and ground
E9
AI
1MICRN
Left and right channel differential pins for microphone input
E10
AI
2AUX3R
Left and right channel single ended pins for microphone or line input
E11
AI
2MICRN
Left and right channel differential pins for microphone input
F1
AI
2CAPMIC
A capacitor must be connected between CAPMIC and ground.
F2
AI
1CAPMIC
A capacitor must be connected between CAPMIC and ground
F3
P
GNDA
Ground pin for the analog section
F4
AI
2MICLP
Left and right channel differential pins for microphone input
11/85
Pinout
Table 1.
STw5098
STw5098 pin description
Position
Type
Pin name
Description
F8
AI
1CAPLINEIN
A capacitor must be connected between CAPLINEIN and ground
F9
AI
1MICRP
Left and right channel differential pins for microphone input
F10
AI
1AUX3R
Left and right channel single ended pins for microphone or line input
F11
AI
2MICRP
Left and right channel differential pins for microphone input
G1
AI
1AUX2LN
Left and right channel differential pins for microphone or line input
G2
AI
2AUX2LN
Left and right channel differential pins for microphone or line input
G3
AI
1LINEINL
Left and right channel single ended pins for line input
G4
AI
2LINEINL
Left and right channel single ended pins for line input
G8
P
GNDA
Ground pin for the analog section
G9
AI
1AUX2RP
Left and right channel differential pins for microphone or line input.
G10
AI
1AUX2RN
Left and right channel differential pins for microphone or line input
G11
AI
2AUX2RN
Left and right channel differential pins for microphone or line input
H1
AI
1AUX2LP
Left and right channel differential pins for microphone or line input
H2
AI
2AUX2LP
Left and right channel differential pins for microphone or line input
H3
AO
2OLN
Audio differential line out amplifier for left and right channels. This
outputs can drive up to 1kΩ resistive load. Can be used as single
ended output.
H4
P
GNDCM
Ground pin for analog reference.
GNDCM can be connected to GNDA
H5
AO
1EARPS
EARPS, EARNS (sense) pins must be connected on the application
board to EARP, EARN pins respectively. The connection must be as
close as possible to the pins.
H6
AO
1EARP
Analog differential loudspeaker amplifier output for left channel or
right channel or the sum of both. This output can drive 50nF (with
series resistor) or directly an earpiece transductor from 8Ω. to 32Ω.
Can deliver from 500mW to 125mW.
H7
P
VCCP
Power supply pin for the left and right output drivers (headphones
and line-out). Operating range: from VCCA to 3.3V
H8
AO
1HPR
Audio single ended headphones amplifier outputs for left and right
channels. The outputs can drive 50nF (with series resistor) or
directly an earpiece transductor of 16Ω.
H9
AO
2ORN
Audio differential line out amplifier for left and right channels. This
outputs can drive up to 1kΩ resistive load. Can be used as single
ended output.
H10
AI
2LINEINR
Left and right channel single ended pins for line input
H11
AI
2AUX2RP
Left and right channel differential pins for microphone or line input
J1
AO
1OLN
Audio differential line out amplifier for left and right channels. This
outputs can drive up to 1kΩ resistive load. Can be used as single
ended output.
12/85
STw5098
Table 1.
Pinout
STw5098 pin description
Position
Type
Pin name
Description
J2
AO
1OLP
Audio differential line out amplifier for left and right channels. This
outputs can drive up to 1kΩ resistive load. Can be used as single
ended output.
J3
AO
2OLP
Audio differential line out amplifier for left and right channels. This
outputs can drive up to 1kΩ resistive load. Can be used as single
ended output.
J4
AO
2HPL
Audio single ended headphones amplifier outputs for left and right
channels. The outputs can drive 50nF (with series resistor) or
directly an earpiece transductor of 16Ω.
J5
AO
1VCMHP
Common mode voltage headphones output. The negative pins of
headphones left and right speakers can be connected to this pin to
avoid decoupling capacitors.
J6
AI
1CAPEAR
A capacitor can be connected between this node and ground
J7
AO
1EARN
Analog differential loudspeaker amplifier output for Left channel or
Right channel or the sum of both. This output can drive 50nF (with
series resistor) or directly an earpiece transductor from 8Ω to 32Ω.;
It can deliver from 500mW to 125mW.
J8
P
VCCLS
Power supply pin for the mono differential output driver. Operating
range: from VCCA to 5.5V
J9
AO
2ORP
Audio differential line out amplifier for left and right channels. This
outputs can drive up to 1kΩ resistive load. Can be used as single
ended output.
J10
AO
1ORN
Audio differential line out amplifier for left and right channels. This
outputs can drive up to 1kΩ resistive load. Can be used as single
ended output.
J11
AI
1LINEINR
Left and right channel single ended pins for line input
K1
P
GNDCM
Ground pin for analog reference.
GNDCM can be connected to GNDA
K2
P
VCCP
Power supply pins for the left and right output drivers (headphones
and line-out).
Operating range: from VCCA to 3.3V
K3
AO
1HPL
Audio single ended headphones amplifier outputs for left and right
channels. The outputs can drive 50nF (with series resistor) or
directly an earpiece transductor of 16Ω.
K4
AO
2VCMHPS
VCMHPS (sense) pin must be connected on the application board to
VCMHP pin. The connection must be as close as possible to the
pins.
K5
P
VCCLS
Power supply pin for the mono differential output driver. Operating
range: from VCCA to 5.5V
K6
P
GNDP
Ground pin for the left, right and mono-differential output drivers.
GNDP and GNDA must be connected together.
K7
P
GNDP
Ground pin for the left, right and mono-differential output drivers.
GNDP and GNDA must be connected together.
13/85
Pinout
Table 1.
STw5098
STw5098 pin description
Position
Type
Pin name
Description
K8
AO
1EARNS
EARPS, EARNS (sense) pins must be connected on the application
board to EARP, EARN pins respectively. The connection must be as
close as possible to the pins.
K9
P
VCCLS
Power supply pins for the mono differential output driver. Operating
range: from VCCA to 5.5V
K10
AO
1ORP
Audio differential line out amplifier for left and right channels. This
outputs can drive up to 1kΩ resistive load. Can be used as single
ended output.
K11
P
GNDP
Ground pin for the left, right and mono-differential output drivers.
GNDP and GNDA must be connected together.
L1
P
VCCP
Power supply pin for the left and right output drivers (headphones
and line-out).
Operating range: from VCCA to 3.3V
L2
P
GNDP
Ground pin for the left, right and mono-differential output drivers.
GNDP and GNDA must be connected together.
L3
AO
1VCMHPS
VCMHPS (sense) pin must be connected on the application board to
VCMHP pin. The connection must be as close as possible to the
pins.
L4
AO
2VCMHP
Common mode voltage headphones output. The negative pins of
headphones left and right speakers can be connected to this pin to
avoid decoupling capacitors.
L5
AO
2LSPS
LSPS, LSNS (sense) pins must be connected on the application
board to LSP, LSN pins respectively. The connection must be as
close as possible to the pins.
L6
AO
2LSP
Analog differential loudspeaker amplifier output for Left channel or
Right channel or the sum of both. This output can drive 50nF (with
series resistor) or directly an earpiece transductor of 8Ω.; It can
deliver up to 500mW.
L7
AI
2CAPLS
A capacitor can be connected between this node and ground
L8
AO
2LSN
Analog differential loudspeaker amplifier output for Left channel or
Right channel or the sum of both. This output can drive 50nF (with
series resistor) or directly an earpiece transductor of 8Ω. Can deliver
up to 500mW.
L9
AO
2LSNS
LSPS, LSNS (sense) pins must be connected on the application
board to LSP, LSN pins respectively. The connection must be as
close as possible to the pins.
L10
P
VCCP
Power supply pin for the left and right output drivers (headphones
and line-out). Operating range: from VCCA to 3.3V
L11
AO
2HPR
Audio single ended headphones amplifier outputs for left and right
channels. The outputs can drive 50nF (with series resistor) or
directly an earpiece transductor of 16Ω.
14/85
STw5098
Pinout
Type definitions
AI
-
Analog input
AO
-
Analog output
AIO
-
Analog input output
DI
-
Digital input
DO
-
Digital output
DIO
-
Digital input output
DIOD
-
Digital input output open drain
P
-
Power supply or ground
15/85
1MICLN
1DA_DATA
1DA_CK
1DA_SYNC
1DA_OCK
AMCK
LSG1
-24:6 dB Step 2
Transient
Suppr.
Filter
MCK1
Audio
DA-I/F
CK Gen/
Master
Mode
AMCK
PLL
CK Gen/
Master
Mode
Audio
AD-I/F
Mono
Driver
HPRG1
-40:0 dB Step 2
Transient
Suppr.
Filter
Voltage
Reference
-40:0 dB Step 2
Transient
Suppr.
Filter
Dyn.Comp.
AGC
(Mic&Lin)
LSSEL1
L
(L+R)/2
R
L
DA to AD
Mixing
Gain
DAMONO
DACHSW
(Audio only)
Bass
Treble
(Audio Only)
MIXLIN1
DAC
Filter
Digital
Gain Audio/Voice
AD to DA
Mixing
Gain
(sidetone)
ADC
Filter
Digital Audio/Voice
Gain
ADCHSW
DSP1
ADMONO
R
DAC
Analog
Filter
DA Sample
Rate
Converter
Σ∆
Modulator
MIXDAC1
Digital
DA-PLL
Digital
AD-PLL
2HDET
Headset
Detection
1HDET
CurrentBias
Bandgap
Oscillator
AD_SYNC1
1SCLK
AD_SYNC2
Digital
DA-PLL
Stereo DAC
DA_SYNC2
Digital
AD-PLL
AD Sample
Rate
Converter
Registers
Control I/F
1AS/CSB
Σ∆ADC
1CMOD
Stereo ADC
Control
Logic
1SDA/SDIN
STw5098
Stereo ADC
Power-On
Reset
IRQ
Gen
1IRQ 2IRQ
DA_SYNC1
Stereo DAC
AD Sample
Rate
Converter
Σ∆ADC
VCCA
2CMOD
MIXDAC2
DA Sample
Rate
Converter
Σ∆
Modulator
DAC
Analog
Filter
2AS/CSB
R
Bass
Treble
(Audio Only)
DA to AD
Mixing
Gain
ADMONO
L
DAMONO
DACHSW
(Audio only)
ADCHSW
DAC
Filter
Digital
Audio/Voice Gain
AD to DA
Mixing
Gain
(sidetone)
R
L
MICLA2
MICRA2
-12÷0 dB
Step 1.5
AGC
(from DSP)
R
L
Dyn.Comp.
AGC
(Mic&Lin)
LSSEL2
L
(L+R)/2
R
MIC L-R
PreAmps
MICLG2
MICRG2
0÷39 dB
Step 1.5
LIN L-R
Amps
LINLG2
LINRG2
-20:+18 dB Step 2
AGC
(from DSP)
DSP2
ADC
Filter
Audio/Voice Digital
Gain
Stereo Path
2SCLK 2SDA/SDIN
MIXLIN2
1AD_OCK
1AD_SYNC
CM
Driver
Right
Driver
HPLG1
Left
Driver
Right
LineOut
GND
MIXMIC2
1AD_CK
1AD_DATA
1EARNS
1EARN
1CAPEAR
1EARP
1EARPS
1HPR
1VCMHPS
1VCMHP
1HPL
1ORN
1ORP
MICLO1
R
L
Stereo Path
VCC
Mic.
Bias
Comm.
Mode
Stereo
Sing.E.
Stereo
Sing.E.
Stereo
Diff.
Stereo
Sing.E.
Stereo
Diff.
HPRG2
Mono
Driver
AMCK
PLL
Audio
DA-I/F
CK Gen/
Master
Mode
MCK2
HPLG2
Right
Driver
CM
Driver
Left
Driver
Right
LineOut
Left
LineOut
CK Gen/
Master
Mode
Audio
AD-I/F
LSG2
-24:6 dB Step 2
Transient
Suppr.
Filter
-40:0 dB Step 2
Transient
Suppr.
Filter
Voltage
Reference
-40:0 dB Step 2
Transient
Suppr.
Filter
MICLO2
LOG: -18:0 dB Step 3
2.1V
Reference
MIC
AUX1
AUX2
AUX3
MUTE
MICSEL2
LINEIN
AUX1
AUX2
AUX3
MUTE
LINSEL2
2DA_DATA
2DA_CK
2DA_SYNC
2DA_OCK
2AD_OCK
2AD_SYNC
2AD_CK
2AD_DATA
2LSNS
2LSN
2CAPLS
2LSP
2LSPS
2HPR
2VCMHPS
2VCMHP
2HPL
2ORN
2ORP
2OLN
2OLP
2MBIAS
2CAPLINEIN
2CAPMIC
2LINEINL
2LINEINR
2AUX3R
2AUX3L
2AUX2NR
2AUX2PR
2AUX2NL
2AUX2PL
2AUX1R
2AUX1L
2MICRN
2MICRP
2MICLN
2MICLP
STw5098 block diagram
Left
LineOut
MICLA1
MICRA1
-12÷0 dB
Step 1.5
AGC
(from DSP)
R
L
VCCIO
Figure 2.
1OLP
MIC L-R
PreAmps
MICLG1
MICRG1
0÷39 dB
Step 1.5
LIN L-R
Amps
LINLG1
LINRG1
-20:+18 dB Step 2
GNDA
Block diagram
1OLN
2.1V
Reference
MIC
AUX1
AUX2
AUX3
MUTE
MICSEL1
LINEIN
AUX1
AUX2
AUX3
MUTE
LINSEL1
GNDCM
AGC
(from DSP)
MIXMIC1
GNDP
3
LOG: -18:0 dB Step 3
Mic.
Bias
Comm.
Mode
Stereo
Sing.E.
Stereo
Sing.E.
Stereo
Diff.
Stereo
Sing.E.
Stereo
Diff.
VCCLS
ADLIN2
1MBIAS
1CAPLINEIN
1CAPMIC
1LINEINL
1LINEINR
1AUX3R
1AUX3L
AUX2NR
1AUX2PR
1AUX2NL
1AUX2PL
1AUX1R
1AUX1L
1MICRN
1MICRP
VCCP
ADLIN1
16/85
ADMIC1
1MICLP
Block diagram
STw5098
ADMIC2
STw5098
Functional description
4
Functional description
4.1
Naming convention
The STw5098 is composed of two identical entities, with their respective set of control
registers.
Regarding the pin labelling, a pin name preceded by 1 refers to entity 1 and a pin name
preceded by 2 refers to entity 2 (ie.g. 1SCLK, 2SCLK). In the following sections, no
distinction is made between the two entities when it is not relevant. Consequently, the 1 and
2 prefixes for entities 1 and 2 respectively are omitted. The same naming convention applies
to the control registers (CRxxx).
4.2
Power supply
STw5098 can have different supply voltages for different blocks, to optimize performance,
power consumption and connectivity. See Section 9.2 on page 59 for voltage definition.
The correct sequence to apply supply voltage is to set first (and unset last) the digital I/O
supply (VCCIO). The other supply voltages can be set in any order and can be disconnected
individually, if needed. Disconnection does not cause any harm to the device and no extra
current is pulled from any supply during this operation. Moreover if a voltage conflict is
detected, like VCCA < VCC (not allowed), simply all blocks connected to VCCA are set to
power down and no extra current is pulled from supply.
When VCCIO is set and VCC (digital supply) is not set, all the digital output pins are in high
impedance state, while the digital inputs are disconnected to avoid power consumption for
any input voltage value between GND and VCCIO. Before VCC is disconnected the device
has to be reset (SWRES bit in CR30).
When the analog supply (VCCA) is set and VCC is not set, all the analog inputs are in high
impedance state.
The two sets of control registers are powered by VCC pins (digital supply) so if these pins
are disconnected all the information stored in control registers is lost. When the digital
supply voltage is set, a power-on-reset (POR) circuit sets all the registers content to the
default value and then generates IRQ signals writing 1 in bits PORMSK end POREV in
CR31 and CR32 respectively for both entities.
All supplies must be on during operation.
17/85
Functional description
4.3
STw5098
Device programming
STw5098 can be programmed by writing Control Registers with SPI or I2C compatible
control interface (both slave). The interface is always active, there is no need to have the
master clock running to program the device registers. The control interfaces of each entity
can be operated independently either in SPI or I2C modes.
The choice between the two interfaces for each entity is done via their input pins 1CMOD
and 2CMOD (CMOD):
1.
CMOD connected to GND: I2C compatible mode selected
The device address is selected with AS pin:
AS/CSB connected to GND:
chip address 00110101(35hex) for reading, 00110100 (34hex) for writing
AS/CSB connected to VCCIO:
chip address 00110111(37hex) for reading, 00110110 (36hex) for writing
When this mode is selected control registers are accessed through pins:
SCLK (clock)
SDA (serial data out/in, open drain)
2.
CMOD connected to VCCIO: SPI compatible mode selected
When this mode is selected control registers are accessed through:
AS/CSB (chip select, active low)
SCLK (clock)
SDIN (serial data in)
AD_OCK or DA_OCK or IRQ (serial data out, if selected)
Device Programming: I2C. The I2C Control Interface timing is shown in Section 6.1 on
page 50. The interface has an internal counter that keeps the current address of the control
register to be read or written. At each write access of the interface the address counter is
loaded with the data of the register address field. The value in the address counter is
increased after each data byte read or write. It is possible to access the interface in 2
modes: single-byte mode in which the address and data of a single register are specified,
and multi-byte mode in which the address of the first register to be written or read is
specified and all the following bytes exchanged are the data of successive registers starting
from the one specified (in multi-byte mode the internal address counter restart from register
0 after the last register 36). Using the multi-byte mode it is possible to write or read all the
registers with a single access to the device on the I2C bus. This applies to both entities of
the device.
Device Programming: SPI. The SPI Control Interface timing is shown in section
Section 6.2 on page 51. Bits SPIOSEL (SPI Output Select) in CR33 control the out pin
selection for serial data out (none, AD_OCK, DA_OCK or IRQ), while bit SPIOHIZ=1 in
CR33 selects the high impedance state of serial data out pin when idle. The first bit sent on
SDIN, after AS/CSB falling edge, sets the interface for writing (SDIN=1) or reading
(SDIN=0), then a 7-bit Control Register address follows.
If the interface is set for writing then the last 8 bits on SDIN are written in the control register.
If the interface is set for reading then after the 7 bit address STw5098 sends out 8 bits data
on the pin selected with bits SPIOSEL in CR33, while bits present at SDIN pin are ignored.
If SPIOSEL=00 (no out pin selected) the reading access on SPI interface can still be useful
to clear the IRQ event bits in CR32.
18/85
STw5098
4.4
Functional description
Power up
STw5098 internal blocks can individually be switched on and off according to the user
needs. A general power-up bit is present at bit 7 of CR0. The output drivers should always
be powered up after the general power up. See the following drawing to select the needed
block for the desired function. A fast-settling function is activated to quickly charge external
capacitors when the device is switched on (CAPLS, CAPLINEIN and CAPMIC).
Figure 3.
Power up block diagram: example shown for one entity
ENANA
ENMICL
ENHSD
POWERUP
MBIAS
ENMICR
ENADCL
ENLINL
ENADCR
STw5098
ENADCKGEN
ENLINR
ADMAST ENADOCK
ENLOL
AUDIO I/F
DAMAST ENDAOCK
ENHPL
ENMIXL
ENLS
ENDACL
ENMIXL
ENHPR
ENDACR
ENLOR
ENOSC=0
ENOSC=1
ENHPVCM
4.5
ENDACKGEN
ENPLL
ENAMCK
ENOSC
Master clock
Master clock is applied to both entities. The master clock pin (AMCK) accepts any frequency
from 4 MHz to 32 MHz. The 4-32 MHz range is divided in sub-ranges that have to be
programmed in bits CKRANGE in CR30. The jitter and spectral properties of this clock have
a direct impact on the DAC and ADC performance because it is used to directly or by integer
division drive the continuous-time to sampled-time interfaces.
19/85
Functional description
STw5098
Note that AMCK clock does not need to have any relation to any other digital or analog input
or output.
AMCK can be either a square wave or a sinewave, bit AMCKSIN in CR30 selects the proper
input mode. When a sinewave is used as input, AMCK pin must be decoupled with a
capacitor. Specification for sinusoid input can be found in Section 10.2 on page 62.
The AMCK clock is not needed when only analog functions are used. For this purpose an
internal oscillator with no external components can be used to operate the device (see
Section 4.14 on page 25).
4.6
Data rates
STw5098 supports any data rate in 2 ranges: 8 kHz to 48 kHz and 88 kHz to 96 kHz. The
range is selected with bits DA96K and AD96K in CR29 for AD and DA paths respectively.
Note:
When AD96K=1 it is required to have DA96K=1.
The rates are fully independent in A/D and D/A paths. Moreover the rates do not have to be
specified to the device and they can change on the fly, within one range, while data is
flowing.
The 2 audio data interfaces (for A/D and D/A) can independently operate in master or slave
modes.
4.7
Clock generators and master mode function
STw5098 provides 4 internal clock generators that can drive, if needed, the audio interfaces
(master mode), and/or two independent master clocks.
The AMCK clock input frequency is internally raised via a PLL on each entity to obtain a
clock (MCK) in the range 32 MHz to 48 MHz. The ratio MCK/AMCK is defined in CR30 (see
MCKCOEFF in Section 4.7 on page 20).
MCK is used to obtain, by fractional division, the oversampled clock (OCK), word clock
(SYNC) and bit clock (CK), that will therefore have edges aligned with MCK (the OCK period
can have jitter of 1 MCK period).
The frequency of OCK, SYNC and CK is set with DAOCKF in CR21/20 for DA interface, and
ADOCKF in CR24/23 for AD interface.
The ratio between OCK and SYNC clocks is selected with bit DAOCK512 in CR22 for DA
interface and bit ADOCK512 in CR25 for AD interface. The ratio between CK and SYNC
clocks depends on the selected interface format (see Audio digital interfaces paragraph
below). Note that SPI format can only be slave.
The ADOCK and DAOCK output clocks are activated by bits ENADOCK and ENDAOCK
respectively, while master mode generation is activated with two bits: first ADMAST
(DAMAST) sets ADSYNC and ADCK (DASYNC and DACK) pins as outputs, then
ADMASTGEN (DAMASTGEN) generates the SYNC and CK clocks. The logical value at
SYNC and CK pins before data generation depends on the interface selected format.
See description of CR20 to CR25 for further details.
20/85
STw5098
4.8
Functional description
Audio digital interfaces
Four separate audio data interfaces are provided for AD and DA paths to have maximum
flexibility in communicating with other devices. The 4 interfaces can have different rates and
can work in different formats and modes (i.e an AD interface can be 8 kHz PCM slave while
a DA is 44.1 kHz I2S master).
The pins used by the interfaces are:
AD_SYNC, AD_CK and AD_DATA for AD paths word clock, bit clock and data, respectively,
and
DA_SYNC, DA_CK and DA_DATA for DA paths word clock, bit clock and data, respectively.
Data is exchanged with MSB first and left channel data first in all formats. Data word-length
is selected with bits DAWL in CR26 and ADWL in CR27. AD_DATA pin, outside the selected
time slot, is in the impedance condition selected by bit ADHIZ in CR28 in all data formats
except right aligned format.
In the following paragraphs SYNC, CK and DATA will be used when the distinction between
AD and DA is not relevant. When Master Mode is selected (bits DAMAST and ADMAST in
CR22 and CR25 respectively) the SYNC and CK clocks are generated internally. In addition,
an oversampled clock can be generated for each interface (AD_OCK and DA_OCK). The
clock is available in Slave Mode also, if needed.
The AD and DA interfaces can also be used as a single bidirectional interface when they are
configured with the same format (Delayed, DSP, etc.) and AD_SYNC is connected to
DA_SYNC and DA_CK to AD_CK. Master Mode is still available selecting ADMAST or
DAMAST (not both).
The interfaces features are controlled with control registers CR26, CR27 and CR28.
Supported operating formats:
●
Delayed format (I2S compatible) (DAFORM or ADFORM =000): the Audio Interface is
I2S compatible (Figure 9 on page 54). The number of CK periods within one SYNC
period is not relevant, as long as enough CK periods are used to transfer the data and
the maximum frequency limit specified for bit clock is not exceeded. CK can be either a
continuous clock or a sequence of bursts. In master mode there are 32 CK periods per
SYNC period (that means 16 CK periods per channel) when the word length is 16 bit,
while there are 64 CK periods per SYNC period (or 32 CK periods per channel) when
word length is 18bit or higher. Bits ADSYNCP, DASYNCP and ADCKP, DACKP affect
the interface format inverting the polarity of SYNC and CK pins respectively.
●
Left aligned format (DAFORM or ADFORM =001): this format is equivalent to delayed
format without the 1 bit clock delay at the beginning of each frame (Figure 9 on
page 54).
●
Right aligned format (DAFORM or ADFORM =010): this format is equivalent to
delayed format, except that the audio data is right aligned and that the number of CK
periods is fixed to 64 for each SYNC period (Figure 9 on page 54).
●
DSP format (DAFORM or ADFORM =011) in this format the audio interface starting
from a frame sync pulse on SYNC receives (DA) or sends (AD) the left and right data
one after the other (Figure 10 on page 55). The number of CK periods within one
SYNC period is not relevant, as long as enough CK periods are used to transfer the
data and the maximum frequency limit specified for bit clock is not exceeded. CK can
be either a continuous clock or a sequence of bursts. In Master Mode there are 32 CK
periods per SYNC period when the word length is 16 bit, while there are 64 CK periods
per SYNC period when word length is 18bit or higher. Bit CKP (ADCKP and DACKP)
21/85
Functional description
STw5098
affects the interface format inverting the polarity of CK pin. Bit SYNCP (ADSYNCP and
DASYNCP) switches between delayed (SYNCP=0) and non delayed (SYNCP=1)
formats.
DSP format is suited to interface with a multi-channel serial port.
4.9
●
SPI format (DAFORM or ADFORM =100) in this format left and right data is received
with separate data burst. Every burst is identified with a low level on SYNC signal
(Figure 10 on page 55). There is no timing difference between the left and right data
burst: the two channels are identified by the startup order: the first burst after AD path
or DA path power-up identifies the left channel data, the second one is the Right
channel data, then left and right data repeat one after the other. CK must have 16
periods per channel in case of 16 bit data word and 32 periods per channel in case of
18 bit to 32 bit data word.
The SPI interface can be configured as a single-channel (mono) interface with bit SPIM
(ADSPIM and DASPIM). The mono interface always exchanges the left channel
sample.
SPI-format can only be slave: if Master Mode is selected the CK and SYNC pins are set
to 0. Bit CKP (ADCKP and DACKP) affects the interface format inverting the polarity of
CK pin.
●
PCM format (DAFORM or ADFORM =111): this format is monophonic, as it can only
receive (DA) and transmit (AD) single channel data (Figure 10 on page 55). It is mainly
used when voice filters are selected. If audio filters are used then the same sample is
sent from DA-PCM interface to both channel of DA path, and the left channel sample
from AD path is sent to AD-PCM interface. If in the AD path the right channel has to be
sent to the PCM interface then the following must be set: ADRTOL=1 (CR27) and
ENADCR=0 (CR1). In Master Mode the number of CK periods per SYNC period is
between 16 and 512 (see DAPCMF in CR22 and ADPCMF in CR25 Section 4.7 on
page 20 for details). Bit CKP (ADCKP and DACKP) affects the interface format
inverting the polarity of CK pin. Bit SYNCP (ADSYNCP and DASYNCP) switches
between delayed (SYNCP=0) and non delayed (SYNCP=1) formats.
Analog inputs
Each entity of the STw5098 has a stereo Microphone preamplifier and a stereo Line In
amplifier, with inputs selectable among 5: MIC (for Microphone preamplifiers only), LINEIN
(for Line In amplifiers only) and 3 different AUX inputs (for Microphone and Line In
amplifiers). The AUX inputs can be used simultaneously for Line In amplifiers and
Microphone preamplifiers.
The following description is for one entity, it is similar for the other entity.
●
22/85
Microphone preamplifier: it has a very low noise input, specifically designed for low
amplitude signals. For this reason the preamplifier has a high input gain (up to 39 dB)
keeping a constant 50 kΩ input impedance for the whole gain range. However it can
also be used as line in preamplifier because it can accept a high dynamic input signal
(up to 4 Vpp). There are two separate gain and attenuation stages in order to improve
the S/N ratio when the preamplifier output range is below full scale (volume
control).The gain and attenuation controls are separate for left and right channel (CR3
and CR4 respectively). The Preamplifier input is selected with bits MICSEL in CR18,
and it is disconnected when MICMUTE=1. If a single ended input is selected then the
preamplifier uses the selected pin as the positive input and connects the negative input
(for both left and right channels) to CAPMIC pin, which has to be connected through a
capacitor to a low noise ground (typically the same reference ground of the input).
STw5098
Functional description
Each stereo Microphone preamplifier is powered up with bits ENMICL and ENMICR in
CR1.
●
4.10
Line In amplifier: each line in amplifier is designed for high level input signal. The input
gain is in the range -20 dB up to 18 dB. The Line In amplifier input is selected with bits
LINSEL in CR18, and it is disconnected when LINMUTE=1. If a single ended input is
selected then the amplifier uses the selected pin as the positive input and connects the
negative input (for both left and right channels) to CAPLINEIN pin, which has to be
connected through a capacitor to a low noise ground (typically the same reference
ground of the input).
The stereo Line In amplifier is powered up with bits ENLINL and ENLINR in CR1.
Analog output drivers
Each entity of the STw5098 provides 3 different analog signal outputs and 1 common mode
reference output. The description here below is for one entity. VCCP and VCCL are common
for both entities.
●
Line out drivers: it is a stereo differential output, it can be used as single-ended output
just by using the positive or negative pin. It can drive 1 kΩ resistive load. The load can
be connected between the positive and negative pins or between one pin and ground
through a decoupling capacitor. The output gain is regulated with LOG bits in CR7, in
the range 0 to -18 dB, simultaneously for left and right channels. When used as a single
ended output the effective gain is 6 dB lower. It is muted with bit MUTELO in CR19. The
input signal of this stereo output can come from the analog mixer or directly from MIC
preamplifiers. The output Common Mode Voltage level is controlled with bits VCML in
CR19. The supply voltage of line out drivers is VCCP .
The line out drivers are powered up with bits ENLOL and ENLOR in CR1. The output
pins are in high impedance state with a 180kΩ pull-down resistor when the line out
drivers are powered down.
●
Headphones drivers: it is a stereo single ended output. It can drive 16 ohm resistive
load and deliver up to 40 mW. The output gain is regulated with HPLG and HPRG bits
in CR8 and CR9 respectively, with a range of -40 to 6 dB. It is muted with bit MUTEHP
in CR19. The input signal of this stereo output comes from the analog mixer.The output
common mode voltage is controlled with bits VCML in CR19. The supply voltage of
headphones drivers is VCCP .
The headphones drivers are powered up with bits ENHPL and ENHPR in CR2.The
output pins are in high impedance state when the headphones drivers are powered
down.
●
Common mode voltage driver: it is a single ended output with output voltage value
selectable with bits VCML in CR19, from 1.2 V to 1.65 V in steps of 150 mV. The output
voltage should be set to the value closest to VCCP/2 to optimize output drivers
performance. The common mode voltage driver is designed to be connected to the
common pin of stereo headphones, so that decoupling capacitors are not needed at
HPL and HPR outputs. The supply voltage of the common mode voltage driver is
VCCP .
The common mode voltage driver is powered up with bit ENHPVCM in CR2.The output
pin is in high impedance state when the common mode voltage driver is powered down.
23/85
Functional description
●
Note:
1
STw5098
Loudspeaker driver (one entity only): it is a monophonic differential output. It can
drive 8 Ω resistive load and deliver up to 500 mW to the load. The output gain is
regulated with LSG bits in CR7, in the range -24 to +6 dB. The input signal of the
loudspeaker driver comes from the analog mixers: bits LSSEL in CR29 select left
channel, right channel, (L+R)/2 (mono) or mute. The output common mode voltage is
obtained with an internal voltage divider from VCCLS and it is connected to CAPLS pin.
The supply voltage of the loudspeaker driver is VCCLS.
The loudspeaker driver is powered up with bit ENLS in CR2.The output pin is in high
impedance state when the loudspeaker driver is powered down.
Together with the LS driver, only a second power output is allowed among:
Ear (1EARP - 1EARN)
Headphones 1 (1HPL and 1HPR)
Headphones 2 (2HPL and 2HPR)
●
Earphone driver (one entity only): it is a monophonic differential output. It can drive
32 Ω resistive load and deliver up to 125 mW to the load. The output gain is regulated
with EARG bits in CR7, in the range -24 to +6 dB. The input signal of the loudspeaker
driver comes from the analog mixers: bits EARSEL in CR29 select left channel, right
channel, (L+R)/2 (mono) or mute. The output Common Mode Voltage is obtained with
an internal voltage divider from VCCLS and it is connected to CAPEAR pin. The supply
voltage of the loudspeaker driver is VCCLS.
The loudspeaker driver is powered up with bit ENEAR in CR2.The output pin is in high
impedance state when the loudspeaker driver is powered down.
Note:
Note on direct connection of VCCLS to the battery:
The voltage of batteries of handheld devices during charging is usually below 5.5 V, making
VCCLS supply pin suitable for a direct connection to the battery. In this case if STw5098 is
delivering the maximum power to the load and the ambient temperature is above 70 °C then
the simultaneous charging of the battery can overheat the device. A basic protection
scheme is implemented in STw5098 (activated with bit LSLIM in CR19): it limits the
maximum gain of the loudspeaker to -6 dB when VCCLS is above 4.2 V, and it removes the
limit for VCCLS below 4.0 V. The loudspeaker gain is left unchanged if it is set below -6 dB
with bits LSG. This event (VCCLS > 4.2 V) can generate, if enabled (bit VLSMSK in CR31),
an IRQ signal.
4.11
Analog mixers
STw5098 can send to the output drivers the sum of stereo audio signals from 3 different
sources of each entity: DA path (bit MIXDAC in CR17), Microphone Preamplifiers (bit
MIXMIC in CR17) and Line In Amplifiers (bit MIXLIN in CR17). The analog mixers do not
have a gain control on the inputs, therefore the user should reduce the levels of the input
signals within the analog signal range.
The stereo analog mixers are powered up with bits ENMIXL and ENMIXR in CR2.
4.12
AD paths
In each entity the AD path converts audio signals from Microphone Preamplifiers (selected
with bit ADMIC in CR17) and Line In Amplifiers (bit ADLIN in CR17) inputs to digital domain.
If both inputs are selected then the sum of the two is converted. After AD conversion the
audio data is resampled with a sample rate converter and then processed with the internal
DSP. Two different filters are selectable in the DSP (bit ADVOICE in CR29): stereo Audio
24/85
STw5098
Functional description
Filter, with DC offset removal and FIR image filtering; and a standard mono voice-channel
filter (uses left channel input and feeds both channel output). The AD path includes a digital
gain control (ADCLG, ADCRG in CR12 and CR13 respectively) in the range -57 to +8 dB.
The maximum gain from Mic Preamplifier to AD interface is then 47 dB. When Audio filter is
selected in both AD and DA paths then DA audio data can be summed to AD data and sent
to the AD Audio Interface (see DA2ADG in CR15). Left and right channels can be
independently switched on and off to save power, if needed (bits ENADCL and ENADCR in
CR1)
4.13
DA paths
In each entity the DA path converts digital data from the digital audio interface to analog
domain and feeds it to the analog mixer. Incoming audio data is processed with a DSP
where different filters are selectable (bit DAVOICE in CR29): Audio filter, stereo, with FIR
image filtering, bass and treble controls (bits BASS and TREBLE in CR14), de-emphasis
filter; and a standard voice channel filter, mono (uses left channel input and feeds both
channel output). A dynamic compression function is available for both audio and voice filters
(bit DYNC in CR14). The DA path includes a digital gain control (DACLG, DACRG in CR10
and CR11 respectively) in the range -65 to 0 dB. AD to DA mixing (sidetone) can be
enabled: see CR16 for details. Left and right channel can be independently switched on and
off to save power, if needed (bits ENDACL and ENDACR in CR1).
4.14
Analog-only operations
Each entity from the STw5098 can operate without AMCK master clock if analog-only
functions are used. It is possible to mix Microphone and Line In preamplifiers signals and
listen through headphones, loudspeaker or send them to line-out. The analog-only operation
is enabled with bit ENOSC in CR0. When ENOSC=1 the AD and DA paths cannot be used.
In Analog Mode, each of the two entities can handle two different stereo audio signals, so it
can be used as a front end for an external voice codec that does not include microphone
preamplifiers and power drivers: mic signal is sent through Microphone preamplifiers directly
to line out drivers (Transmit path), while Receive signal is sent through Line In amplifiers to
the selected power drivers.
4.15
Automatic Gain Control (AGC)
STw5098 provides a digital Automatic Gain Control in AD path for each entity. The circuit
can control the input gain at MIC preamplifier, Line In amplifier or both (bits ENAGCMIC and
ENAGCLIN in CR35). When one input is selected, the center gain value used for the input is
fixed with bits MICLG, MICRG, LINLG and LINRG in CR3 to CR6 (like in normal operation),
then the AGC circuit adds to all the gains a value in the range -10.5 dB to +10.5 dB (or,
extended with bit AGCRANGE in CR35, -21 dB to 21 dB), in order to obtain an average level
at the digital interface output in the range -6 dB to -30 dB (selected with bits AGCLEV in
CR35). The AGC added gain acts directly in the input gain, to avoid input saturation and
improve S/N ratio, so it cannot exceed the input gain range. When MIC and Line-In inputs
are selected simultaneously the control is performed on the sum of the two, preserving the
balance fixed with input gains. Different values for Attack and Decay constants can be
selected, depending on the kind of signal the AGC has to control (i.e. voice, music). The
25/85
Functional description
STw5098
Attack and Decay time constants are related to the AD data rate (see bits AGCATT and
AGCDEL in CR34).
4.16
Interrupt request: IRQ pins
On each entity of the STw5098, the interrupt request feature can signal to a control device
the occurrence of particular events on each entity. Two control registers are used to choose
the behavior of IRQ pin: the first is a Status/Event Register (CR32), where bits can
represent the status of an internal function (i.e. a voltage is above or below a threshold) or
an event (i.e. a voltage changed crossing a threshold); the second is a Mask Register
(CR31) where if a bit in the mask is set to 1 then the corresponding bit in the Status/Event
Register can affect IRQ pin status.
On each entity, the IRQ pin is always active low. At VCC power up an interrupt request is
generated by the Power-On-Reset circuit that sets to 1 bits PORMSK in CR31 and POREV
in CR32. After this event the PORMSK bit should be cleared by the user and bit IRQCMOS
in CR33 should be set according to the application (open drain or CMOS).
When an IRQ event occurs and SPI control interface is selected with no serial output pin it is
still possible to identify the event (and relative status) that generated the interrupt request.
This can be done by setting the IRQ mask/enable bits (in CR31) one at the time (with
successive writings) and reading the IRQ pin status. A simple example of this is the headset
plug-in detection: at first we set bit HSDETMSK=1 in CR31 (with all the other bits set to 0). If
there is an interrupt request then we set HSDETMSK=0 and HSDETEN=1, so we can read
the HSDET status at IRQ pin. Then we read CR32 to clear its content (even if no data is
sent out).
4.17
Headset plug-in and push-button detection
Each entity of the STw5098 can detect the plug-in of a microphone connector and the
press/release event of a call/answer push-button. An application example can be found
below, while specifications can be found in Section 10.4 on page 64.
Figure 4.
Plug-in and push-button detection application note
HDET
AUX1L
200nF
AUX1R
VCCA
3kΩ
1.5kΩ
Call/Answer Button
10µF
From driver
Generic Connector
26/85
STw5095
200nF
CAPMIC
STw5098
4.18
Functional description
Microphone biasing circuits
The Microphone Biasing Circuits can drive mono or stereo microphones and can switch
them off when not needed in order to save the current used by the microphone biasing
network on each entity. Two bits control the behavior of the microphone bias circuit: MBIAS
in CR17 enables the circuit (fixed voltage at MBIAS pin), while bit MBIASPD in CR17 affects
the behavior of MBIAS pin when the function is not enabled. In particular when MBIASPD=1
the MBIAS pin is pulled down, otherwise it is left in tristate mode. The specification for the
microphone biasing circuits can be found in Section 10.6 on page 64.
27/85
Control registers
STw5098
5
Control registers
5.1
Summary
Table 2.
Control register summary
CR#
(hex)
Description
CR0
(00h)
D7
D6
D5
D4
D3
D2
D1
D0
Def.
Supply & power
control #1
POWER
UP
ENANA
ENAMCK
ENOSC
ENPLL
ENHSD
A24V
D12V
0000
0000
CR1
(01h)
Power control #2
ENADCL
ENADCR
ENDACL
ENDACR
ENMICL
ENMICR
ENLINL
ENLINR
0000
0000
CR2
(02h)
Power control #3
ENLOL
ENLOR
ENHPL
ENHPR
ENHPVC
M
1ENEAR
2ENLS
ENMIXL
ENMIXR
0000
0000
CR3
(03h)
Mic gain left
MICLA(2:0)
MICLG(4:0)
0000
0000
CR4
(04h)
Mic gain right
MICRA(2:0)
MICRG(4:0)
0000
0000
CR5
(05h)
Line in gain left
X
X
X
LINLG(4:0)
0000
1001
CR6
(06h)
Line in gain right
X
X
X
LINRG(4:0)
0000
1001
CR7
(07h)
LO gain & LS
gain
X
CR8
(08h)
HPL gain
X
X
X
HPLG(4:0)
0000
0011
CR9
(09h)
HPR gain
X
X
X
HPRG(4:0)
0000
0011
CR10
(0Ah)
DAC digital gain
left
X
X
DACLG(5:0)
0000
0000
CR11
(0Bh)
DAC digital gain
right
X
X
DACRG(5:0)
0000
0000
CR12
(0Ch)
ADC digital gain
left
X
X
ADCLG(5:0)
0000
1000
CR13
(0Dh)
ADC digital gain
right
X
X
ADCRG(5:0)
0000
1000
CR14
(0Eh)
Bass/treble/deemphasis
CR15
(0Fh)
DA to AD mixing
gain
X
X
CR16
(10h)
AD to DA
mix/sidetone
gain
X
X
CR17
(11h)
Mixer switches &
mic bias
MBIAS
M
BIASPD
28/85
1EARG(3:0)
2LSG(3:0)
LOG(2:0)
DYNC
TREBLE(2:0)
0000
0011
0000
0000
BASS(3:0)
X
0000
0000
DA2ADG(4:0)
0000
0000
AD2DAG(5:0)
ADMIC
ADLIN
MIXMIC
MIXLIN
MIXDAC
MICLO
0000
0000
STw5098
Table 2.
Control registers
Control register summary
CR#
(hex)
Description
CR18
(12h)
Input switches
CR19
(13h)
Drivers control
CR20
(14h)
DAOCK
frequency LSB
DAOCKF(7:0)
0000
0000
CR21
(15h)
DAOCK
frequency MSB
DAOCKF(15:8)
0000
0000
CR22
(16h)
DA clock
generator control
CR23
(17h)
ADOCK
frequency LSB
ADOCKF(7:0)
0000
0000
CR24
(18h)
ADOCK
frequency MSB
ADOCKF(15:8)
0000
0000
CR25
(19h)
AD Clock
generator control
X
CR26
(1Ah)
DAC data IF
control
X
DAFORM(2:0)
DASPIM
DAWL(2:0)
0000
0000
CR27
(1Bh)
ADC data IF
control
ADRTOL
ADFORM2:0)
ADSPIM
ADWL(2:0)
0000
0000
CR28
(1Ch)
DAC&ADC data
IF control
CR29
(1Dh)
D7
D6
D5
X
IN2VCM
LINMUTE
VCML(1:0)
X
D4
LINSEL(1:0)
X
X
X
DAMAST
ADMAST
D3
MUTELO
DA
MASTGEN
AD
MASTGEN
MUTEHP
END
AOCK
ENA
DOCK
D2
D1
D0
Def.
MICMUTE
MICSEL(1:0)
0010
0100
1EARLIM
2LSLIM
1EARSEL(1:0)
2LSSEL(1:0)
0101
1000
DAO
CK512
DAPCMF(1:0)
ADO
CK512
ADPCMF(1:0)
0000
0000
0000
0000
AMC
KINV
DACKP
DASYNCP
DAMONO
ADCKP
AD
SYNCP
ADMONO
ADHIZ
0000
0000
Digital filters
control
X
DAVOICE
DA96K
RXNH
ADVOICE
AD96K
ADNH
TXNH
0000
0000
CR30
(1Eh)
Soft reset &
AMCK range
SWRES
X
X
X
AMCKSIN
CR31
(1Fh)
Interrupt mask
VLSHEN
PUSH
BEN
HSDETEN
VLSHMSK
PUSH
BMSK
CR32
(20h)
Interrupt status
VLSH
PUSHB
HSDET
VLSHEV
CR33
(21h)
Misc. control
X
X
SPIOHIZ
CR34
(22h)
AGC
attack/decay
coeff.
CR35
(23h)
AGC control
X
ENA
GCLIN
ENAG
CMIC
AGC
RANGE
CR36
(24h)
RESERVED
X
X
X
X
HSDET
MSK
PUSHBEV HSDETEV
SPIOSEL(1:0)
AGCATT(3:0)
X
0000
0000
CKRANGE(2:0)
IRQCMOS
OVFMSK
PORMSK
0000
0000
OVFEV
POREV
0000
0000
OVFDA
OVFAD
0000
0000
AGCDEC(3:0)
0000
0000
AGCLEV(3:0)
0000
0000
X
X
X
0000
0000
Note: X reserved, write zero
29/85
Control registers
STw5098
Caution:
In the following Section 5: Control registers, reference to each entity is omitted. Each entity
of the STw5098 has the same register set.
5.2
Supply and power control
CR#
(hex)
Description
D7
D6
D5
D4
D3
D2
D1
D0
Def.
CR0
(00h)
Supply & power
control #1
POWER
UP
ENANA
ENAMCK
ENOSC
ENPLL
ENHSD
A24V
D12V
0000
0000
CR1
(01h)
Power control #2
ENADCL
ENADCR
ENDACL
ENDACR
ENMICL
ENMICR
ENLINL
ENLINR
0000
0000
CR2
(02h)
Power control #3
ENLOL
ENLOR
ENHPL
ENHPR
ENH
PVCM
ENLS
ENMIXL
ENMIXR
0000
0000
Table 3.
Bits
CR0 description
Name
Val.
CR0 description
Def.
7
POWERUP
1
0
All the enabled analog and digital blocks are in power up
All the device is in power down
0
6
ENANA
1
0
The analog blocks can be enabled
All the analog blocks are in power down
0
5
ENAMCK
1
0
AMCK clock input pin is enabled
AMCK clock input pin is disabled
0
1
4
ENOSC
0
0
The Internal oscillator is enabled.
The analog blocks use oscillator clock
The internal oscillator is in power down
3
ENPLL
1
0
The PLL is enabled
The PLL is in power down
0
2
ENHSD
1
0
The headset plug-in detector is enabled
The headset plug-in detector is disabled
0
1
A24V
1
0
Analog supply pins voltage range is 2.4V<VCCA<2.7V
Analog supply pins voltage range is 2.7V<VCCA<3.3V
0
0
D12V
1
0
Digital I/O pin voltage range is 1.2V<VCCIO<1.8V
Digital I/O pin voltage range is 1.71V<VCCIO<VCC
0
30/85
STw5098
Table 4.
Bits
Control registers
CR1 description
Name
Value
CR1 description
Def.
7
ENADCL
1
0
The left channel A/D converter is enabled
The left channel A/D converter is in power down
0
6
ENADCR
1
0
The right channel A/D converter is enabled
The right channel A/D converter is in power down
0
5
ENDACL
1
0
The left channel D/A converter is enabled
The left channel D/A converter is in power down
0
4
ENDACR
1
0
The right channel D/A converter is enabled
The right channel D/A converter is in power down
0
3
ENMICL
1
0
The left channel microphone preamplifier is enabled
The left channel microphone preamplifier is in power down
0
2
ENMICR
1
0
The right channel microphone preamplifier is enabled
The right channel microphone preamplifier is in power down
0
1
ENLINL
1
0
The left channel line-in preamplifier is enabled
The left channel line-in preamplifier is in power down
0
0
ENLINR
1
0
The right channel line-in preamplifier is enabled
The right channel line-in preamplifier is in power down
0
Table 5.
Bit #
CR2 description
Name
Value
CR2 Description
Def.
7
ENLOL
1
0
The left channel line out driver is enabled
The left channel line out driver is in power down (default)
0
6
ENLOR
1
0
The right channel line out driver is enabled
The right channel line out driver is in power down (default)
0
5
ENHPL
1
0
The left channel headphones driver is enabled
The left channel headphones driver is in power down (default)
0
4
ENHPR
1
0
The right channel headphones driver is enabled
The right channel headphones driver is in power down (default)
0
3
ENHPVCM
1
0
The headphones reference voltage generator is enabled
The headphones reference voltage generator is in power down (def)
0
1ENEAR
1
0
The 32Ω earphone amplifier is enabled
The 32Ω earphone amplifier is in power down (default)
0
2ENLS
1
0
The 8Ω loudspeaker amplifier is enabled
The 8Ω loudspeaker amplifier is in power down (default)
0
1
ENMIXL
1
0
The left channel analog output mixer is enabled
The left channel analog output mixer is in power down (default)
0
0
ENMIXR
1
0
The right channel analog output mixer is enabled
The right channel analog output mixer is in power down (default)
0
2
31/85
Control registers
5.3
STw5098
Gains
CR#
(hex)
Description
D7
D6
D5
D4
D3
D2
D1
D0
Def.
CR3
(03h)
Mic gain left
MICLA(2:0)
MICLG(4:0)
0000
0000
CR4
(04h)
Mic gain right
MICRA(2:0)
MICRG(4:0)
0000
0000
CR5
(05h)
Line in gain left
X
X
X
LINLG(4:0)
0000
1001
CR6
(06h)
Line in gain right
X
X
X
LINRG(4:0)
0000
1001
CR7
(07h)
LO gain & LS
gain
X
CR8
(08h)
HPL gain
X
X
X
HPLG(4:0)
0000
0011
CR9
(09h)
HPR gain
X
X
X
HPRG(4:0)
0000
0011
CR10
(0Ah)
DAC digital gain
left
X
X
DACLG(5:0)
0000
0000
CR11
(0Bh)
DAC digital gain
right
X
X
DACRG(5:0)
0000
0000
CR12
(0Ch)
ADC digital gain
left
X
X
ADCLG(5:0)
0000
1000
CR13
(0Dh)
ADC digital gain
right
X
X
ADCRG(5:0)
0000
1000
Table 6.
Bits
7-5
4-0
32/85
LOG(2:0)
LSG(3:0)
0000
0011
CR3 and CR4 description
Name CR3
Name CR4
MICLA(2:0)
MICRA(2:0)
MICLG(4:0)
MICRG(4:0)
Value
CR3 and CR4 description
000
001
010
...
110
111
Left (CR3) and right (CR4) channels microphone attenuation
0.0 dB gain (default)
-1.5 dB gain
-3.0 dB gain
...step 1.5 dB
-9.0 dB gain
-12.0 dB gain
00000
00001
00010
...
11010
Left (CR3) and right (CR4) channels microphone gain
0.0 dB gain (default)
1.5 dB gain
3.0 dB gain
...step 1.5 dB
39.0 dB gain
Def.
000
00000
STw5098
Table 7.
Name CR6
LINLG(4:0)
LINRG(4:0)
Table 8.
Bits
6-4
CR5 and CR6 description
Name CR5
Bits
4-0
Control registers
Value
00000
00001
00010
...
01001
...
10011
LOG(2:0)
Value
3-0
2LSG(3:0)
4-0
01001
CR7 description
Def.
000
001
010
...
110
Left and right channel line out drivers gain
Gain to differential output
Equivalent single-ended gain
18.0 dB gain (default)
-24.0 dB gain (default)
-15.0 dB gain
-21.0 dB gain
-12.0 dB gain
-18.0 dB gain
...step 3 dB
...step 3 dB
00 dB gain
-6.0 dB gain
000
0000
0001
0010
0011
...
1111
32Ω earphone gain/ 8Ω loudspeaker gain
6.0 dB gain
4.0 dB gain
2.0 dB gain
0.0 dB gain (default)
...step 2.0 dB
-24.0 dB gain
0011
1EARG(3:0)
Bits
Left (CR5) and right (CR6) channels line in gain
18.0 dB gain
16.0 dB gain
14.0 dB gain
...step 2.0 dB
0.0 dB gain (default)
...step 2.0 dB
-20.0 dB gain
Def.
CR7 description
Name
Table 9.
CR5 and CR6 description
CR8 and CR9 description
Name CR8
Name CR9
HPLG(4:0)
HPRG(4:0)
Value
00000
00001
00010
00011
...
10100
CR8 and CR9 description
Left (CR8) and right (CR9) channels headphones driver gain
0.0 dB gain
-2.0 dB gain
-4.0 dB gain
-6.0 dB gain (default)
...step 2.0 dB
-40.0 dB gain
Def.
00011
33/85
Control registers
Table 10.
Bits
5-0
34/85
STw5098
CR10 and CR11 description
Name CR10
Name CR11
DACLG(5:0)
DACRG(5:0)
Value
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
100000
100001
100010
100011
100100
100101
CR10 and CR11 description
Left (CR10) and right (CR11) channels DAC digital gain
0.0 dB gain (default)
-1.0 dB gain
-2.0 dB gain
-3.0 dB gain
-4.0 dB gain
-5.0 dB gain
-6.0 dB gain
-7.0 dB gain
-8.0 dB gain
-9.0 dB gain
-10.0 dB gain
-11.0 dB gain
-12.0 dB gain
-13.0 dB gain
-14.0 dB gain
-15.0 dB gain
-16.0 dB gain
-17.0 dB gain
-18.0 dB gain
-20.0 dB gain
-22.0 dB gain
-24.0 dB gain
-26.0 dB gain
-28.0 dB gain
-30.0 dB gain
-32.0 dB gain
-34.0 dB gain
-36.0 dB gain
-38.0 dB gain
-41.0 dB gain
-44.0 dB gain
-47.0 dB gain
-50.0 dB gain
-53.0 dB gain
-56.0 dB gain
-59.0 dB gain
-65.0 dB gain
-∞ dB gain
Def.
000000
STw5098
Table 11.
Bits
5-0
Control registers
CR12 and CR13 description
Name CR12
Name CR13
ADCLG(5:0)
ACDRG(5:0)
Value
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
100000
100001
100010
100011
100100
100101
100110
CR12 and CR13 description
Left (CR12) and right (CR13) channels ADC digital gain
8.0 dB gain
7.0 dB gain
6.0 dB gain
5.0 dB gain
4.0 dB gain
3.0 dB gain
2.0 dB gain
1.0 dB gain
0.0 dB gain (default)
-1.0 dB gain
-2.0 dB gain
-3.0 dB gain
-4.0 dB gain
-5.0 dB gain
-6.0 dB gain
-7.0 dB gain
-8.0 dB gain
-9.0 dB gain
-10.0 dB gain
-11.0 dB gain
-12.0 dB gain
-14.0 dB gain
-16.0 dB gain
-18.0 dB gain
-20.0 dB gain
-22.0 dB gain
-24.0 dB gain
-26.0 dB gain
-28.0 dB gain
-30.0 dB gain
-33.0 dB gain
-36.0 dB gain
-39.0 dB gain
-42.0 dB gain
-45.0 dB gain
-48.0 dB gain
-51.0 dB gain
-57.0 dB gain
-∞ dB gain
Def.
001000
35/85
Control registers
5.4
STw5098
DSP control
CR#
(hex)
Description
D7
D6
CR14
(0Eh)
Bass/treble/deemphasis
CR15
(0Fh)
DA to AD mixing
gain
X
X
CR16
(10h)
AD to DA
mix/sidetone
gain
X
X
Table 12.
Bits
7
6-4
3-0
36/85
DYNC
D5
D4
D3
D2
TREBLE(2:0)
D1
BASS(3:0)
X
DA2ADG(4:0)
AD2DAG(5:0)
D0
Def.
0000
0000
0000
0000
0000
0000
CR14 description
Name
DYNC
TREBLE(2:0)
BASS(3:0)
Value
CR14 description
Def.
1
0
Audio dynamic compression in D/A path is enabled
Audio dynamic compression in D/A path is disabled
011
010
001
000
111
110
101
100
Treble control in D/A path
+6.0 dB treble gain
+4.0 dB treble gain
+2.0 dB treble gain
0.0 dB treble gain
-2.0 dB treble gain
-4.0 dB treble gain
-6.0 dB treble gain
De-emphasis filter enabled
000
0101
0100
0011
0010
0001
0000
1111
1110
1101
1100
1011
Bass control in D/A path
+12.5 dB bass gain
+10.0 dB bass gain
+7.5 dB bass gain
+5.0 dB bass gain
+2.5 dB bass gain
0.0 dB bass gain
-2.5 dB bass gain
-5.0 dB bass gain
-7.5 dB bass gain
-10.0 dB bass gain
-12.5 dB bass gain
0000
0
STw5098
Table 13.
Bits
4-0
Control registers
CR15 description
Name
DA2ADG(4:0)*
Value
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
CR15 description
DA to AD mixing (Audio filter in D/A and A/D path selected)
DA to AD mixing disabled (default)
+2.0 dB gain
0.0 dB gain
-2.0 dB gain
-4.0 dB gain
-6.0 dB gain
-8.0 dB gain
-10.0 dB gain
-12.0 dB gain
-14.0 dB gain
-16.0 dB gain
-18.0 dB gain
-20.0 dB gain
-22.0 dB gain
-24.0 dB gain
-26.0 dB gain
-28.0 dB gain
-30.0 dB gain
-32.0 dB gain
-34.0 dB gain
-36.0 dB gain
-38.0 dB gain
-40.0 dB gain
Def.
00000
* When Voice filter in D/A or A/D path is selected this function is disabled
Note:
D/A to A/D mixing is performed at AD data rate, so if A/D and D/A rates are different then asynchronous sampling artifacts
may occur.
37/85
Control registers
Table 14.
Bits
5-0
38/85
STw5098
CR16 description
Name
AD2DAG(5:0)
Value
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
CR16 description
AD to DA mixing (sidetone)
AD to DA mixing disabled (default)
-1.0 dB gain
-2.0 dB gain
-3.0 dB gain
-4.0 dB gain
-5.0 dB gain
-6.0 dB gain
-7.0 dB gain
-8.0 dB gain
-9.0 dB gain
-10.0 dB gain
-11.0 dB gain
-12.0 dB gain
-13.0 dB gain
-14.0 dB gain
-15.0 dB gain
-16.0 dB gain
-17.0 dB gain
-18.0 dB gain
-19.0 dB gain
-20.0 dB gain
-21.0 dB gain
-22.0 dB gain
-23.0 dB gain
-24.0 dB gain
-25.0 dB gain
-26.0 dB gain
-27.0 dB gain
-28.0 dB gain
-29.0 dB gain
-30.0 dB gain
-31.0 dB gain
-32.0 dB gain
-33.0 dB gain
-34.0 dB gain
-35.0 dB gain
-36.0 dB gain
-37.0 dB gain
-38.0 dB gain
-39.0 dB gain
-40.0 dB gain
-41.0 dB gain
-42.0 dB gain
Def.
000000
STw5098
5.5
Control registers
Analog functions
CR#
(hex)
Description
D7
D6
D5
D4
D3
D2
D1
D0
Def.
CR17
(11h)
Mixer switches &
Mic Bias
MBIAS
MBIASPD
ADMIC
ADLIN
MIXMIC
MIXLIN
MIXDAC
MICLO
0000
0000
CR18
(12h)
Input switches
X
IN2VCM
LINMUTE
CR19
(13h)
Drivers control
Table 15.
Bits
VCML(1:0)
X
LINSEL(1:0)
MUTELO
MICMUTE
MICSEL(1:0)
0010
0100
LSLIM
LSSEL(1:0)
0101
1000
MUTEHP
CR17 description
Name
Value
CR17 description
Def.
1
0
Microphone Bias enabled (2.1V typ at MBIAS pin)
Microphone Bias disabled
0
1
0
MBIAS pin is pulled down when microphone bias is disabled
MBIAS pin is in high impedance state when microphone Bias is
disabled
0
ADMIC
1
0
Microphone preamplifiers are connected to AD path
Microphone preamplifiers are not connected to AD path
0
4
ADLIN
1
0
Line in preamplifiers are connected to AD path
Line in preamplifiers are not connected to AD path
0
3
MIXMIC
1
0
Microphone preamplifiers are connected to mixers
Microphone preamplifiers are not connected to mixers
0
2
MIXLIN
1
0
Line in preamplifiers are connected to mixers
Line in preamplifiers are not connected to mixers
0
1
MIXDAC
1
0
Stereo DAC path is connected to mixers
Stereo DAC path is not connected to mixers
0
0
MICLO
1
0
Microphone preamplifiers are connected to line out drivers
Mixers are connected to line out drivers
0
7
MBIAS
6
MBIASPD
5
Table 16.
Bits
CR18 description
Name
Value
CR18 description
Def.
6
IN2VCM
1
0
Unused analog input pins are biased to common mode voltage
Unused analog input pins are in high impedance state
0
5
LINMUTE
1
0
Line in preamplifiers are muted
Line in preamplifiers are not muted
1
00
01
10
11
Input pins connected to line in preamplifiers (if LINMUTE=0)
LINEIN
(LINEINL, LINEINR)
AUX1
(AUX1L, AUX1R)
AUX2
(AUX2LP-AUX2LN, AUX2RP-AUX2RN)
AUX3
(AUX3L, AUX3R)
00
4-3
LINSEL(1:0)
39/85
Control registers
Table 16.
Bits
2
1-0
Bits
CR18 description
Name
MICMUTE
MICSEL(1:0)
Table 17.
STw5098
Value
CR18 description
Def.
1
0
Microphone preamplifiers are muted
Microphone preamplifiers are not muted
1
00
01
10
11
Input pins connected to microphone preamplifiers (if MICMUTE=0)
MIC
(MICLP-MICLN, MICRP-MICRN)
AUX1
(AUX1L, AUX1R)
AUX2
(AUX2LP-AUX2LN, AUX2RP-AUX2RN)
AUX3
(AUX3L, AUX3R)
00
CR19 Description
Def.
CR19 description
Name
Value
00
01
10
11
Common mode voltage level for line out and headphones drivers
1.20 V
1.35 V (default)
1.50 V
1.65 V
01
7-6
VCML(1:0)
4
MUTELO
1
0
Line out drivers are muted
Line out drivers are not muted
1
3
MUTEHP
1
0
Headphones drivers (HP) are muted
Headphones drivers (HP) are not muted
1
1
0
EAR/LS driver gain is limited when VCCLS is above 4.2V typ
EAR/LS driver (LS) gain is not limited
0
00
01
10
11
Mute
Right
Left
Mono
driver
00
1EARLIM
2
2LSLIM
1EARSEL(1:0)
1-0
2LSSEL(1:0)
40/85
Loudspeaker driver (LS) is muted
Right channel mixer only connected to loudspeaker driver
Left channel mixer only connected to loudspeaker driver
(Left + Right)/2 channel mixers connected to loudspeaker
STw5098
5.6
Control registers
Digital audio interfaces master mode and clock generators
CR#
(hex)
Description
D7
D6
D5
D4
D3
D2
D1
D0
Def.
CR20
(14h)
DAOCK
frequency LSB
DAOCKF(7:0)
0000
0000
CR21
(15h)
DAOCK
frequency MSB
DAOCKF(15:8)
0000
0000
CR22
(16h)
DA clock
generator control
CR23
(17h)
ADOCK
frequency LSB
ADOCKF(7:0)
0000
0000
CR24
(18h)
ADOCK
frequency MSB
ADOCKF(15:8)
0000
0000
CR25
(19h)
AD clock
generator
control
Table 18.
Bits
X
X
X
X
DA
MASTGEN
DAMAST
AD
MASTGEN
ADMAST
END
OCK
ENA
DOCK
DAO
CK512
ADO
CK512
DAPCMF(1:0)
ADPCMF(1:0)
0000
0000
0000
0000
CR21-20 and CR24-23 description
Name CR21-20
Name CR24-23
Value
CR21-20 and CR24-23 Description
Def.
The following formulas can be used to obtain the value of K for the
desired FS or OCK respectively in the clock generator
K ( FS ) = round ⎛ 2
⎝
15-0
DAOCKF(15:0)
ADOCKF(15:0)
25
K ( OCK ) = round ⎛ 2
⎝
K
FS
--------------------------------------------------------------⎞
AMCK ⋅ MCKCOEFF⎠
25
OCK
------------------------------------------------------------------------------------⎞
AMCK ⋅ MCKCOEFF ⋅ OSR⎠
0000h
FS: Data rate (DA_SYNC or AD_SYNC frequency in master mode)
OCK: Oversampled clock frequency (DA_OCK or AD_OCK)
AMCK: Input master clock frequency
MCKCOEFF: See CR30 for definition
OSR: See bit 2 in CR22 and CR25
Note: CR21-20 and CR24-23 are meaningful in master mode only.
Table 19.
Bits
CR22 and CR25 description
Name CR22
(Name CR25)
Value
CR22 and CR25 description
Def.
5
DAMAST
(ADMAST)
1
0
DA (AD) Audio interface is in master mode (low impedance output)
DA (AD) Audio interface is in slave mode (high impedance input)
0
4
DAMASTGEN
(ADMASTGEN)
1
0
DA (AD) Master generator is enabled
DA (AD) Master generator is disabled
0
3
ENDAOCK
(ENADOCK)
1
0
DA_OCK (AD_OCK) output clock is enabled
DA_OCK (AD_OCK) output clock is disabled
0
41/85
Control registers
Table 19.
Bits
2
1-0
42/85
STw5098
CR22 and CR25 description
Name CR22
(Name CR25)
DAOCK512
(ADOCK512)
DAPCMF(1:0)
(ADPCMF(1:0))
Value
CR22 and CR25 description
Def.
0
0
Definition of DA_OSR (AD_OSR)
DA_OCK/DA_SYNC (AD_OCK/AD_SYNC) ratio in master mode is
512
da_ock/da_sync (ad_ock/ad_sync) ratio in master mode is 256
00
00
01
10
11
11
DA_CK/DA_SYNC (AD_CK/AD_SYNC) Ratio in PCM master mode
- 16 when CR26 DAWL=000 (CR27 ADWL=000)
- 32 when CR26 DAWL≠000 (CR27 ADWL≠000)
- 64
- 128
- 256 when CR22 DAOCK512=0 (CR25 ADOCK512=0)
- 512 when CR22 DAOCK512=1 (CR25 ADOCK512=1)
00
1
STw5098
5.7
Control registers
Digital audio interfaces
CR#
(hex)
Description
D7
D6
D5
D4
D3
D2
D1
D0
Def.
CR26
(1Ah)
DAC data IF
control
X
DAFORM(2:0)
DASPIM
DAWL(2:0)
0000
0000
CR27
(1Bh)
ADC data IF
control
ADRTOL
ADFORM2:0)
ADSPIM
ADWL(2:0)
0000
0000
CR28
(1Ch)
DAC&ADC data
IF control
AMCKINV
Table 20.
Bits
Name
DAFORM(2:0)
3
DASPIM
DAWL(2:0)
Table 21.
Bits
7
6-4
DASYNCP
DAMONO
ADCKP
AD
SYNCP
ADMONO
ADHIZ
0000
0000
CR26 description
6-4
2-0
DACKP
Value
000
001
010
011
100
111
1
0
000
001
010
011
100
CR26 Description
DA audio interface format selection
Delayed format (I2S compatible)
Left aligned format
Right aligned format
DSP format
SPI format
PCM format (uses left channel)
DA interface in SPI mode receives one word for both channels
DA interface in SPI mode receives two words
(alternated, left channel first)
DA interface word length
16 bit
18 bit
20 bit
24 bit
32 bit
Def.
000
0
000
CR27 description
Name
ADRTOL
ADFORM(2:0)
Value
1
0
000
001
010
011
100
111
CR27 description
AD right channel sent to PCM I/F (must set ENADCR=0 in CR1)
Normal operation
AD audio interface format selection
Delayed format (I2S compatible)
Left aligned format
Right aligned format
DSP format
SPI format
PCM format (sends out left channel)
Def.
0
000
43/85
Control registers
Table 21.
Bits
3
2-0
Bits
CR27 description (continued)
Name
ADSPIM
ADWL(2:0)
Table 22.
STw5098
Value
1
0
000
001
010
011
100
CR27 description
AD interface in SPI mode sends one channel (left)
AD interface in SPI mode sends two channels (alternated, left first)
AD interface word length
16 bit
18 bit
20 bit
24 bit
32 bit
Def.
0
000
CR28 description
Name
Value
CR28 description
Def.
7
AMCKINV
1
0
AMCK is inverted
AMCK is not inverted
0
6
DACKP
1
0
DA Bit clock pin (DA_CK) polarity is inverted
DA Bit clock pin (DA_CK) polarity is not inverted
0
1
0
DSP and PCM formats in DA interface
Non delayed format
Delayed format
1
0
Delayed, left-aligned, right-aligned and SPI formats in DA interface
DA sync pin (DA_SYNC) polarity is inverted
DA sync pin (DA_SYNC) polarity is not inverted
5
DASYNCP
0
1
4
3
2
0
0
Mono mode: (L+R)/2 from Audio Interface is used on both DAC
channels
Stereo mode
1
0
AD Bit clock pin (AD_CK) polarity is inverted
AD Bit clock pin (AD_CK) polarity is not inverted
0
1
0
DSP and PCM formats in AD interface
Non delayed format
Delayed format
1
0
Delayed, left-aligned, right-aligned and SPI formats in AD interface
DA sync pin (DA_SYNC) polarity is inverted
DA sync pin (DA_SYNC) polarity is not inverted
DAMONO
ADCKP
ADSYNCP
0
1
1
ADMONO
0
1
0
ADHIZ
0
44/85
Mono mode: (L+R)/2 from ADC is sent to both channels in the Audio
interface
Stereo mode
0
AD data pin (AD_DATA) is in high impedance state when no data is
available
AD data pin (AD_DATA) is forced to 0 when no data is available
0
STw5098
Control registers
5.8
Digital filters, software reset and master clock control
CR#
(hex)
Description
D7
D6
D5
D4
D3
D2
D1
D0
Def.
AD96K
ADNH
TXNH
0000
0000
CR29
(1Dh)
Digital filters
control
X
DAVOICE
DA96K
RXNH
ADVOICE
CR30
(1Eh)
Soft reset &
AMCK range
SWRES
X
X
X
AMCKSIN
Table 23.
Bits
CKRANGE(2:0)
0000
0000
CR29 description
Name
Value
CR29 description
Def.
6
DAVOICE
1
0
DA path voice RX filter is enabled (single channel, left used)
DA path voice filters are enabled
0
5
DA96K
1
0
DA path data rate is in the range 88 kHz to 96 kHz
DA path data rate is in the range 8 kHz to 48 kHz
0
4
RXNH
1
0
DA path high pass voice RX filter is disabled
DA path high pass voice RX filter is enabled (300Hz @ 8kHz rate)
0
3
ADVOICE
1
0
AD path voice TX filter is enabled (single channel, left used)
AD path audio filters are enabled
0
2
AD96K
1
0
AD path data rate is in the range 88 kHz to 96 kHz
AD path data rate is in the range 8 kHz to 48 kHz
0
1
ADNH
1
0
AD path audio DC filter is disabled
AD path audio DC filter is enabled
0
0
TXNH
1
0
AD path high pass voice TX filter is disabled
AD path high pass voice TX filter is enabled (300Hz @ 8kHz rate)
0
Table 24.
Bits
CR30 description
Name
Value
CR30 description
Def.
7
SWRES
1
0
Software reset: All registers content is reset to the default value
Control Register content is left unchanged
0
3
AMCKSIN
1
0
Signal at AMCK pin is a sinusoid
Signal at AMCK pin is a square wave
0
2-0
CKRANGE(2:0)
000
001
010
011
100
101
AMCK range
4.0 MHz to 6.0 MHz
6.0 MHz to 8.0 MHz
8.0 MHz to 12.0 MHz
12.0 MHz to 16.0 MHz
16.0 MHz to 24.0 MHz
24.0 MHz to 32.0 MHz
MCKCOEFF
8.0
6.0
4.0
3.0
2.0
1.5
000
45/85
Control registers
5.9
STw5098
Interrupt control and control interface SPI out mode
CR#
(hex)
Description
D7
D6
D5
CR31
(1Fh)
Interrupt mask
VLSHEN
PUSH
BEN
CR32
(20h)
Interrupt status
VLSH
PUSHB
HSDET
CR33
(21h)
Misc. control
x
X
SPIOHIZ
Table 25.
Bits
D4
HSDETEN VLSHMSK
VLSHEV
D3
D2
D1
D0
Def.
PUSH
BMSK
HSDET
MSK
OVFMSK
PORMSK
0000
0000
OVFEV
POREV
0000
0000
OVFDA
OVFAD
0000
0000
PUSHBEV HSDETEV
SPIOSEL(1:0)
IRQCMOS
CR31 description
Name
Value
CR31description
Def.
7
VLSHEN
1
0
VLSH status can be seen at IRQ output
VLSH status is masked
0
6
PUSHBEN
1
0
PUSHB status can be seen at IRQ output
PUSHB status is masked
0
5
HSDETEN
1
0
HSDET status can be seen at IRQ output
HSDET status is masked
0
4
VLSHMSK
1
0
VLSH event can be seen at IRQ output
VLSH event is masked
0
3
PUSHBMSK
1
0
PUSHB event can be seen at IRQ output
PUSHB event is masked
0
2
HSDETMSK
1
0
HSDET event can be seen at IRQ output
HSDET event is masked
0
1
OVFMSK
1
0
OVF event can be seen at IRQ output
OVF event is masked
0
0
PORMSK
1
0
POR event can be seen at IRQ output
POR event is masked
0
Note:
Value at IRQ pin is:
⎧
IRQ = ⎨ (1 or Z) when (CR31 & CR32) = 00 hex
0
when (CR31 & CR32) ≠ 00 hex
⎩
Table 26.
Bits
CR32 description
Name
Read
only
CR32 description
Def.
7
VLSH*
1
0
VCCLS is above 4.2 V
VCCLS is below 4.0 V
0
6
PUSHB*
1
0
Headset Button is pressed
Headset Button is released
0
5
HSDET*
1
0
Headset Connector is inserted
Headset Connector is not inserted
0
46/85
STw5098
Table 26.
Bits
Control registers
CR32 description (continued)
Name
Read
only
CR32 description
Def.
4
VLSHEV
1
0
VLSH bit has changed
VLSH bit has not changed
0
3
PUSHBEV
1
0
Headset Button Status has changed
Headset Button Status has not changed
0
2
HSDETEV
1
0
Headset Connector Status has changed
Headset Connector Status has not changed
0
1
OVFEV
1
0
An Audio Data overflow has occurred in DSP
No Audio Data overflow has occurred in DSP
0
0
POREV
1
0
Device was reset by power-on-reset
Device was not reset by power-on-reset
0
Note: content of bits 4 to 0 in CR32 is cleared after reading, while it is left unchanged if accessed for writing.
*Bits 7 to 5 represent the status when the Control register is read, not when the event occurred.
Table 27.
Bits
CR33 description
Name
Val.
1
5
4-3
Def.
0
0
SPI control interface out pin is set to high impedance state when
inactive
SPI control interface out pin is set to zero when inactive
00
01
10
11
Out pin selection for SPI control interface
No output. Control registers cannot be read in SPI mode
SPI output sent to IRQ pin
SPI output sent to DA_OCK pin
SPI output sent to AD_OCK pin
00
SPIOHIZ
SPIOSEL(1:0)
CR33 description
2
IRQCMOS
1
0
IRQ interrupt request pin is set to CMOS (active low)
IRQ interrupt request pin is set to pull down
0
1
OVFDA
1
0
An overflow (saturation) occurred in DA path
No overflow occurred in DA channel
0
0
OVFAD
1
0
An overflow (saturation) occurred in AD path
No overflow occurred in AD channel
0
Note: content of bits 1 to 0 in CR33 is cleared after reading, while it is left unchanged if accessed for writing.
47/85
Control registers
5.10
AGC
CR#
(hex)
Description
CR34
(22h)
AGC
attack/decay
coeff.
CR35
(23h)
AGC control
Table 28.
Bits
STw5098
D7
D6
D5
D4
D3
AGCATT(3:0)
X
ENAG
CLIN
ENAG
CMIC
AGC
RANGE
D2
D1
D0
Def.
AGCDEC(3:0)
0000
0000
AGCLEV(3:0)
0000
0000
CR 34 description
Name
Value
CR 34 description
Def.
AGC attack time constant; FS=AD data rate
7-4
AGCATT(3:0)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
Audio filter in AD path
4096 / FS
2048 / FS
1365 / FS
1024 / FS
683 / FS
512 / FS
341 / FS
256 / FS
171 / FS
128 / FS
85 / FS
64 / FS
43 / FS
32 / FS
Voice filter in AD path
8192 / FS
4096 / FS
2731 / FS
2048 / FS
1365 / FS
1024 / FS
683 / FS
512 / FS
341 / FS
256 / FS
171 / FS
128 / FS
85 / FS
64 / FS
0000
AGC decay time constant; FS=AD data rate
3-0
48/85
AGCDEC(3:0)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Audio filter in AD path
65536 / FS
32768 / FS
21845 / FS
16384 / FS
10923 / FS
8192 / FS
5461 / FS
4096 / FS
2731 / FS
2048 / FS
1365 / FS
1024 / FS
683 / FS
512 / FS
341 / FS
256 / FS
Voice filter in AD path
131072 / FS
65536 / FS
43691 / FS
32768 / FS
21845 / FS
16384 / FS
10923 / FS
8192 / FS
5461 / FS
4096 / FS
2731 / FS
2048 / FS
1365 / FS
1024 / FS
683 / FS
512 / FS
0000
STw5098
Table 29.
Bits
Control registers
CR 35 description
Name
Value
CR35 description
Def.
6
ENAGCLIN
1
0
AGC control on AD path acts on Line In Gain
AGC control on AD path does not act on Line In Gain
0
5
ENAGCMIC
1
0
AGC control on AD path acts on Mic Gain
AGC control on AD path does not act on Mic Gain
0
4
AGCRANGE
1
0
AGC action range is -21.0 dB to +21.0 dB
AGC action range is -10.5 dB to +10.5 dB
0
3-0
AGCLEV(3:0)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
AGC requested output level
-30.0 dB gain
-30.0 dB gain
-27.0 dB gain
-24.0 dB gain
-21.0 dB gain
-18.0 dB gain
-15.0 dB gain
-12.0 dB gain
-9.0 dB gain
-6.0 dB gain
0000
49/85
Control interface and master clock
6
STw5098
Control interface and master clock
Unless specified, the following description applies to both entities.
6.1
Control interface I2C mode
Figure 5.
Control interface I2C format
ACK
ACK
DEVICE ADDRESS REG n ADDRESS
0 0 1 1 0 1 AS0
START
WRITE
SINGLE BYTE
ACK
REG n DATA IN
STOP
WRITE
MULTI BYTE
ACK
ACK
ACK
ACK
ACK
DEVICE ADDRESS REG n ADDRESS REG n DATA IN
REG n+m DATA IN
0 0 1 1 0 1 AS0
START
m+1 data bytes
STOP
CURRENT ADDR
READ
SINGLE BYTE
ACK
NO ACK
DEVICE ADDRESSCurrent REG DATA OUT
0 0 1 1 0 1 AS1
START
STOP
CURRENT ADDR
READ
MULTI BYTE
ACK
ACK
ACK
NO ACK
DEVICE ADDRESSCurrent REG DATA OUT
Curr REG+m DATA OUT
0 0 1 1 0 1 AS1
m+1 data bytes
START
STOP
RANDOM ADDR
READ
SINGLE BYTE
ACK
ACK
ACK
NO ACK
DEVICE ADDRESS REG n ADDRESS
DEVICE ADDRESS REG n DATA OUT
0 0 1 1 0 1 AS0
0 0 1 1 0 1 AS1
START
START
STOP
RANDOM ADDR
READ
MULTI BYTE
ACK
ACK ACK
ACK
ACK
NO ACK
DEVICE ADDRESS REG n ADDRESS
DEVICE ADDRESS REG n DATA OUT
REG n+m DATA OUT
0 0 1 1 0 1 AS0
0 0 1 1 0 1 AS1
START
START
m+1 data bytes
STOP
Note:
CMOD pin tied to GND
Figure 6.
Control interface: I2C format timing
SDA
tBUF
tHD
(STA)
tLOW
tHD
(DAT)
tHIGH
tSU
(DAT)
tSU
(STA)
tHD
(STA)
tSU
(STO)
SCLK
tR
P
S
P = STOP
S = START
Sr = START repeated
50/85
tF
Sr
P
STw5098
Table 30.
Symbol
Control interface and master clock
Control interface timing with I²C format
Parameter
Test conditions
Min.
Typ.
Max.
Unit
400
kHz
fSCL
Clock frequency
tHIGH
Clock pulse width high
600
ns
tLOW
Clock pulse width low
1300
ns
tR
SDA and SCLK rise time
1000
ns
tF
SDA and SCLK fall time
300
ns
tHD:STA
Start condition hold time
600
ns
tSU:STA
Start condition setup time
600
ns
tHD:DAT
Data input hold time
0
ns
tSU:DAT
Data input setup time
250
ns
tSU:STO
Stop condition setup time
600
ns
tBUF
Bus free time
1300
ns
6.2
Control interface SPI mode
Figure 7.
Control interface SPI format(a)
CSB
SCLK
SDIN
W/R A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
8 bit Address
SDO
SPIOHIZ=1
D4
D3
D2
D1
D0
D2
D1
D0
8 bit Data
D7
D6
D5
D4
D3
8 bit Data
a. CMOD pin tied to VCCIO; SDO pin position selected with bits SPIOSEL in CR33.
51/85
Control interface and master clock
Figure 8.
STw5098
Control interface: SPI format timing
tHICS
CSB
tPSCK
tSCSF
tLSCK
SCLK
0
tSDI
SDIN
tHCS
8
15
tHDI
W/R
D7
tDDOF
SDO
SPIOHIZ=1
SPIOHIZ=0
Table 31.
Symbol
tSCSR
tHSCK
D0
tDDO
tDDOL
D7
D0
Control interface signal timing with SPI format
Parameter
Test conditions
Min.
Typ.
Max.
Unit
tHICS
CSB pulse width high
80
ns
tSCSR
Setup time CSB rising
edge to SCLK rising edge
20
ns
tSCSF
Setup time CSB falling
edge to SCLK rising edge
20
ns
tHCS
Hold time CSB rising edge
from SCLK rising edge
20
ns
tSDI
Setup time SDIN to SCLK
rising edge
20
ns
tHDI
Hold time SDIN from SCLK
rising edge
20
ns
tDDOF
SDO first Delay time from
SCLK falling edge
30
ns
tDDO
SDO Delay time from
SCLK falling edge
20
ns
tDDOL
SDO Delay time from CSB
rising edge
30
ns
tPSCK
Period of SCK
tHSCK
SCK pulse width high
tLSCK
SCK pulse width low
52/85
100
ns
Measured from VIH to VIH
40
ns
Measured from VIL to VIL
40
ns
STw5098
Control interface and master clock
6.3
Master clock timing
Table 32.
AMCK timing
Symbol
tCKDC
Parameter
AMCK duty cycle
AMCK range
4 MHz-8 MHz
8 MHz-32 MHz
Min.
45
40
Typ.
Max.
Unit
55
60
%
%
53/85
Audio interfaces
7
STw5098
Audio interfaces
Information included in the following section is valid for both entities.
Figure 9.
Audio interfaces formats: delayed, left and right justified
I2S format (delayed) with default polarity settings, ADHIZ=0
DA_SYNC/
AD_SYNC
DA_CK/
AD_CK
1 AD_CK/DA_CK
1 AD_CK/DA_CK
DA_DATA
1
2
n-1
n
MSB n-bit word Left data LSB
1
2
n-1
n
MSB n-bit word Right data LSB
AD_DATA
1
2
n-1
n
MSB n-bit word Left data LSB
1
2
n-1
n
MSB n-bit word Right data LSB
Left justified format with default polarity settings, ADHIZ=0
DA_SYNC/
AD_SYNC
DA_CK/
AD_CK
DA_DATA
1
2
n-1
n
MSB n-bit word Left data LSB
1
2
n-1
n
MSB n-bit word Right data LSB
AD_DATA
1
2
n-1
n
MSB n-bit word Left data LSB
1
2
n-1
n
MSB n-bit word Right data LSB
Right justified format with default polarity settings
32 AD_CK/DA_CK
32 AD_CK/DA_CK
DA_SYNC/
AD_SYNC
DA_CK/
AD_CK
54/85
DA_DATA
1
2
n-1
n
MSB n-bit word Left data LSB
1
2
n-1
n
MSB n-bit word Right data LSB
AD_DATA
1
2
n-1
n
MSB n-bit word Left data LSB
1
2
n-1
n
MSB n-bit word Right data LSB
STw5098
Audio interfaces
Figure 10. Audio interfaces formats: DSP, SPI and PCM
DSP format delayed and non-delayed (default AD_CK/DA_CK polarity, ADHIZ=0)
DA_SYNC/
AD_SYNC
{
SYNCP=0
SYNCP=1
DA_CK/
AD_CK
DA_DATA
1
2
n-1
n
1
2
n-1
n
MSB n-bit word Left data LSB MSB n-bit word Right data LSB
AD_DATA
1
2
n-1
n
1
2
n-1
n
MSB n-bit word Left data LSB MSB n-bit word Right data LSB
SPI format (slave only) (default AD_CK/DA_CK polarity, ADHIZ=1 - Stereo or Mono)
DA_SYNC/
AD_SYNC
DA_CK/
AD_CK
DA_DATA
x
AD_DATA
1
MSB
2
3
n-1
n
n-bit word Left/Mono data LSB
1
MSB
2
3
n-1
n
n-bit word Left/Mono data LSB
1
2
3
MSB n-bit word Right/Mono data
High impedance
x
1
2
3
MSB n-bit word Right/Mono data
PCM format (default AD_CK/DA_CK polarity, ADHIZ=1)
DA_SYNC/
AD_SYNC
{
SYNCP=0
SYNCP=1
DA_CK/
AD_CK
DA_DATA
1
MSB
2
3
n-1
n
LSB
n-bit word Mono data
AD_DATA
1
MSB
2
3
n-1 n
LSB
n-bit word Mono data
1
MSB
High impedance
1
MSB
55/85
Audio interfaces
STw5098
Figure 11. Audio interface timings: master mode
DA_SYNC/
AD_SYNC
tDSY
DA_CK/
AD_CK
{
CKP=0
CKP=1
tSDDA
tHDDA
DA_DATA
tDAD
AD_DATA
PCM format only
tDAD
tDADZ
ADHIZ=1
ADHIZ=1
ADHIZ=0
ADHIZ=0
tDAD
AD_DATA
All other formats
ADHIZ=1
ADHIZ=1
ADHIZ=0
ADHIZ=0
Figure 12. Audio interface timing: slave mode
DA_SYNC/
AD_SYNC
tHSY
DA_CK/
AD_CK
{
tSSY
CKP=0
tHCK
tLCK
CKP=1
tSDDA
tHDDA
tPCK
DA_DATA
tDADST
AD_DATA
PCM format
tDAD
tDADZ
ADHIZ=1
ADHIZ=1
ADHIZ=0
ADHIZ=0
tDAD
AD_DATA
All other formats
ADHIZ=1
ADHIZ=1
ADHIZ=0
ADHIZ=0
tDAD
56/85
STw5098
Table 33.
Symbol
Audio interfaces
Audio interface signal timings
Parameter
Test conditions
Min.
Typ.
Max.
Unit
10
ns
tDSY
Delay of
AD_SYNC/DA_SYNC
Master Mode
edge from AD_CK/DA_CK
active edge
tSDDA
Setup time DA_DATA to
DA_CK active edge
10
ns
tHDDA
Hold time DA_DATA from
DA_CK active edge
10
ns
tDAD
Delay of AD_DATA edge
from AD_CK active edge
30
ns
tDADST
Delay of the first AD_DATA
AD_SYNC active edge comes
edge from AD_SYNC
after AD_CK active edge
active edge
30
ns
tDADZ
Delay of AD_DATA high
impedance from
AD_SYNC inactive edge
PCM format
10
50
ns
tSSY
Setup time
AD_SYNC/DA_SYNC to
AD_CK/DA_CK active
edge
Slave Mode
20
ns
tHSY
Hold time
AD_SYNC/DA_SYNC from
Slave Mode
AD_CK/DA_CK active
edge
20
ns
tPCK
Period of AD_CK/DA_CK
Slave Mode
100
ns
tHCK
AD_CK/DA_CK pulse
width high
Measured from VIH to VIH
40
ns
tLCK
AD_CK/DA_CK pulse
width low
Measured from VIL to VIL
40
ns
57/85
Timing specifications
8
STw5098
Timing specifications
Information included in this section is valid for both entities.
Unless otherwise specified, VCCIO = 1.71V to 2.7V, Tamb = -30°C to 85°C, max capacitive
load 20 pF; typical characteristics are specified at VCCIO = 2.4 V, Tamb = 25 °C; all signals
are referenced to GND, see Note below figure for timing definitions.
Figure 13. A.C. testing input-output waveform
Input/output
0.8²VCCIO
0.7²VCCIO
0.7²VCCIO
TEST POINTS
0.2²VCCIO
0.3²VCCIO
0.3²VCCIO
AC Testing: inputs are driven at 0.8•VCCIO for a logic ‘1’ and 0.2•VCCIO for a logic ‘0’.
Timing measurements are made at 0.7•VCCIO for a logic ‘1’ and 0.3•VCCIO for a logic ‘0’.
Note:
A signal is valid if it is above VIH or below VIL and invalid if it is between VIL and VIH. For the
purpose of this specification the following conditions apply (see Figure 13 above):
a) All input signal are defined as: VIL = 0.2• VCCIO, VIH = 0.8• VCCIO, tR < 10ns, tF < 10ns.
b) Delay times are measured from the inputs signal valid to the output signal valid.
c) Setup times are measured from the data input valid to the clock input invalid.
d) Hold times are measured from the clock signal valid to the data input invalid.
Note:
All timing specifications subject to change.
58/85
STw5098
Operative ranges
9
Operative ranges
9.1
Absolute maximum ratings
Table 34.
Absolute maximum ratings
Parameter
Value
Unit
VCC or VCCIO to GND
-0.5 to 3.6
V
VCCA or VCCP to GND
-0.5 to 5
V
VCCLS to GND
-0.5 to 7
V
GND-0.5 to VCCA+0.5
V
Maximum power delivered to the load from LSP/N
500
mW
Peak current at HPR,HPL
100
mA
Current at VCCP, VCCLS, GNDP
350
mA
Current at any digital output
50
mA
GND-0.5 to VCCIO+0.5
V
-65 to 150
°C
-30 to 85
°C
-2 to +2
-500 to +500
kV
V
Voltage at analog inputs (VCCA ≤3.3V)
Voltage at any digital input (VCCIO ≤2.7V); limited at ± 50mA
Storage temperature range
Operating temperature
range(1)
Electrostatic discharge voltage (Vesd)
Human body model(2)
Charge device model(3)
1. in some operating conditions the temperature can be limited to 70 °C. See loudspeaker driver description from Section 4.10
for details.
2. HBM tests have been performed in compliance with JESD22-A114-B and ESD STM 5.1-2001.HBM
3. CDM tests have been performed in compliance with CDM ANSI-ESDSTM5.3.1-1999
9.2
Operative supply voltage
Table 35.
Operative supply voltage
Symbol
Parameter
Condition
Min.
Max.
Unit
1.71
2.7
V
VCC
Digital supply
VCCA
Analog supply
Note: VCCA ≥ VCC
A24V=0 (bit 1 in CR0)
A24V=1 (bit 1 in CR0)
2.7
2.4
3.3
2.7
V
V
VCCIO
Digital I/O supply
D12V=0 (bit 0 in CR0)
D12V=1 (bit 0 in CR0)
1.71
1.2
VCC
1.8
V
V
VCCP
Stereo power drivers supply
VCCA
3.3
V
VCCLS
Mono power driver supply
VCCA
5.5
V
VG
Single supply voltage range
2.4
2.7
V
VCC=VCCA=VCCIO=VCCP=VCCLS
A24V=1 (bit 1 in CR0)
59/85
Operative ranges
9.3
STw5098
Power dissipation
Unless otherwise specified, VCCP = VCCLS = VCCA = 2.7V to 3.3V, VCCIO = VCC = 1.71V to
2.7V, Tamb = -30°C to 85°C, all analog outputs not loaded; typical characteristics are
specified at VCCIO = VCC = 1.8V, VCCP = VCCLS = VCCA = 2.7V, Tamb = 25°C.
Table 36.
Power dissipation
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
0.8
5.8
µW
µW
Stereo ADC power
52.6
mW
PDA
Stereo DAC power
46.6
mW
PDAAD
Stereo ADC+DAC power
93.8
mW
PAA
Stereo Analog Path power
27.6
mW
POFF
Power Down Dissipation
PAD
9.4
No Master Clock
AMCK=13MHz
Typical power dissipation by entity
Tamb = 25°C; Analog Supply: VCCP = VCCLS = VCCA = 2.7V;
digital supply: VCCIO = VCC = 1.8V.
Full scale signal in every path, 20kΩ load at analog outputs.
No master clock
Table 37.
N.
Typical power dissipation, no master clock
Function
CR0-CR2
setting
Other settings
Supply
Current
Power
Analog:
Digital:
Total:
0.02 µA
0.20 µA
0.05 µW
0.36 µW
0.41 µW
1
Power Down
CR0=0x00
CR1=0x00
CR2=0x00
2
Stereo analog path
(Mic-LO)
CR0=0xD0
CR1=0x0C
CR2=0xC0
MICLO=1
MICSEL=2
Analog:
Digital:
Total:
4.3 mA
2.0 µA
11.6 mW
0.0 mW
11.6 mW
3
Stereo analog path
(Mic-Mixer-LO)
CR0=0xD0;
CR1=0x0C;
CR2=0xC3
MIXMIC=1
MICSEL=2
Analog:
Digital:
Total:
5.4 mA
2.0 µA
14.6 mW
0.0 mW
14.6 mW
60/85
STw5098
Operative ranges
Master clock AMCK = 13 MHz
Table 38.
N.
Typical power dissipation with master clock AMCK = 13 MHz
Function
CR0-CR2
setting
Other settings
Supply
Current
Power
Analog:
Digital:
Total:
0.02 µA
2.20 µA
0.05 µW
3.96 µW
4.01 µW
Power Down
CR0=0x00
CR1=0x00
CR2=0x00
5
Stereo ADC
CR0=0xE8
CR1=0xCC
CR2=0x00
MICSEL=1
ADMIC=1
Analog:
Digital:
Total:
7.9 mA
2.8 mA
21.3 mW
5.0 mW
26.3 mW
6
Stereo DAC
CR0=0xE8
CR1=0x30
CR2=0x33
MIXDAC=1
Analog:
Digital:
Total:
6.1 mA
3.8 mA
16.5 mW
6.8 mW
23.3 mW
7
Stereo analog path
(Mic-LO)
CR0=0xE8
CR1=0x0C
CR2=0xC0
MICLO=1
MICSEL=2
Analog:
Digital:
Total:
4.8 mA
0.8 mA
13.0 mW
1.4 mW
13.8 mW
8
Stereo ADC
Stereo DAC
CR0=0xE8
CR1=0xFC
CR2=0x33
MICSEL=2
ADMIC=1
MIXDAC=1
Analog:
Digital:
Total:
13.5 mA
5.8 mA
36.5 mW
10.4 mW
46.9 mW
9
Stereo ADC
Stereo DAC
Stereo analog path
CR0=0xE8
CR1=0xFF
CR2=0xF3
LINSEL=2; MICSEL=2
ADLIN=1;MIXDAC=1
MICLO=1
Analog:
Digital:
Total:
15.2 mA
5.8 mA
41.0 mW
10.4 mW
51.4 mW
Voice TX+RX
CR0=0xE8
CR1=0xA8
CR2=0x06
MICSEL=2;
LSMODE=2
ADMIC=1 MIXDAC=1
ADVOICE=1
DAVOICE=1
VCCA,VCCP:
VCCLS:
Digital
Total:
6.8 mA
1.3 mA
2.5 mA
18.4 mW
5.5 mW
4.5 mW
28.4 mW
4
10
61/85
Electrical characteristics
10
STw5098
Electrical characteristics
Unless otherwise specified, VCCIO = 1.71V to 2.7V, Tamb = -30°C to 85°C; typical
characteristic are specified at VCCIO = 2.0V, Tamb = 25°C; all signals are referenced to GND.
10.1
Digital interfaces
Table 39.
Digital interfaces specifications
Symbol
Parameter
VIL
Input low voltage
VIH
Input high voltage
VOL
Output low voltage
VOH
Output high voltage
Test conditions
Min.
Typ.
All digital inputs
DC
AC
All digital inputs,
DC 0.7•VCCIO
AC 0.8•VCCIO
All digital outputs
IL = 10µA
IL = 2µA
All digital outputs
IL = 10µA VCCIO-0.1
IL = 2µA VCCIO-0.4
Max.
Unit
0.3•VCCIO
0.2•VCCIO
V
V
V
V
0.1
0.4
V
V
V
V
IIL
Input low current
Any digital input,
GND < VIN < VIL
-1
1
µA
IIH
Input high current
Any digital input,
VIH < VIN < VCCIO
-1
1
µA
IOZ
Output current in
high impedance
(Tristate)
Tristate outputs
-1
1
µA
Max.
Unit
Note:
See Figure 13: A.C. testing input-output waveform on page 58.
10.2
AMCK with sinusoid input
Table 40.
AMCK with sinusoid input specifications
Symbol
Parameter
Test conditions
Min.
CAMCK
Minimum External
Capacitance
AMCKSIN=1, see CR30
100
VAMCK
AMCK sinusoidal voltage
swing
AMCKSIN=1, see CR30
0.5
62/85
Typ.
pF
VCCIO
VPP
STw5098
10.3
Electrical characteristics
Analog interfaces
Information below is for each entity.
Table 41.
Analog interface specifications
Symbol
Parameter
Test conditions
GND< VMIC< VCCA
Min.
IMIC
MIC input leakage
RMIC
MIC input resistance
30
RLIN
Line in input resistance
30
RLHP
Headphones (HP) drivers
load resistance
HPL, HPR to GNDP or
VCMHP
RLEAR
Earphone (EAR) drivers
load resistance
RLLS
Typ.
-100
Max.
Unit
+100
µA
50
kΩ
kΩ
14.4
16/32
Ω
1 EARP to 1EARN
30
32
Ω
Loudspeaker (LS) drivers
load resistance
2LSP to 2LSN
6.4
8
Ω
CLHP
Headphones (HP) drivers
load capacitance
HPL, HPR to GNDP or
VCMHP
50
50*
pF
nF
CLEAR
Earphone (EAR) drivers
load capacitance
1 EARP to 1EARN
50
50*
pF
nF
CLLS
Loudspeaker (LS) drivers
load capacitance
2LSP to 2LSN
50
50*
pF
nF
VOFFLS
Differential offset voltage
at 2LSP, 2LSN
RL = 50Ω
-50
+50
mV
VOFFEAR
Differential offset voltage
at 1EARP, 1EARN
RL = 50Ω
-50
+50
mV
RLOL
Line out (OL) diff./singleended driver load
resistance
OLP/ORP to OLN/ORN or
OLP/ORP to GND
(decoupled)
1
kΩ
* with series resistor
63/85
Electrical characteristics
10.4
STw5098
Headset plug-in and push-button detector
Information below is for each entity.
Table 42.
Symbol
Headset plug-in and push-button detector specifications
Parameter
Test conditions
HDVL
Plug-in detected
Voltage at HDET
HDVH
Plug-in undetected
Voltage at HDET
HDH
Plug-in detector hysteresis
PBVL
Push-button pressed
Voltage at HDET
PBVH
Push-button released
Voltage at HDET
PBD
Push-button de-bounce
time
10.5
Min.
Typ.
Max.
Unit
VCCA-1
V
VCCA-0.5
V
100
mV
0.5
V
1
V
15
50
ms
Microphone bias
Information below is for each entity.
Table 43.
Symbol
Microphone bias specifications
Parameter
VMBIAS
MBIAS output
voltage
IMBIAS
MBIAS output
current
RMBIAS
MBIAS output load
CMBIAS
MBIAS output
capacitance
PSRMB4
PSRMB20
MBIAS power
supply rejection
Test conditions
Unit
1.95
2.1
2.25
V
1.1
mA
kΩ
150
f<4kHz
f<20kHz
Table 44.
Power supply rejection ratio specifications
Test conditions
60
50
Min.
pF
dB
dB
Typ.
Max.
Unit
Each output (LSP, LSN)
f<20kHz
f<200kHz
65
47
dB
dB
PSRR VCCP
Headphones f<20kHz
Line out single ended f<20kHz
Line out differential f<20kHz
65
65
65
dB
dB
dB
PSRR VCCA
Mic input f<20kHz
Line In f<20kHz
50
50
dB
dB
PSRL20
PSRL200
PSRR VCCLS
PSRPH
PSRPOS
PSRPOD
PSRAM
PSRAL
64/85
Max.
3.5
Power supply rejection ratio
Parameter
Typ.
From MBIAS to ground
10.6
Symbol
Min.
STw5098
10.7
Electrical characteristics
LS and EAR gain limiter
Information below is for each entity.
Table 45.
Symbol
LS and EAR gain limiter
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VLSLIMH
High voltage at VCCLS
(VLSH=1)
VCCLS raising
4.2
V
VLSLIML
Low voltage at VCCLS
(VLSH=0)
VCCLS falling
4.0
V
VLSLIMD
VCCLS Hysteresis
200
mV
Note: See CR32 for VLSH definition. See Loudspeaker driver description in Section 4.10 for details.
65/85
Analog input/output operative ranges
11
STw5098
Analog input/output operative ranges
Information included in this section applies to both entities.
11.1
Analog levels
Table 46.
Reference full scale analog levels
Symbol
11.2
Parameter
Test conditions
Min.
Typ.
Max.
Unit
0dBFS level
2.7V < VCCA < 3.3V
12
4
dBVpp
Vpp
0dBFS level low voltage
mode
2.4V < VCCA < 2.7V
10
3.18
dBVpp
Vpp
Microphone input levels
Analog supply range: 2.7 V < VCCA < 3.3 V
Table 47.
Symbol
Microphone input levels, absolute levels at pins connected to preamplifiers
Parameter
Test conditions
Min.
Typ.
Max.
Unit
707
2
-6
mVRMS
Vpp
dBFS
MIC gain > 6dB
− (MIC_Gain)
dBFS
MIC gain = 0dB
1.41
4
0
mVRMS
Vpp
dBFS
− (MIC_Gain)
dBFS
Overload level, single
ended
MIC gain = 0 to 6dB
Overload level, single
ended, versus MIC gain
Overload level, differential
Overload level, differential,
MIC gain > 0dB
versus MIC gain
Note: When 2.4 V < VCCA < 2.7 V, voltage values are reduced by 2dB.
Table 48.
Symbol
Microphone input levels, absolute levels at pins connected to the line-in amplifiers
Parameter
Test conditions
Overload level, single
ended
Line in gain from −20dB to 6dB
Overload level (single
ended) versus line in gain
Line in gain > 6dB
Overload level (differential) Line in gain from −20dB to 0dB
66/85
Min.
Typ.
Max.
Unit
707
2
-6
mVRMS
Vpp
dBFS
− (Line_In_Gain)
dBFS
1.41
4
0
mVRMS
Vpp
dBFS
STw5098
Table 48.
Symbol
Analog input/output operative ranges
Microphone input levels, absolute levels at pins connected to the line-in amplifiers
Parameter
Test conditions
Min.
Overload level (differential)
Line in gain > 0dB
versus line in gain
Typ.
Max.
− (Line_In_Gain)
Unit
dBFS
Note: When 2.4 V < VCCA < 2.7 V, the values are reduced by 2dB
11.3
Line output levels
Analog supply range: 2.7 V < VCCA < 3.3 V
Table 49.
Symbol
Absolute levels at OLP/OLN, ORP/ORN
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Output level, single ended
0 dB gain
Full scale digital input
707
2
-6
mVRMS
Vpp
dBFS
Output level, differential
0 dB gain
Full scale digital input
1.41
4
0
mVRMS
Vpp
dBFS
Note: When 2.4 V < VCCA < 2.7 V, the values are reduced by 2dB
11.4
Power output levels HP
Analog supply range: 2.7 V < VCCA < 3.3 V
Table 50.
Symbol
Absolute levels at HPL - HPR
Parameter
Test conditions
Output level
-6dB gain
Full scale digital input
Max output power(1)
16 Ω load
VCCP > 3.2 V
Min.
Typ.
707
2
-6
40
Max.
Unit
mVRMS
Vpp
dBFS
mW
1. In some operating conditions the maximum output power can be limited. See “Section 9.1: Absolute maximum ratings” and
“loudspeaker driver” description from Section 4.10: Analog output drivers for details.
Note: When 2.4 V < VCCA < 2.7 V, the values are reduced by 2dB
11.5
Power output levels LS and EAR
Analog supply range: 2.7 V < VCCA < 3.3 V
67/85
Analog input/output operative ranges
Table 51.
Symbol
STw5098
Absolute levels at 1EARP-1EARN and 2LSP - 2LSN
Parameter
Test conditions
Min.
Typ.
1.41
4
0
Max.
Unit
VRMS
Vpp
dBFS
Output level
0 dB gain
Full scale digital input
Max EAR output power
32 Ω load
VCCLS > 4V
125
mW
Max LS output power(1)
8 Ω load
VCCLS > 4V
500
mW
1. In some operating conditions the maximum output power can be limited. See “Section 9.1: Absolute maximum ratings” and
“loudspeaker driver” description from Section 4.10: Analog output drivers for details.
Note: When 2.4 V < VCCA < 2.7 V, the values are reduced by 2dB
68/85
STw5098
12
Stereo audio ADC specifications
Stereo audio ADC specifications
Information included in this section applies to both entities. Typical measures at
VCCA=VCCP=VCCLS=2.7V; VCCIO=VCC=1.8 V; Tamb=25° C;13 MHz AMCK
Table 52.
Symbol
ADN
Stereo audio ADC specifications
Parameter
Test conditions
Min.
Typ.
Resolution
ADDRM
ADDRLI
Dynamic range
20Hz to 20kHz, A-weighted
Measured at -60dBFS
MIC input, 21dB gain
Line-In, 0dB gain
ADSNA
ADSN
Signal to noise ratio
Max level at MIC input, 21dB gain
A-weighted
Unweighted (20 Hz to 20 kHz)
87
89
Max.
Unit
20
Bits
91
93
dB
dB
90
86
dB
dB
37
3.3
1.9
30
7.5
µV
µV
µV
µV
µV
A-weighted
Input referred ADC
noise
ADTHD
ADfPB
ADfSB
ADtgd
Mic input 0dB gain
Mic input 21dB gain
Mic input 39dB gain
Line in input 0dB gain
Line in input 18dB gain
Total harmonic
distortion
Max level at MIC input, 21dB gain
Deviation from
linear phase
Measurement bandwidth 20Hz to
20kHz, Fs= 48kHz. Combined digital
and analog filter characteristics
Passband
Combined digital and analog filter
characteristics AD96K=0
Passband ripple
Combined digital and analog filter
characteristics AD96K=0
Stopband
Combined digital and analog filter
characteristics AD96K=0
Stopband
Attenuation
Measurement bandwidth up to
3.45Fs. Combined digital and analog
filter characteristics, AD96K=0
Group delay
Audio filters, 96kHz FS
Audio filters, 48kHz FS
Audio filters, 8kHz FS
Interchannel
isolation
0.001
0
0.003
%
1
Deg
0.45Fs
kHz
0.2
dB
0.55Fs
kHz
60
dB
0.11
0.4
2.6
ms
ms
ms
90
dB
Interchannel gain
mismatch
0.2
dB
Gain error
0.5
dB
Note: When 2.4 V < VCCA < 2.7 V, the values are reduced by 2dB
69/85
Stereo audio DAC specifications
13
STw5098
Stereo audio DAC specifications
Information included in this section applies to both entities.
Typical measures at VCCA=VCCP=VCCLS=2.7V; VCCIO=VCC=1.8V; Tamb=25° C;13MHz
AMCK
Table 53.
Symbol
DAN
Stereo audio DAC specifications
Parameter
Test conditions
Min.
Typ.
Resolution
20Hz to 20kHz, A-weighted.
Measured at -60dBFS
Differential line out
Single-ended line out
HPL/HPR to GND or VCMHP
LSP-LSN
90
Max.
Unit
20
Bits
95
93
94
94
dB
dB
dB
dB
94
90
dB
dB
DADR
Dynamic range
DASNA
DASN
2Vpp output
HPL, HPR gain set to -6dB, 16Ω load
Signal to noise ratio
A-weighted
Unweighted (20 Hz to 20 kHz)
DATHDL
Total harmonic
distortion
Worst case load
2Vpp output
HPL, HPR gain set to -6dB, 16Ω load
0.02
DATHD
Total harmonic
distortion
2Vpp output,
HPL, HPR gain set to -6dB, 1kΩ load
0.004
Deviation from
linear phase
Measurement bandwidth 20Hz to
20kHz, Fs= 48kHz.
Combined digital and analog filter
characteristics
Passband
Combined digital and analog filter
characteristics, DA96K=0
Passband ripple
Combined digital and analog filter
characteristics, DA96K=0
Stopband
Combined digital and analog filter
characteristics, DA96K=0
0.55Fs
kHz
Stopband
attenuation
Measurement bandwidth up to
3.45Fs.
Combined digital and analog filter
characteristics, DA96K=0
50
dB
DAfPB
DAfSB
TSF
Transient
suppression filter
cut-off frequency
Out of band noise
70/85
0
15
Measurement bandwidth 20 kHz to
100 kHz. Zero input signal
0.04
%
1
Deg
0.45Fs
kHz
0.2
dB
23
-85
%
Hz
dBr
STw5098
Table 53.
Symbol
DAtgd
SUT
AD to DA mixing (sidetone) specifications
Stereo audio DAC specifications (continued)
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Group delay
Audio filters, 96kHz FS
Audio filters, 48kHz FS
Audio filters, 8kHz FS
0.09
0.4
2.6
ms
ms
ms
Interchannel
isolation
2Vpp output
HPR, HPL unloaded
HPR, HPL with 16Ω to VCMHP
100
60
dB
dB
Interchannel gain
mismatch
0.2
dB
Gain error
0.5
dB
Startup time from
power up
FS=48 kHz
Line out
HPL/R out
1
10
ms
ms
Note: When 2.4 V < VCCA < 2.7 V, values are reduced by 2 dB
14
AD to DA mixing (sidetone) specifications
Information included in this section applies to both entities.
Typical measures at VCCA=VCCP=VCCLS=2.7V; VCCIO=VCC=1.8V; Tamb=25° C;13MHz
AMCK.
Table 54.
Symbol
STDEL
AD to DA mixing (sidetone) specifications
Parameter
AD to DA mixing
(sidetone) delay
Test conditions
Valid for audio and voice filters
Min.
Typ.
Max.
Unit
5
10
µs
71/85
Stereo analog-only path specifications
15
STw5098
Stereo analog-only path specifications
Information included in this section applies to both entities.
Measured at differential line-out, ENOSC=1, No master clock.
Typical measures at VCCA=VCCP=VCCLS=2.7V; VCCIO=VCC=1.8V; Tamb=25° C
Table 55.
Symbol
Stereo analog-only path specifications
Parameter
Test conditions
Min.
Typ.
90
90
95
97
dB
dB
97
94
dB
dB
AADRM
AADRLI
Dynamic range
20Hz to 20kHz, A-weighted.
Measured at -60dBFS
MIC input, 21dB gain
Line-In, 0dB gain
AASNA
AASN
Signal to noise ratio
Max level at line-in input, 0dB gain,
A-weighted
Unweighted (20 Hz to 20 kHz)
AATHD
Total harmonic
distortion
Unit
1kHz @ 0dBFS
MIC input, 21dB gain
Line-in input, 0dB gain
Note: When 2.4V<VCCA<2.7V, the values are reduced by 2dB.
72/85
Max.
0.003
0.004
0.01
0.02
%
%
STw5098
16
ADC (TX) & DAC (RX) specifications with voice filters selected
ADC (TX) & DAC (RX) specifications with voice filters
selected
Information included in this section applies to both entities.
Typical measures at VCCA=VCCP=VCCLS=2.7V; VCCIO=VCC=1.8V; Tamb=25° C;13MHz
AMCK
Table 56.
Symbol
ADC (TX) & DAC (RX) specifications with voice filters selected
Parameter
Test conditions
Min.
Typ.
Max.
Unit
86
83
89
86
dB
dB
TXDR
RXDR
Dynamic range
300Hz to 3.4kHz; 1kHz @ -60dBFS
TX Path, MIC input, 21dB gain
RX Path, LS Output, 0dB gain
TXSN
RXSN
Signal to noise ratio
300Hz to 3.4kHz; 1kHz @ 0dBFS
TX Path, MIC input, 21dB gain
RX Path, LS and EAR outputs, 0dB gain
88
86
dB
dB
THD
THD
1kHz @ 0dBFS
TX Path, MIC input, 21dB gain
RX Path, LS and EAR outputs, 0dB gain
<0.001
0.005
%
%
TXG
RXG
TX gain mask
f=60Hz
f=100Hz
f=200Hz
f=300Hz
f=400Hz-3000Hz
f=3400Hz
f=4000H
f=4600Hzz
f=8000Hz
RX gain mask
f=60Hz
f=100Hz
f=200Hz
f=300Hz
f=400Hz-3000Hz
f=3400Hz
f=4000Hz
f=5000Hz
RX out of band
noise
Measurement bandwidth 4kHz to
100kHz. Zero input signal
Group delay
TX path
RX path
-1.5
-0.5
-1.5
-1.5
-0.5
-1.5
-30
-24
-6
0.5
0.5
0.0
-14
-35
-47
dB
dB
dB
dB
dB
dB
dB
dB
dB
-20
-12
-2
0.5
0.5
0.0
-14
-50
dB
dB
dB
dB
dB
dB
dB
dB
-85
dBr
0.32
0.28
ms
ms
Note: When 2.4V<VCCA<2.7V, the values are reduced by 2dB
73/85
Typical performance plots
17
STw5098
Typical performance plots
Figure 14. Bass treble control, de-emphasis
filter
Figure 15. Dynamic compressor transfer
function
1
10
Output Amplitude [FS]
Gain @ Fs=44.1 kHz [dB]
15
5
0
-5
-10
0.75
0.5
0.25
0
-0.25
-0.5
-0.75
-15
100
1k
Frequency [Hz]
-1
10k
-1 -0.75-0.5-0.25 0 0.25 0.5 0.75 1
Input Amplitude [FS]
Bass and treble gains are independently selectable in any combination.
The de-emphasis filter (thick line, alternative to treble control)
compensates for pre-emphasis used on some audio CDs.
Gain error < 0.1dB. Filter characteristics at Fs=44.1kHz are plotted
Figure 16. ADC audio path measured filter
response
Audio signal transfer function when the Dynamic Compressor is active.
Figure 17. ADC in band audio path measured
filter response
0
-10
Gain [dB]
Gain [dB]
-20
-30
-40
-50
-60
-70
-80
100
1k
10k
Frequency [Hz]
100k
48 kHz sample rate.
Full ADC path Frequency response up to 100 kHz.
Gain [dB]
Gain [dB]
-20
-40
-60
-80
100k
DA96K=0; 48 kHz Sample Rate
Frequency response up to 166kHz (3.45 Fs @ 48kHz sampling rate)
74/85
5k
10k
15k
Frequency [Hz]
20k
Figure 19. DAC in band digital audio filter
characteristics
0
1k
10k
Frequency [Hz]
0
48 kHz Sample Rate.
In band Frequency response
Figure 18. DAC digital audio filter
characteristics
100
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0
5k
10k
15k
Frequency [Hz]
48 kHz Sample Rate
In band Frequency response
20k
STw5098
Typical performance plots
Figure 20. ADC 96 kHz audio path measured
filter response
Figure 21. ADC 96 kHz audio in-band
measured filter response
1
0
0
-10
Gain [dB]
Gain [dB]
-20
-30
-40
-50
-60
-1
-2
-3
-4
-70
-5
-80
10
100
1k
Frequency [Hz]
10k
0
100k
5k 10k 15k 20k 25k 30k 35k 40k 45k
Frequency [Hz]
The plot is extended down to 5 Hz to show the high pass filter
implemented in the ADC 96 kHz sample rate,
96 kHz audio filter selected signal from Mic input
96 kHz sample rate,
96 kHz audio filter selected signal from Mic input.
Figure 22. ADC voice TX path measured filter
response
Figure 23. ADC voice TX path measured inband filter response
0
-20
Gain [dB]
Gain [dB]
-10
-30
-40
-50
-60
-70
100
1k
Frequency [Hz]
10k
Figure 24. DAC voice (RX) digital filter
characteristics
-20
Gain [dB]
Gain [dB]
-10
-30
-40
-50
-60
8 kHz sample rate, rx voice filter
1k
1500 2k 2500
Frequency [Hz]
3k
3500
4k
Figure 25. DAC voice (RX) in-band digital filter
characteristics
0
1k
Frequency [Hz]
500
8 kHz sample rate, tx voice filter selected signal from Mic input.
8 kHz Sample rate, tx voice filter selected.
Signal from Mic input
-70
100
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
10k
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
500
1k
1500 2k 2500
Frequency [Hz]
3k
3500
4k
8 kHz sample rate, rx voice filter
75/85
Typical performance plots
Figure 26. ADC path FFT
STw5098
Figure 27. ADC S/N versus input-level
100
90
-20
80
-40
70
S/N [dB]
Amplitude [dBFS]
0
-60
-80
60
50
40
-100
-120
30
0
2k
4k
6k
20
8k 10k 12k 14k 16k 18k 20k
Frequency [Hz]
12 MHz master clock.
Differential input at Mic preamplifier, 21 dB gain.
48 kHz sampling rate.
Both channels active
Figure 28. DAC path FFT
-10
0
100
90
-20
80
-40
S/N [dB]
Amplitude [dBFS]
-40
-30
-20
Input Level [dBFS]
Figure 29. DAC S/N versus input-level
-60
-80
-120
70
60
50
40
-100
30
0
2k
4k
6k
20
8k 10k 12k 14k 16k 18k 20k
Frequency [Hz]
12 MHz master clock.
48 kHz sampling rate
Differential output at line-out, 1kΩ load.
Both channels active
Figure 30. Analog path FFT
-60
-50
-40
-30
-20
Input Level [dBFS]
-10
0
12 MHz master clock.
48 kHz Sampling Rate
Differential output at Line-Out, 1kΩ load.
A-Weighted, Both channels active
Figure 31. Analog path S/N versus input-level
100
0
90
-20
80
-40
S/N [dB]
Amplitude [dBFS]
-50
12 MHz master clock
Differential input at Line-In Amplifier, 0 dB gain.
48 kHz Sampling Rate
A-Weighted, Both channels active
0
-60
-80
70
60
50
40
-100
-120
30
0
2k
4k
6k
8k 10k 12k 14k 16k 18k 20k
Frequency [Hz]
Differential input at Mic Preamplifier, 21 dB gain.
Direct Mic to Line-Out connection (MICLO=1)
Differential output at Line-Out, 20kΩ load. Both channels active
76/85
-60
20
-60
-50
-40
-30
-20
Input Level [dBFS]
-10
0
Differential input at Line-In Amplifier, 0 dB gain.
Line-In to DA-Mixer to Line-Out connection.
Differential output at Line-Out, 20kΩ load. A-weighted, both channels
active
STw5098
18
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
77/85
Package mechanical data
18.1
STw5098
LFBGA 6x6x1.4
Table 57.
Dimensions of LFBGA 6x6x1.4 112 4R11x11. 0.5
Databook (mm)
Drawing (mm)
Reference
Notes
Min.
Typ.
A
A1
0.15
78/85
Max.
1.26
0.16
0.21
0.26
0.985
0.93
0.985
1.04
A3
0.20
0.16
0.20
0.24
0.80
0.77
0.785
0.80
b
0.25
0.30
0.35
0.25
0.30
0.35
D
5.85
6.00
6.15
5.90
6.00
6.10
E
2
Typ.
A2
D1
1
Min.
1.40
A4
Note:
Max.
5.00
5.85
6.00
Note 1
Note 2
5.00
6.15
5.90
6.00
E1
5.00
5.00
e
0.50
0.50
F
0.50
0.50
6.10
ddd
0.08
0.08
eee
0.15
0.15
Note 4
fff
0.05
0.05
Note 5
LFBGA stands for Low Profile Fine Pitch Ball Grid Array.
- Low profile: the total profile height (DIm A) is measured from the seating plane to the top of
the component. The maximum total package height is calculated as follows:
2
2
2
A2Typ + A1Typ + ( A 1 + A3 + A4 tolerancevalues ) . Fine pitch: e<1.0 mm pitch
The typical ball diameter before mounting is 0.30 mm
3
The tolerance of position that controls the location of the pattern of balls with respect to
datum A and B. For each ball there is a cylindrical tolerance zone eee perpendicular to
datum C and located on true position with respect to datum A and B as defined by e. The
axis perpendicular to datum C of each ball must lie within this tolerance zone.
4
The tolerance of position that controls the location of the balls within the matrix with respect
to each other. For each ball there is a cylindrical tolerance zone fff perpendicular to datum C
and located on true position as defined by e. The axis perpendicular to datum C of each ball
must lie within this tolerance zone. Each tolerance zone fff in the array is contained entirely
in the respective zone eee above.
The axis of each ball must lie simultaneously in both tolerance zones.
5
The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink
or metallized markings, or other feature of package body or integral heatslug. A
distinguishing feature is allowable on the bottom surface of the package to identify the
terminal A1 corner. Exact shape of each corner is optional.
STw5098
Package mechanical data
C
Figure 32. LFBGA 6x6x1.4 112 4R11x11 0.5 drawing
ddd
SEATING
PLANE
A
A1
A2
C
D
D1
f
e
E1
K
J
I
H
G
F
E
D
C
B
A
E
f
e
1 2 3 4 5 6 7 8 9 10 11
A1 CORNER INDEX AREA
(SEE NOTE 3)
Øb (112 BALLS)
BOTTOM VIEW
79/85
Package mechanical data
18.2
STw5098
VFBGA 5x5x1.0
Table 58.
Dimensions of VFBGA 5x5x1.0 112 balls 0.4 mm pitch
Databook (mm)
Drawing (mm)
Reference
Notes
Min.
Typ.
A
A1
0.125
80/85
Max.
0.99
0.125
0.165
0.205
0.765
0.71
0.765
0.82
A3
0.18
0.14
0.18
0.22
0.60
0.57
0.585
0.60
b
0.22
0.26
0.30
0.22
0.26
0.30
D
4.95
5.00
5.05
4.95
5.00
5.05
E
2
3
Typ.
A2
D1
1
Min.
1.00
A4
Note:
Max.
4.00
4.95
5.00
Note 1
Note 2
4.00
5.05
4.95
5.00
E1
4.00
4.00
e
0.40
0.40
F
0.50
0.50
5.05
Note 3
ddd
0.08
0.08
eee
0.13
0.13
Note 4
fff
0.04
0.04
Note 5
VFBGA stands for Very thin Profile Fine Pitch Ball Grid Array.
The maximum total package height is calculated by the following methodology:
2
2
2
A2Typ + A1Typ + ( A 1 + A3 + A4 tolerancevalues ) .
Very thin profile: 0.80mm < A ≤1.00mm Max/Fine pitch: e<1.0 mm
The typical ball diameter before mounting is 0.25 mm
VFBGA with 0.40mm ball pitch is not yet registered into JEDEC publications.
4
The tolerance of position that controls the location of the pattern of balls with respect to
datum A and B. For each ball there is a cylindrical tolerance zone eee perpendicular to
datum C and located on true position with respect to datum A and B as defined by e. The
axis perpendicular to datum C of each ball must lie within this tolerance zone.
5
The tolerance of position that controls the location of the balls within the matrix with respect
to each other. For each ball there is a cylindrical tolerance zone fff perpendicular to datum C
and located on true position as defined by e. The axis perpendicular to datum C of each ball
must lie within this tolerance zone. Each tolerance zone fff in the array is contained entirely
in the respective zone eee above.
The axis of each ball must lie simultaneously in both tolerance zones.
6
The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink
or metallized markings, or other feature of package body or integral heatslug. A
distinguishing feature is allowable on the bottom surface of the package to identify the
terminal A1 corner. Exact shape of each corner is optional.
STw5098
Package mechanical data
Figure 33. VFBGA 5x5x1.0 112 0.4 drawing
81/85
Application schematics
19
Application schematics
See Figure 34: STw5098 application schematics.
82/85
STw5098
AUDIO_1V8
AUDIO_FM_RIGHT
AUDIO_FM_LEFT
AUDIO_FROM_MODEM_N
AUDIO_FROM_MODEM_P
AUDIO_PCM_CLK
AUDIO_BT_PCM_FS
AUDIO_FROM_BT_PCM_DATA
AUDIO_APP_I2S_DA_DATA
AUDIO_APP_I2S_AD_DA_CLK
AUDIO_APP_I2S_AD_DA_SYNC
AUDIO_PWR_AMPLIFIER_STANDBY
AUDIO_CLK
AUDIO_I2C_SDA
M800
Microphone
5
1
2
AUDIO_PWR_AMPLIFIER_STANDBY
AUDIO_TO_TVOUT_R
AUDIO_TO_TVOUT_L
AUDIO_FROM_MODEM_P
AUDIO_FROM_MODEM_N
AUDIO_HANDSET_MIC_N
AUDIO_HANDSET_MIC_P
AUDIO_APP_I2S_AD_DATA
AUDIO_CLK
AUDIO_TO_BT_PCM_DATA
AUDIO_I2C_SCLK
AUDIO_I2C_SDA
100nF
C800
220 nF / 0406
AUDIO_TO_TVOUT_L
AUDIO_TO_TVOUT_R
AUDIO_FM_ANTENNA
1
AUDIO_I2C_SCLK
AUDIO_IRQ
R810
1.2kohm
R807
1.2kohm
33uF
C807
R808
2.7kohm
R811
2.7kohm
5
AUDIO_1V8
5
AUDIO_1V8
R802
10kohm
AUDIO_TO_MODEM_P
C811
E9
680nF
C805
C810
C806
C812
100nF
C826
100nF
C816
100nF
C838
100nF
C832
J1
H4
K2
J7
J6
J11
H9
I9
H3
I3
K11
J4
K4
I4
K7
K9
K8
K5
K6
D9
C1
C3
F8
I11
G3
F10
E2
G10
G9
C803
C804
G1
C802
H1
D10
D2
F2
F9
680nF
E3
C2
C11
D5
B8
D4
B7
A8
C6
A9
A7
A4
B2
D3
220 nF / 0406
100nF
A6
C7
C4
680nF
220 nF / 0406
100nF
100nF
100nF
100nF
100nF
100nF
D7
C8
680nF
220 nF / 0406
C820
C821
C809
220ohm
R815
470nF
C815
C808
100nF
1nF
1 uF / 0402
C801
B4
A2
C5
1
1
1
1
AUDIO_TO_MODEM_N
2
2
2
2
AUDIO_2V8
2.2 uF / 0603
5
2.2nF
C813
5
MN800
STW5098
1IRQ
GND2
1MBIAS
2HDET
2AUX1L
2AUX2LN
2AUX3L
1CAPLINEIN
1LINEINR
2LINEINR
GNDCM2
GNDCM1
GNDP4
GNDP2
GNDP1
GNDP3
2ORN
ST000000131
1HPR
VCCP2
VCCP1
VCCP4
VCCP3
VCCLS3
VCCLS1
VCCLS2
1ORN
1ORP
1OLN
1OLP
2ORP
2OLN
2OLP
1VCMHPS
1VCMHP
1HPL
1CAPLS
1LSNS
1LSN
1LSPS
1LSP
GNDA1
GNDA2
2CAPLINEIN
2HPR
2VCMHPS
2VCMHP
2HPL
2CAPLS
2LSNS
2LSN
2LSPS
2LSP
VCCA3
VCCA1
VCCA2
2LINEINL
2AUX3R
2AUX2RN
1LINEINL
1AUX3R
1AUX3L
2AUX2RP
1AUX2RN
1AUX2RP
1AUX2LN
2AUX2LP
2AUX1R
2CAPMIC
1AUX2LP
1AUX1R
1AUX1L
2MICRN
2MICRP
2MICLN
2MICLP
1CAPMIC
1MICRN
1MICRP
1MICLN
1MICLP
1HDET
2MBIAS
GND1
VCCIO
VCC1
2DA_DATA
2DA_SYNC
2DA_CK
2DA_OCK
2AD_OCK
2IRQ
1DA_DATA
1DA_CK
1DA_SYNC
VCC2
AMCK
2AD_DATA
2AD_CK
2AD_SYNC
2AS_CSB
2SDA_SDIN
2SCLK
2CMOD
1AD_DATA
1AD_CK
1AD_SYNC
1DA_OCK
1AD_OCK
1SCLK
1AS_CSB
1SDA_SDIN
1CMOD
A5
A3
D8
J2
H7
K10
K1
J9
I8
J5
I10
J10
I1
I2
H8
K3
I5
J3
I6
J8
I7
H5
H6
F3
G8
E8
H10
G4
E10
E1
G11
H11
G2
H2
D11
D1
F1
E11
F11
E4
F4
B1
C10
B11
A1
B10
B6
B9
B5
B3
C9
A11
D6
A10
220ohm
R816
C822
100nF
5
2
1uF
C827
33uF
1
TP809
TP806
AUDIO_1V8
100nF
C835
1uF
VBAT
C818
100nF
C839
22uF / 0805
Mono speaker
HP800
2
22uF / 0805
C837
AUDIO_2V8
C833
10uF
C836
C834
C831
C830
C829
C828
C824
C823
220 nF / 0406
100nF
C817
C819
220 nF / 0406
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
C814
220 nF / 0406
100nF
1
AUDIO_1V8
2
AUDIO_2V8
1
AUDIO_APP_I2S_AD_DATA
10kohm
AUDIO_TO_BT_PCM_DATA
2
R800
5
1
VBAT
AUDIO_IRQ
AUDIO_BT_PCM_FS
C825
100nF
C139
100nF
AUDIO_TO_MODEM_P
AUDIO_TO_MODEM_N
22pF
C841
22kohm
R813
1nF
22pF
C842
C840
1 uF / 0402
22kohm
R814
AUDIO_EARKIT_RIGHT_SPEAKER
AUDIO_EARKIT_COMMON_VOLTAGE_SPEAKER
AUDIO_EARKIT_LEFT_SPEAKER
AUDIO_FM_ANTENNA
AUDIO_FM_LEFT
AUDIO_FM_RIGHT
AUDIO_APP_I2S_AD_DA_SYNC
AUDIO_APP_I2S_AD_DA_CLK
AUDIO_APP_I2S_DA_DATA
AUDIO_PCM_CLK
AUDIO_FROM_BT_PCM_DATA
E5
D6
B2
A1
C3
C1
VBAT
22pF
C843
STDBY
BYPASS1
IN2M
IN2P
IN1P
IN1M
22pF
C844
5
AUDIO_2V8
TS4984
MN801
B6
GND2
E1
R809
22kohm
GND1
D2
3
1
D801
5
I_O3
GND2
2
I_O2
GND1
I_O5
TRANSIL
ST000000145
I_O1
BYPASS2
VOUT2M
VOUT2P
VOUT1M
VOUT1P
1nF
C846
1 uF / 0402
22pF
C845
C5
E3
D4
A3
B4
AUDIO_JACK_DETECT
ST000000133
A5
?
R812
22kohm
?
VCC2
VBAT
VCC1
4
6
HP802
HP801
3
J800
ST000000144
JACK_CUI
LOUDSPEAKER 2
LOUDSPEAKER 1
2
4
4
1
3
2
1
Jack audio
Figure 34. STw5098 application schematics
A
STw5098
Application schematics
83/85
2
Ordering information
20
STw5098
Ordering information
Table 59.
Order codes
Part Number
21
Packing
STw5098
LFBGA 6x6x1.4, 0.5 mm pitch, 112 pins
Tray
STw5098T
LFBGA 6x6x1.4, 0.5 mm pitch, 112 pins
Tape and reel
STw5098BBLR/LF
VFBGA 5x5x1.0, 0.4 mm pitch, 112 pins
Tray
STw5098BBLT/LF
VFBGA 5x5x1.0, 0.4 mm pitch, 112 pins
Tape and reel
Revision history
Table 60.
84/85
Package
Document revision history
Date
Revision
24-Apr-2007
1
Changes
Initial release.
STw5098
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2007 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
85/85