Issue 5.0 June 1999 Description The SYS32512 is a 512K x 8 SRAM module in a ZIP (ZK) or SIMM (LK & LKXA) packages with access times of 12 and 15ns, with 10ns parts under development. The device is available to commercial and industrial temperature grade. The LK SIMM package is designed for standard SIMM sockets. The LKXA is designed to fit both angled and standard sockets. Block Diagram A0~A18 /WE /OE 512K x 8 SRAM D0~7 /CS1 512K x 8 SRAM D8~15 /CS2 512K x 8 Features • Access times of 10, 12 and 15ns. • 5V + 10%. • Commercial and Industrial temperature grades • 72 pin ZIP and SIMM packages. • Industry standard footprint. • Power dissipation. • Operating Power (32 Bit) 4.62W (max) • Low power standby. (TTL) 1.32W (max) (CMOS) 330mW (max) • Completely Static Operation. SRAM D16~23 /CS3 512K x 8 SRAM D24~D31 /CS4 Pin Definition See page 2. Pin Functions Package Details Plastic 72 Pin ZIP (ZK) Max. Dimensions (mm) - 97.80 x 20.61 x 5.90 Plastic 72 Pin SIMM (LK) Max. Dimensions (mm) - 108.08 x 15.00 x 5.25 Plastic 72 Pin SIMM (LKXA) Max. Dimensions (mm) - 108.08 x 20.32 x 4.55 Description Signal Address Input Data Input/Output Chip Select Presence Detect Write Enable Output Enable No Connect Power Ground A0~A18 D0~D31 /CS1~4 PD0~3 /WE /OE NC VCC VSS 512 K x 32 Static RAM SYS32512ZK/LK - 010/012/015 Pin Definition - SYS32512 ZK/LK/LKXA Pin Signal Pin Signal 1 NC 37 /CS4 2 NC 38 /CS3 3 PD2 39 A17 4 PD3 40 A16 5 V SS 41 /OE 6 PD0 42 V SS 7 PD1 43 D24 8 D0 44 D16 9 D8 45 D25 10 D1 46 D17 11 D9 47 D26 12 D2 48 D18 13 D10 49 D27 14 D3 50 D19 15 D11 51 A3 16 V CC 52 A10 17 A0 53 A4 18 A7 54 A11 19 A1 55 A5 20 A8 56 A12 21 A2 57 V CC 22 A9 58 A13 23 D12 59 A6 24 D4 60 D20 25 D13 61 D28 26 D5 62 D21 27 D14 63 D29 28 D6 64 D22 29 D15 65 D30 30 D7 66 D23 31 V SS 67 D31 32 /WE 68 V SS 33 A15 69 A18 34 A14 70 NC 35 /CS2 71 NC 36 /CS1 72 NC Note ZK : PD1=GND, PDO=PD2=PD3=OPEN PAGE 2 Issue 5.0 June 1999 Absolute Maximum Ratings(1) Symbol (2) Voltage on any pin relative to VSS VT Power Dissipation PT Storage Temperature TSTG Min -0.3 to Max Unit +7.0 V 4.0 -55 to W O +125 C Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability (2) VT can be -2.0V pulse of less than 2ns. Recommended Operating Conditions Parameter Symbol Min Typ Max Unit Supply Voltage VCC 4.5 5.0 5.5 V Input High Voltage VIH 2.2 - VCC+0.3 V Input Low Voltage VIL -0.3 - 0.8 Operating Temperature (Commercial) (Industrial) TA 0 - 70 TAI -40 - 85 V O C O C (I Suffix) DC Electrical Characteristics (VCC=5V+10%, TA=0OC to 70OC) Parameter Symbol Test Condition Min Typ Max Unit Input Leakage Current Address, /OE, /WE ILI 0V < V IN < V CC -8 - 8 µA Output Leakage Current Worst Case ILO /CS=V IH,V I/O =GND to V CC -8 - 8 µA Average Supply Current 32 Bit ICC1 Min. Cycle, /CS=VIL , V IN =V IH or V IL, IOUT =OmA - - 840 mA Standby Supply Current TTL ISB1 /CS=V IH - - 240 mA CMOS ISB2 /CS >V CC-0.2V, 0.2V >V IN>V CC-0.2V - - 60 mA Output Voltage Low V OL IOL=8.0mA - - 0.4 V Output Voltage High V OH IOH=-4.0mA 2.4 - - V Notes (1) /CS1~4 inputs operate simultaneously for 32 bit mode, in pairs for 16 bit mode and singly for 8 bit mode. (2) Typical Values are at VCC=5.0V, TA=25OC and specified loading. /CS above refers to /CS1~4 PAGE 3 Issue 5.0 June 1999 DC Operating Conditions Parameter Capacitance (VCC = 5.0V, TA = 25OC) P aram eter S ym b ol T est C ondition M in T yp M ax U nit Input C apacitan ce, ( Address, /O E, /W E) C IN 1 V IN = 0V - - 32 pF Input C apacitan ce, ( O ther) C IN 2 V IN = 0V - - 7 pF O utpu t C apacita nce, 8 bit m ode (w orst case) C I/O V I/O = 0V - - 40 pF Note : These Parameters are calculated not measured. Test Conditions • • • • • Output Load Input pulse levels : 0V to 3.0V Input rise and fall times : 3ns Input and Output timing reference levels : 1.5V Output Load : See Load Diagram. VCC = 5V+10% I/O Pin 166Ω 1.76V 30pF Operation Truth Table /CS /OE /WE Data Pins Supply Current Mode H X X High Impedence ISB1,ISB2 Standby L L H Data Out ICC1 Read L H L Data In ICC1 Write L L L Data In ICC1 Write L H H High Impedence ISB1,ISB2 High Z Notes : H=VIH : L=VIL : X=VIH or VIL PAGE 4 Issue 5.0 June 1999 10 Parameter 12 15 Symbol Min Max Min Max Min Max Units Read Cycle Time tRC 10 - 12 - 15 - ns Address Access Time tAA - 10 - 12 - 15 ns Chip Select Access Time tACS - 10 - 12 - 15 ns Output Enable to Output Valid tOE - 5 - 6 - 7 ns Output Hold From Address Change tOH 3 - 3 - 3 - ns Chip Selection to Output in Low Z tCLZ 3 - 3 - 3 - ns Output Enable to Output in Low Z tOLZ 0 - 0 - 0 - ns Chip Deselection to Output in High Z tCHZ 0 5 0 6 0 7 ns Output Disable to Output in High Z tOHZ 0 5 0 6 0 7 ns Write Cycle 10 Parameter Symbol 12 15 Min Max Min Max Min Max Units Write Cycle Time tWC 10 - 12 - 15 - ns Chip Selection to End of Write tCW 7 - 8 - 10 - ns Address Valid to End of Write tAW 7 - 8 - 10 - ns Address Setup Time tAS 0 - 0 - 0 - ns Write Pulse Width tWP 7 - 8 - 10 - ns Write Recovery Time tWR 0 - 0 - 0 - ns Write to Output in High Z tWHZ 0 5 0 6 0 10 ns Data to Write Time Overlap tDW 5 - 6 - 7 - ns Data Hold time from Write Time tDH 0 - 0 - 0 - ns Output Active from End of Write tOW 3 - 3 - 3 - ns Under Development PAGE 5 Issue 5.0 June 1999 AC Operating Conditions Read Cycle Timing Waveforms Read Cycle 1 (Address Controlled, /CS=/OE=VIL, /WE=VIH) tRC Address tOH Data Out tAA Previous Data Valid Data Valid Read Cycle 2 (/WE = VIH) tRC Address tAA tACS tCHZ(3,4,5) /CS tOHZ tOE /OE tOLZ tOH tCLZ(4,5) Data Out Valid Data NOTES(READ CYCLE) 1. /WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V OH or VOL levels. 4. At any given temperature and voltage condition, t CHZ(Max.) is less than t CLZ(Min.) both for a given device and from device to device. 5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with /CS=V IL. 7. Address valid prior to coincident with /CS transition low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 9. /CS=/CS1~4 PAGE 6 Issue 5.0 June 1999 Write Cycle 1 (/OE = Clock) tWC Address tAW tWR(5) /OE tCW(3) /CS tAS(4) tWP(2) /WE tDW tDH High Z Data In Valid Data tOHZ(6) High Z(8) Data Out NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low /CS and /WE. A write begins at the latest transition /CS going low and /WE going low ; A write ends at the earliest transition /CS going high or /WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of /CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 6. If OE, /CS and /WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If /CS goes low simultaneously with /WE going or after /WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10.When /CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. 11 ./CS=/CS1~4 PAGE 7 Issue 5.0 June 1999 Write Cycle 2 (/OE = Low Fixed) tWC Address tAW tWR(5) tCW(3) /CS tAS(4) tWP(2) /WE tDW tDH High Z Valid Data Data In tOW tWHZ(6) High Z(8) (10) (9) Data Out NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low /CS and /WE. A write begins at the latest transition /CS going low and /WE going low ; A write ends at the earliest transition /CS going high or /WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of /CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 6. If OE, /CS and /WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If /CS goes low simultaneously with /WE going or after /WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10.When /CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. 11 ./CS=/CS1~4 PAGE 8 Issue 5.0 June 1999 Write Cycle 3 (/CS = Controlled) tWC Address tAW tWR(5) tCW(3) /CS tAS(4) tWP(2) /WE tDW tDH High Z High Z Data In Valid Data tLZ High Z tWHZ(6) High Z(8) Data Out NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low /CS and /WE. A write begins at the latest transition /CS going low and /WE going low ; A write ends at the earliest transition /CS going high or /WE going high. t WP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of /CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. t WR applied in case a write ends as /CS or /WE going high. 6. If /OE, /CS and /WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If /CS goes low simultaneously with /WE going or after /WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10.When /CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. 11 /CS=/CS1~4 PAGE 9 Issue 5.0 June 1999 Front View 97.80 M ax. 16. 61 Ma x FROM S TA NDOF F 5.90 Max. 3.50 +0.5 Pin 1 2.54 Typ. 6.35 Typ. Pin 72 Plastic 72 pin SIMM (LK) Front View 108.08 Max. L1 Pin 1 1.27 Typ. 6.35 Typ. 1 5. 00 Max . 5 . 2 5 Ma x . L2 Pin 72 Plastic 72 pin SIMM (LKXA) FRONT VIEW 108.08 MAX 4.55 MAX. 20.32 M A X L1 Pin 1 PAGE 10 6.35 typ 1.27 typ. Pin 72 Issue 5.0 June 1999 Package Details Plastic 72 pin ZIP (ZK) Ordering Information Speed Temperature Range 010 = 10ns 012 = 12ns 015 = 15ns Blank = Commercial I = Industrial Power Consumption Blank = Standard Package ZK = Plastic 72 pin ZIP LK = Plastic 72 pin SIMM LKXA = Plastic 72 pin SIMM (Angled Sockets) Memory Organisation 32512 = 512K x 32 Technology SYS = SRAM Note : Although this data is believed to be accurate the information contained herein is not intended to and does not create any warranty of merchantibility or fitness for a particular purpose. Our products are subject to a constant process of development. Data may be changed without notice. Products are not authorised for use as critical components in life support devices without the express written approval of a company director. PAGE 11 http://www.mosaicsemi.com/ Issue 5.0 June 1999 Ordering Information SYS32512ZK/LK I - 010