T6B70BF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic T6B70BF Interface IC for Water Heater The T6B70BF incorporates two-channel 4-bit DA converter, a pseudo sine wave generator and an external analog signal detection/non-detection circuit. It is designed to be used mainly for communication between water heater and control unit. Features · On-chip two-channel 4-bit DA converter (opposite polarities) · On-chip pseudo sine wave generator (external clock/16) · On-chip external analog signal detection/non-detection circuit · On-chip two-channel analog switch Weight: 0.16 g (typ.) Block Diagram OSCIN 1 OSCOUT 2 Divide-by16 unit Pseudo sine wave generator 0°C 180°C Waveform initialization block 4-bit DA converter 13 SOUT+ 4-bit DA converter 12 SOUT− FOUT 3 SCTL 4 16 VDD Modulation control circuit Zero-cross waveform shaping circuit SW1IN 14 Amplifier input circuit SW1OUT 15 7 AMPIN 6 AMPOUT Cycle measurement counter SW2IN 11 Analog signal detection/non-detection SW2OUT 10 RESET 5 8 VSS 9 DOUT Output buffer Reset circuit 1 2003-03-13 T6B70BF Pin Assignment OSCIN 1 16 VDD OSCOUT 2 15 SW1OUT FOUT 3 14 SW1IN SCTL 4 13 SOUT+ T6B70BF RESET 5 12 SOUT− AMPOUT 6 11 SW2IN AMPIN 7 10 SW2OUT VSS 8 9 DOUT Pin Function No. Symbol Input/Output Function 1 OSCIN Input Pins connected to oscillation 2 OSCOUT Output Pins connected to oscillation 3 FOUT Output Output pin for oscillation waveform shaping circuit 4 SCTL Input Modulation control signal input pin 5 RESET Input Reset signal input pin 6 AMPOUT Output 7 AMPIN Input Amplifier signal output pin Amplifier signal input pin 8 VSS ― 9 DOUT Output Output pin for amplifier input signal detector Device GND pin (0 V) 10 SW2OUT Output Output pin on analog SW2 side 11 SW2IN Input 12 SOUT− Output Pseudo sine wave (opposite polarity of SOUT+ output) output pin 13 SOUT+ Output Pseudo sine wave output pin 14 SW1IN Input Input pin on analog SW1 side 15 SW1OUT Output Output pin on analog SW1 side 16 VDD ― Device power supply pin (+5 V) Input pin on analog SW2 side 2 2003-03-13 T6B70BF Function Description Pseudo sine wave generator and 4-bit DA converters (sending block) Pseudo sine wave signal with Fosc/16 frequency is driven out from pseudo sine wave output pin (SOUT+ and SOUT−). The outputs of pins SOUT+ and SOUT− have the opposite polarities. The block of pseudo sine wave generator and 4-bit DA converter (the side of SOUT+ pin) are shown below. SOUT+ pin MSB R R R SOUT+ R R R SOUT− LSB R FOSC R R R R 2R Pseudo sine wave generator (1) VSS RST The data of pseudo sine wave generator is driven out in the following sequence. 0 → 1 → 3 → 6 → 9 → C → E → F → F → E → C → 9 → 6 → 3 → 1 → 0 (in hexadecimal) FF E E C C 9 9 6 6 3 0 1 3 FSIN 250 kHz @FOSC = 4 MHz 1 0 Thus, the pseudo sine waveform of positive-going and negative-going outputs is like a staircase at no load. An analog switch is incorporated so that the driver output buffer is connected to the transmission line only when transmission is performed. However, an emitter follower circuit is externally connected to the driver output buffer. The phase difference between positive-going and negative-going outputs is within 180° ± 5°. (pseudo sine wave output phase fluctuation) 3 2003-03-13 T6B70BF (2) Amplifier input circuit and signal detection/non-detection circuit (receiving block) The modulation signal input block incorporates two level comparators having a high and a low threshold values to detect the external sine wave signal with amplitude higher than the specified threshold. Thus, it avoids signals with amplitude lower than the specified threshold (e.g., noise signals) being detected erroneously. The detection frequency range (frequency window) is determined by the divider ratio 1/18 to 1/14 of Fosc. In detection/non-detection determined condition, when the signals within the specified frequency range are detected (or not detected) sequentially, signals are controlled using the majority rule. The time which detection/non-detection is determined takes 9 to 15 waves to pass when one wave is referenced to Fosc/16 frequency. VDD Reference voltage VH RESET High comparator VA R Q S Q Cycle measurement counter R2 APU R1 VDD Reference voltage VL VBIAS Low comparator VB RESET R4 APD R3 7 AMPIN pin VSS Analog signal detection 9 /nondetection DOUT pin circuit 6 AMPOUT pin VDD VSS AMPIN input sine waveform VH Input sensitivity VPP VL Detect reception Not detect reception Not detect reception AMPOUT Truth Table AMPOUT output timing (when RESET is Low) VH VBIAS VL AMPOUT Held at High Not detect reception VA VB AMPOUT VBIAS > VH L H L VH > VBIAS > VL H H Hold VBIAS < VL H L H Held at Low VBIAS < VL VBIAS > VH VH > VBIAS > VL VH > VBIAS > VL 4 2003-03-13 T6B70BF (3) Function description and timing chart of the sending block When modulation control input ( SCTL ) is in High-level, pseudo sine wave output is held at 0° of the phase angle of pseudo sine wave. When modulation control input changes from High-level to Low-level, the pseudo sine wave output (SOUT+) starts from −90° (SOUT− starts from +90°). In this case, the time which takes to turn ON is as follows. td (ON) < 500 ns When modulation control input changes from Low-level to High-level, the phase angle is forcibly held at 0°, regardless of the phase of the pseudo sine wave output. (the pseudo sine wave output is stopped). In this case, the time which takes to turn OFF is as follows. td (OFF) < 1 µs SCTL td (OFF) td (ON) SOUT+ pseudo sine wave output (SOUT− output pin has the opposite polarity) (4) Function description and timing chart of the receiving block When it is ready to receive amplifier input signal, the time T (DET) which takes to change from High to Low at DOUT pin is within the time which 9 to 15 waves to pass. In this case, one wave is referenced to 16 Fosc clocks. The time width is determined by the internal clock and amplifier input signal. The timings of the internal clock and internal detection signal in the majority logic circuit are synchronous with each other. When input signals with the cycle, which is within the range specified by the frequency window, are detected (or not detected) sequentially, this rule is valid (the majority rule). Amplifier input T (DET) T (DET) DOUT Note 1: Any communication protocol is used, however, it takes 15 carrier waves to pass when the signal changes its state. 5 2003-03-13 T6B70BF Timing Chart (SOUT+ = SW1IN, SW1OUT, SOUT− = SW2IN, SW2OUT) VDD RESET OSCIN (4 MHz) FOUT AMPIN (250 kHz) VPP AMPOUT High-z SCTL When sending td (ON) td (OFF) FSIN SOUT+ VOPP SOUT− DOUT TDET When receiving TDET SW1IN SW1OUT High-z High-z SW2IN SW2OUT High-z High-z 6 2003-03-13 T6B70BF Maximum Ratings (Ta = 25°C ± 1.5°C) Characteristics Symbol Rating Unit VDD −0.3 to 6.0 V Input voltage VI −0.3 to VDD + 0.3 V Input peak current IIK −20 to 20 mA Operating temperature Topr −20 to 80 °C Storage temperature Tstg −55 to 125 °C 0.54 W Power supply voltage PD Power dissipation (Note 1) Note 1: Decreases approximately 4.35 mW per 1°C. Electrical Characteristics (unless otherwise specified, VDD = 5.0 V, VSS = 0 V, FOSC = 4 MHz and Ta = −20 to 80°C) Symbol Test Circuit Operating voltage VDD ― Current consumption IDD 1 FOSC 2 High level VIHOSC Low level Characteristics Test Condition Min Typ. Max Unit ― 4.5 5.0 5.5 V ― ― 10 mA ― 1 4 10 MHz 3 ― 0.7 VDD ― VDD VILOSC 3 ― VSS ― 0.3 VDD High level IIHROSC 4 VIN = 5 V, Ta = 25°C 3.2 6.58 13.2 Low level IILROSC 4 VIN = 0 V, Ta = 25°C −3.2 −6.58 −13.2 High level VOHOSC 3 IOH = −0.1 mA VDD − 1.0 ― VDD Low level VOLOSC 4 IOL = +0.1 mA VSS ― VSS + 0.6 Low to High input switching level VIHRST 5 ― 0.65 VDD ― VDD V High to Low input switching level VILRST 5 ― VSS ― 0.35 VDD V VDD pin (pin 16) No load, Fosc = 4 MHz OSCIN pin (pin 1) and OSCOUT pin (pin 2) Oscillation frequency Input voltage Input current Output voltage V µA V RESET pin (pin 5) High-level input current IIHRST 6 VIN = VDD Pull-up resistance 1 IILRRST1 7 VIN = VSS, Ta = 25 −10 ― 10 µA 9 15 21 kΩ Pull-up resistance 2 IILRRST2 7 VIN = VSS, Ta = −20 to 80 6.3 ― 27.3 kΩ Low to High input switching level VIHSCTL 8 ― 0.65 VDD ― VDD V High to Low input switching level VILSCTL 8 ― VSS ― 0.35 VDD V High level IIHSCTL 9 VIN = VDD −1 ― 1 Low level IILSCTL 9 VIN = VDD −1 ― 1 High level VOHFOUT 10 IOH = −1.0 mA VDD − 1.0 ― VDD Low level VOLFOUT 11 IOL = +1.0 mA VSS ― VSS + 0.6 SCTL pin (pin 4) Input current µA FOUT pin (pin 3) Output voltage V Note 2: One direction in which current flow into the IC should be + (sink) and the other direction in which current flow out from the IC should be − (drain). 7 2003-03-13 T6B70BF Symbol Test Circuit High level VOHDOUT 12 Low level VOLDOUT 13 TDET1 19 Characteristics Test Condition Min Typ. Max Unit IOH = −1.0 mA VDD − 1.0 ― VDD IOL = +1.0 mA VSS ― VSS + 0.6 40 ― 60 µs 36 ― 56 µs DOUT pin (pin 9) Output voltage Non-reception to reception detection time Reception to non-reception detection time TDET2 19 Fosc = 4 MHz, AMPIN = 250 kHz Time which takes DOUT to change from High to Low Fosc = 4 MHz, AMPIN = 250 kHz Time which takes DOUT to change from Low to High V AMPIN pin (pin 7) Input dynamic range VAMPIN 14 Pull-up resistance 1 IILRAPU1 15 VIN = VSS, Ta = 25 Pull-up resistance 2 IILRAPU2 15 VIN = VSS, Ta = −20 to 80 Pull-down resistance 1 IIHRAPD1 16 VIN = VDD, Ta = 25 Pull-down resistance 2 IIHRAPD2 16 VIN = VDD, Ta = −20 to 80 VBIAS 17 VPP 18 Amplifier input bias voltage Amplifier input sensitivity ― VSS ― VDD V 11.6 19.4 27.2 kΩ 7 ― 38 kΩ 5.9 9.8 13.7 kΩ 3 ― 19.2 kΩ No load (design goal) 1.54 1.63 1.71 V No load, receivable amplitude range is 250 kHz, when sine wave signal is applied. 0.3 ― 0.45 V (design goal) Detection frequency range DETON 19 Fosc = 4 MHz 236 ― 266 kHz Non-detection frequency (low frequency) DETOFF1 19 Fosc = 4 MHz ― ― 222 kHz Non-detection frequency (high frequency) DETOFF2 19 Fosc = 4 MHz 286 ― ― kHz SW1IN pin (pin 14) and SW1OUT pin (pin 15) Analog switch input voltage VINASW1 ― ― VSS ― VDD V Analog switch output voltage VOUTASW1 ― ― VSS ― VDD V OFF-leak current of analog switch 1 IOFFASW1 20 −1 ― 1 µA ON-resistance of analog switch 1 RONASW1 21 35 ― 105 Ω SCTL = H, SW1IN = VDD, SW1OUT = VSS SCTL = L, SW1IN = 5 V, SW1OUT = 0 V Current measure SW2IN pin (pin 11) and SW2OUT pin (pin 10) Analog switch input voltage VINASW2 ― ― VSS ― VDD V Analog switch output voltage VOUTASW2 ― ― VSS ― VDD V OFF-leak current of analog switch 2 IOFFASW2 20 −1 ― 1 µA ON-resistance of analog switch 2 RONASW2 21 35 ― 105 Ω 0.85 VDD ― VDD V SCTL = H, SW2IN = VDD, SW2OUT = VSS SCTL = L, SW2IN = 5 V, SW2OUT = 0 V Current measure SOUT+ pin (pin 13) and SOUT− pin (pin 12) Output voltage VOPP 22 Maximum voltage value at no load Pseudo sine wave output frequency FSIN 23 FOSC = 4 MHz ― 250 ― kHz Pseudo sine wave output start time tdON 23 SCTL = H → L ― ― 500 ns tdOFF 23 SCTL = L → H ― ― 1 µs ROUTSIN 24 No load 2.8 4 5.2 kΩ Pseudo sine wave output stop time Equivalent output impedance Note: One direction in which current flow into the IC should be + (sink) and the other direction in which current flow out from the IC should be − (drain). 8 2003-03-13 T6B70BF Test Circuit (1) Current consumption 4 MHz PG (2) A 1 OSCIN 5V ICC Oscillation frequency 1 to 10 MHz PG VDD 16 2 OSCOUT SW1OUT 15 3 FOUT SW1IN 14 4 SCTL 2 OSCOUT SW1OUT 15 Monitor Fosc SOUT+ 13 4 SCTL SOUT+ 13 5 RESET SOUT− 12 5 RESET SOUT− 12 6 AMPOUT SW2IN 11 6 AMPOUT SW2IN 11 SW2OUT 10 7 AMPIN (4) SOUT+ 13 5 RESET 6 AMPOUT 7 AMPIN 8 VSS VIN VIHRST VILRST 5V 1 OSCIN VDD 16 2 OSCOUT SW1OUT 15 3 FOUT SW1IN 14 4 SCTL SOUT+ 13 SOUT− 12 5 RESET SOUT− 12 SW2IN 11 6 AMPOUT SW2IN 11 VOLOUT V SW2OUT 10 7 AMPIN SW2OUT 10 8 VSS 9 DOUT Low to High input switching level High to Low input switching level 4 MHz PG IOL A +0.1 mA IOH −0.1 mA 4 SCTL 9 IIHROSC IILROSC VDD 16 1 OSCIN VIHOSC VOHOSC VILOSC 2 OSCOUT SW1OUT 15 SW1IN 14 DOUT High-level input current Low-level input current Low-level output voltage 5V 3 FOUT SW2OUT 10 8 VSS DOUT 9 High-level input voltage Low-level input voltage High-level output voltage (5) VDD 16 SW1IN 14 8 VSS V 1 OSCIN 3 FOUT 7 AMPIN (3) 5V (6) DOUT 9 High-level input current 5V 1 OSCIN 5V VDD 16 1 OSCIN VDD 16 2 OSCOUT SW1OUT 15 2 OSCOUT SW1OUT 15 3 FOUT SW1IN 14 3 FOUT SW1IN 14 4 SCTL SOUT+ 13 Monitor IIHRST 4 SCTL SOUT+ 13 5 RESET SOUT− 12 Monitor 6 AMPOUT 7 AMPIN 8 VSS A VIN SW2IN 11 SW2OUT 10 DOUT 5 RESET SOUT− 12 6 AMPOUT SW2IN 11 7 AMPIN 8 VSS 9 9 SW2OUT 10 DOUT 9 2003-03-13 T6B70BF Pull-up resistance 1 Pull-up resistance 2 (8) 5V 1 OSCIN Low to High input switching level High to Low input switching level 4 MHz PG VDD 16 2 OSCOUT SW1OUT 15 IILRRST1 3 FOUT IILRRST2 4 SCTL A SOUT+ 13 SOUT− 12 6 AMPOUT SW2IN 11 7 AMPIN (9) VIHSCTL VILSCTL SW2OUT 10 8 VSS VDD 16 2 OSCOUT SW1OUT 15 SW1IN 14 5 RESET 5V 1 OSCIN 3 FOUT SW1IN 14 4 SCTL SOUT+ 13 Monitor 5 RESET SOUT− 12 Monitor 6 AMPOUT SW2IN 11 7 AMPIN SW2OUT 10 8 VSS DOUT 9 High-level input current Low-level input current DOUT 9 (10) High-level output voltage 5V 1 OSCIN 4 SCTL SOUT+ 13 5 RESET SOUT− 12 6 AMPOUT SW2IN 11 7 AMPIN SW2OUT 10 8 VSS DOUT IOL +1.0 mA 4 SCTL SOUT+ 13 5 RESET SOUT− 12 6 AMPOUT SW2IN 11 SW2OUT 10 8 VSS 9 DOUT 4 MHz PG VDD 16 5V 1 OSCIN VDD 16 2 OSCOUT SW1OUT 15 2 OSCOUT SW1OUT 15 3 FOUT SW1IN 14 3 FOUT SW1IN 14 4 SCTL SOUT+ 13 4 SCTL SOUT+ 13 5 RESET SOUT− 12 5 RESET SOUT− 12 6 AMPOUT SW2IN 11 6 AMPOUT SW2IN 11 7 AMPIN 8 VSS 9 (12) High-level output voltage 5V VOLFOUT V SW1IN 14 7 AMPIN (11) Low-level output voltage 1 OSCIN VOHFOUT V 3 FOUT SW2OUT 10 DOUT 7 AMPIN 8 VSS 9 SW2OUT 10 DOUT 9 VOHDOUT V 10 −1.0 mA A VDD 16 2 OSCOUT SW1OUT 15 −1.0 mA OSCOUT SW1OUT 15 IIHSCTL 2 IILSCTL 3 FOUT SW1IN 14 VIN 5V VDD 16 IOH 1 OSCIN IOH (7) 2003-03-13 T6B70BF (13) Low-level output voltage 5V 1 OSCIN 4 MHz PG VDD 16 5V 1 OSCIN VDD 16 2 OSCOUT SW1OUT 15 2 OSCOUT SW1OUT 15 3 FOUT SW1IN 14 3 FOUT SW1IN 14 4 SCTL SOUT+ 13 4 SCTL SOUT+ 13 5 RESET SOUT− 12 5 RESET SOUT− 12 6 AMPOUT SW2IN 11 6 AMPOUT SW2IN 11 8 VSS SW2OUT 10 DOUT 9 Monitor IOL 7 AMPIN +1.0 mA 4 MHz PG (14) Input dynamic range 7 AMPIN VAMPIN SW2OUT 10 8 VSS DOUT 9 VOLDOUT V (15) Pull-up resistance 1 Pull-up resistance 2 (16) Pull-down resistance 1 Pull-down resistance 2 5V 1 OSCIN VDD 16 1 OSCIN 2 OSCOUT SW1OUT 15 3 FOUT SW1IN 14 3 FOUT SW1IN 14 4 SCTL SOUT+ 13 4 SCTL SOUT+ 13 7 AMPIN 8 VSS SOUT− 12 IIHRAPD1 5 RESET IIHRAPD2 6 AMPOUT SW2IN 11 SW2OUT 10 DOUT A VIN 9 (17) Amplifier input bias voltage 7 AMPIN 8 VSS SOUT− 12 SW2IN 11 SW2OUT 10 DOUT 9 (18) Amplifier input sensitivity 5V 1 OSCIN 4 MHz PG VDD 16 5V 1 OSCIN VDD 16 2 OSCOUT SW1OUT 15 2 OSCOUT SW1OUT 15 3 FOUT SW1IN 14 3 FOUT SW1IN 14 4 SCTL SOUT+ 13 4 SCTL SOUT+ 13 5 RESET SOUT− 12 5 RESET SOUT− 12 6 AMPOUT SW2IN 11 6 AMPOUT SW2IN 11 7 AMPIN VBIAS V VDD 16 2 OSCOUT SW1OUT 15 IILRAPU1 5 RESET IILRAPU2 6 AMPOUT A 5V 8 VSS SW2OUT 10 DOUT Monitor 250 kHz Vp-p sine wave 7 AMPIN 8 VSS 9 11 SW2OUT 10 DOUT 9 2003-03-13 T6B70BF (19) Detection frequency range Non-detection frequency (low frequency) Non-detection frequency (high frequency) Non-reception to reception detection time Reception to non-reception detection time (20) OFF-leak current of analog switch 1 OFF-leak current of analog switch 2 5V 5V VDD 16 1 OSCIN VDD 16 2 OSCOUT SW1OUT 15 2 OSCOUT SW1OUT 15 3 FOUT SW1IN 14 3 FOUT SW1IN 14 IOFFASW1 A SOUT+ 13 4 SCTL SOUT+ 13 5 RESET SOUT− 12 5 RESET SOUT− 12 IOFFASW2 6 AMPOUT SW2IN 11 6 AMPOUT SW2IN 11 200 to 300 kHz PG 7 AMPIN SW2OUT 10 Monitor TDET1 TDET2 DOUT 9 (21) ON-resistance of analog switch 1 ON-resistance of analog switch 2 VDD 16 2 OSCOUT SW1OUT 15 4 SCTL SOUT+ 13 5 RESET 6 AMPOUT 7 AMPIN SOUT+ 13 SOUT− 12 RONASW2 5 RESET SOUT− 12 SW2IN 11 6 AMPOUT SW2IN 11 SW2OUT 10 DOUT A 8 VSS SW1IN 14 4 SCTL SOUT+ 13 5 RESET SOUT− 12 6 AMPOUT SW2IN 11 4 MHz PG DOUT V VOPP 9 5V 1 OSCIN VDD 16 2 OSCOUT SW1OUT 15 FSIN Monitor DEGSOUT Monitor tdON tdOFF SW2OUT 10 DOUT SW2OUT 10 V VOPP (24) Equivalent output impedance VDD 16 3 FOUT 7 AMPIN 9 2 OSCOUT SW1OUT 15 8 VSS VDD 16 4 SCTL 5V 7 AMPIN 5V 1 OSCIN SW1IN 14 A (23) Pseudo sine wave output frequency Pseudo sine wave output start time Pseudo sine wave output stop time 1 OSCIN 9 3 FOUT 8 VSS 4 MHz PG DOUT 2 OSCOUT SW1OUT 15 5.0 V SW1IN 14 RONASW1 4 MHz PG 5.0 V 3 FOUT 8 VSS (22) Output voltage 5V 1 OSCIN SW2OUT 10 3 FOUT SW1IN 14 4 SCTL SOUT+ 13 5 RESET SOUT− 12 6 AMPOUT SW2IN 11 7 AMPIN 8 VSS 9 12 SW2OUT 10 DOUT A ROUTSIN A ROUTSIN 5.0 V 8 VSS 7 AMPIN A 5.0 V 4 SCTL DETON DETOFF1 DETOFF2 5.0 V 1 OSCIN 5.0 V 4 MHz PG 9 2003-03-13 T6B70BF Markings LOT CODE T6B70BF 13 2003-03-13 T6B70BF Package Dimensions Weight: 0.16 g (typ.) 14 2003-03-13 T6B70BF RESTRICTIONS ON PRODUCT USE 000707EBA · TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. · The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. · The products described in this document are subject to the foreign exchange and foreign trade laws. · The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. · The information contained herein is subject to change without notice. 15 2003-03-13