TC554161AFT-70,-85,-10,-70L,-85L,-10L TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 262,144-WORD BY 16-BIT STATIC RAM DESCRIPTION The TC554161AFT is a 4,194,304-bit static random access memory (SRAM) organized as 262,144 words by 16bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 5V ± 10% power supply. Advanced circuit technology provides both high speed and low power at an operating current of 10 mA/MHz (typ) and a minimum cycle time of 70 ns. It is automatically placed in low-power mode at 2 mA standby current (typ) when chip enable ( CE ) is asserted high. There are two control inputs. CE is used to select the device and for data retention control, and output enable ( OE ) provides fast memory access. Data byte control pin ( LB , UB ) provides lower and upper byte access. This device is well suited to various microprocessor system applications where high speed, low power and battery backup are required. The TC554161AFT is available in a plastic 54-pin thin-small-outline package (TSOP). FEATURES · · · · · · Low-power dissipation Operating: 55 mW/MHz (typical) Single power supply voltage of 5 V ± 10% Power down features using CE . Data retention supply voltage of 2 to 5.5 V Direct TTL compatibility for all inputs and outputs Standby Current (maximum): · TC554161AFT TC554161AFT -70,-85,-10 -70L,-85L,-10L 5.5 V 100 mA 50 mA 3.0 V 50 mA 25 mA PIN ASSIGNMENT (TOP VIEW) NC A3 A2 A1 A0 I/O16 I/O15 VDD GND I/O14 I/O13 UB CE OP R/W I/O12 I/O11 GND VDD I/O10 I/O9 NC A17 A16 A15 A14 A13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 A4 A5 A6 A7 NC I/O1 I/O2 VDD GND I/O3 I/O4 LB OE OP NC I/O5 I/O6 GND VDD I/O7 I/O8 A8 A9 A10 A11 A12 NC Access Times (maximum): · -70,-70L -85,-85L -10,-10L Access Time 70 ns 85 ns 100 ns CE Access Time 70 ns 85 ns 100 ns OE Access Time 35 ns 45 ns 50 ns Package: TSOP II54-P-400-0.80 (AFT) (Weight: 0.57 g typ) PIN NAMES A0~A17 I/O1~I/O16 Address Inputs Data Inputs/Outputs CE Chip Enable R/W Read/Write Control OE Output Enable LB , UB Data Byte Control VDD Power (+5 V) GND Ground NC No Connection OP* Option *: OP pin must be open of connected to GND. (Normal pinout) 2001-08-17 1/10 TC554161AFT-70,-85,-10,-70L,-85L,-10L BLOCK DIAGRAM DATA INPUT BUFFER I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 ROW ADDRESS DECODER ROW ADDRESS REGISTER VDD GND MEMORY CELL ARRAY 2,048 ´ 128 ´ 16 (4,194,304) DATA OUTPUT BUFFER I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 DATA INPUT BUFFER ROW ADDRESS BUFFER CE A0 A1 A2 A3 A11 A12 A13 A14 A15 A16 A17 DATA OUTPUT BUFFER SENSE AMP COLUMN ADDRESS DECODER COLUMN ADDERSS REGISTER CLOCK GENERATOR COLUMN ADDRESS BUFFER CE A4 A5 A6 A7 A8 A9 A10 R/W OE UB LB CE CE MAXIMUM RATINGS SYMBOL RATING VALUE UNIT VDD Power Supply Voltage -0.3~7.0 V VIN Input Voltage -0.3*~7.0 V VI/O Input/Output Voltage -0.5~VDD + 0.5 V PD Power Dissipation 0.6 W Tsolder Soldering Temperature (10s) 260 °C Tstg Storage Temperature -55~150 °C Topr Operating Temperature 0~70 °C *: -3.0 V when measured at a pulse width of 30ns 2001-08-17 2/10 TC554161AFT-70,-85,-10,-70L,-85L,-10L DC RECOMMENDED OPERATING CONDITIONS (Ta = 0° to 70°C) SYMBOL PARAMETER MIN TYP MAX UNIT VDD Power Supply Voltage 4.5 5.0 5.5 V VIH Input High Voltage 2.2 ¾ VDD + 0.3 V VIL Input Low Voltage -0.3* ¾ 0.8 V VDH Data Retention Supply Voltage 2.0 ¾ 5.5 V -3.0 V when measured at a pulse width of 30 ns *: DC CHARACTERISTICS (Ta = 0° to 70°C, VDD = 5 V ± 10%) SYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT VIN = 0 V~VDD ¾ ¾ ±1.0 mA ILO Input Leakage Current Output Leakage Current CE = VIH or R/W = VIL or OE = VIH, VOUT = 0 V~VDD ¾ ¾ ±1.0 mA IOH Output High Current VOH = 2.4 V -1.0 ¾ ¾ mA IOL Output Low Current VOL = 0.4 V 2.1 ¾ ¾ mA tcycle = 70 ns ¾ ¾ 110 tcycle = 85 ns, 100 ns ¾ ¾ 100 tcycle = 1 ms ¾ 15 ¾ tcycle = 70 ns CE = 0.2 V and R/W = VDD - 0.2 V, IOUT = 0 mA, tcycle = 85 ns, 100 ns Other Input = VDD - 0.2 V/0.2 V tcycle = 1 ms ¾ ¾ 100 ¾ ¾ 90 ¾ 10 ¾ CE = VIH ¾ ¾ 3 Ta = 25°C ¾ 2 ¾ Ta = 0~70°C ¾ ¾ 100 Ta = 25°C ¾ 2 5 Ta = 0~70°C ¾ ¾ 50 IIL CE = VIL and R/W = VIH, IOUT = 0 mA, Other Input = VIH/VIL IDDO1 Operating Current IDDO2 IDDS1 -70,-85,-10 Standby Current IDDS2 CE = VDD - 0.2 V, VDD = 2.0 V~5.5 V -70L,-85L,-10L mA mA mA mA CAPACITANCE (Ta = 25°C, f = 1 MHz) SYMBOL PARAMETER TEST CONDITION MAX UNIT CIN Input Capacitance VIN = GND 10 pF COUT Output Capacitance VOUT = GND 10 pF Note: This parameter is periodically sampled and is not 100% tested. 2001-08-17 3/10 TC554161AFT-70,-85,-10,-70L,-85L,-10L OPERATING MODE MODE Read Write CE L L OE L * R/W H L I/O9~I/O16 POWER UB L L Output Output IDDO H L High-Z Output IDDO L H Output High-Z IDDO L L Input Input IDDO H L High-Z Input IDDO L H Input High-Z IDDO High-Z High-Z IDDO High-Z High-Z IDDS L H H * * L * * H H H * * * * Output Deselect Standby I/O1~I/O8 LB * = don't care H = logic high L = logic low 2001-08-17 4/10 TC554161AFT-70,-85,-10,-70L,-85L,-10L AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta = 0° to 70°C, VDD = 5 V ± 10%) READ CYCLE TC554161AFT SYMBOL PARAMETER -70,-70L -85,-85L -10,-10L MIN MAX MIN MAX MIN MAX tRC Read Cycle Time 70 ¾ 85 ¾ 100 ¾ tACC Address Access Time ¾ 70 ¾ 85 ¾ 100 tCO Chip Enable Access Time ¾ 70 ¾ 85 ¾ 100 tOE Output Enable Access Time ¾ 35 ¾ 45 ¾ 50 tBA Data Byte Control Access Time ¾ 35 ¾ 45 ¾ 50 tOH Output Data Hold Time 10 ¾ 10 ¾ 10 ¾ tCOE Chip Enable Low to Output Active 10 ¾ 10 ¾ 10 ¾ tOEE Output Enable Low to Output Active 5 ¾ 5 ¾ 5 ¾ tBE Data Byte Control Low to Output Active 5 ¾ 5 ¾ 5 ¾ tOD Chip Enable High to Output High-Z ¾ 25 ¾ 30 ¾ 35 tODO Output Enable High to Output High-Z ¾ 25 ¾ 30 ¾ 35 tBD Data Byte Control High to Output High-Z ¾ 25 ¾ 30 ¾ 35 UNIT ns WRITE CYCLE TC554161AFT SYMBOL PARAMETER -70,-70L -85,-85L -10,-10L MIN MAX MIN MAX MIN MAX tWC Write Cycle Time 70 ¾ 85 ¾ 100 ¾ tWP Write Pulse Width 50 ¾ 55 ¾ 60 ¾ tCW Chip Enable to End of Write 60 ¾ 70 ¾ 80 ¾ tBW Data Byte Control to End of Write 50 ¾ 55 ¾ 60 ¾ tAS Address Setup Time 0 ¾ 0 ¾ 0 ¾ tWR Write Recovery Time 0 ¾ 0 ¾ 0 ¾ tDS Data Setup Time 30 ¾ 35 ¾ 40 ¾ tDH Data Hold Time 0 ¾ 0 ¾ 0 ¾ tOEW R/W High to Output Active 5 ¾ 5 ¾ 5 ¾ tODW R/W Low to Output High-Z ¾ 25 ¾ 30 ¾ 35 UNIT ns AC TEST CONDITIONS PARAMETER Output load Input pulse level TEST CONDITION 100 pF + 1 TTL Gate 0.6 V, 2.4 V Timing measurements 1.5 V Reference level 1.5 V t R, t F 5 ns 2001-08-17 5/10 TC554161AFT-70,-85,-10,-70L,-85L,-10L TIMING DIAGRANS READ CYCLE (See Note 1) tRC Address tACC tOH tCO CE tOE tOD OE tBA tODO UB , LB tBE tBD tOEE DOUT Hi-Z VALID DATA OUT tCOE Hi-Z INDETERMINATE WRITE CYCLE 1 (R/W CONTROLLED) (See Note 4) tWC Address tAS tWP tWR R/W tCW CE tBW UB , LB tODW DOUT (See Note 2) tOEW Hi-Z tDS DIN (See Note 5) (See Note 3) tDH VALID DATA IN (See Note 5) 2001-08-17 6/10 TC554161AFT-70,-85,-10,-70L,-85L,-10L WRITE CYCLE 2 ( CE CONTROLLED) (See Note 4) tWC Address tAS tWP tWR R/W tCW CE tBW UB , LB tBE DOUT tODW Hi-Z Hi-Z tCOE tDS DIN tDH VALID DATA IN (See Note 5) WRITE CYCLE 3 ( UB ,LB CONTROLLED) (See Note 5) (See Note 4) tWC Address tAS tWP tWR R/W tCW CE tBW UB , LB tCOE DOUT tODW Hi-Z Hi-Z tBE tDS DIN (See Note 5) tDH VALID DATA IN (See Note 5) 2001-08-17 7/10 TC554161AFT-70,-85,-10,-70L,-85L,-10L Note: (1) R/W remains HIGH for the read cycle. (2) If CE goes LOW coincident with or after R/W goes LOW, the outputs will remain at high impedance. (3) If CE goes HIGH coincident with or before R/W goes HIGH, the outputs will remain at high impedance. (4) If OE is HIGH during the write cycle, the outputs will remain at high impedance. (5) Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. DATA RETENTION CHARACTERISTICS (Ta = 0° to 70°C) SYMBOL VDH PARAMETER TYP MAX UNIT 2.0 ¾ 5.5 V VDH = 3.0 V ¾ ¾ 50 VDH = 5.5 V ¾ ¾ 100 VDH = 3.0 V ¾ ¾ 25* VDH = 5.5 V ¾ ¾ 50 Data Retention Supply Voltage -70,-85,-10 IDDS2 MIN Standby Current -70L,-85L,-10L mA tCDR Chip Deselect to Data Retention Mode Time 0 ¾ ¾ ns tR Recovery Time 5 ¾ ¾ ms *: 5 mA (max) at Ta = 0° to 40°C CE CONTROLLED DATA RETENTION MODE VDD DATA RETENTION MODE 4.5 V (See Note) (See Note) VIH tCDR CE VDD - 0.2 V tR GND Note: When CE is operating at the VIH level (2.2V), the standby current is given by IDDS1 during the transition of VDD from 4.5 to 2.4V. 2001-08-17 8/10 TC554161AFT-70,-85,-10,-70L,-85L,-10L PACKAGE DIMENSIONS Weight: 0.57 g (typ) 2001-08-17 9/10 TC554161AFT-70,-85,-10,-70L,-85L,-10L RESTRICTIONS ON PRODUCT USE 000707EBA · TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. · The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. · The products described in this document are subject to the foreign exchange and foreign trade laws. · The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. · The information contained herein is subject to change without notice. 2001-08-17 10/10