TDA9984A HDMI 1.3 transmitter with 1080p upscaler embedded Rev. 04 — 15 January 2009 Product data sheet 1. General description The TDA9984A is a High-Definition Multimedia Interface (HDMI) v. 1.3 transmitter with embedded 1080p upscaling functionality. It is backward compatible DVI 1.0 and can be connected to any DVI 1.0 and HDMI sink. It allows mixing a 3 × 8-bit RGB or YCbCr video stream with a pixel rate up to 150 MHz together with up to 4 × I2S-bus or one S/PDIF audio streams with an audio sampling rate up to 192 kHz. It supports Gamut boundary description (xvYCC), as well as HD audio, both HDMI 1.3 features. A programmable upscaling block allows creating a 1080p output from a standard definition input. An intrafield deinterlacer is included in the scaler. In order to be compatible with most applications, and thanks to the integration of a fully programmable input formatter and color space conversion block, the video input formats accepted also include YCbCr 4 : 4 : 4 (up to 3 × 8-bit), YCbCr 4 : 2 : 2 semi-planar (up to 2 × 12-bit) and YCbCr 4 : 2 : 2 compliant with ITU656 (up to 1 × 12-bit). In case of ITU656-like format, the input pixel clock can be made active on both edges. The TDA9984A includes a HDCP 1.2 compliant cipher block. The HDCP key are stored internally in a non-volatile OTP memory for maximum security. The TDA9984A includes a true I2C-bus master interface for DDC-bus communication for EDID purpose and HDCP purpose. The TDA9984A can be controlled by an I2C-bus interface. 2. Features n 3 × 8-bit video data input buses; CMOS and LV-TTL compatible n Horizontal synchronization, vertical synchronization and data enable inputs or VREF, HREF and FREF inputs which can be used for synchronization n Pixel rate clock input can be made active on one or both edges; selectable via I2C-bus n 4 × I2S-bus audio input channels, one S/PDIF channel; audio data rate up to 192 kHz per input for both standards n Dolby-True HD and DTS-HD High bit rate audio support through the use of the HBR interface n 250 MHz to 1.50 GHz TMDS transmitter operation n Programmable input formatter and upsampler/interpolator allows input of any of the 4 : 4 : 4 or 4 : 2 : 2 semi-planar and 4 : 2 : 2 ITU656-like formats TDA9984A NXP Semiconductors HDMI 1.3 transmitter with 1080p upscaler embedded n Programmable color space converter allows to input RGB video data and to output RGB or YCbCr 4 : 2 : 2 HDMI video data, or to input YCbCr video data and to output RGB or YCbCr 4 : 2 : 2 HDMI video data; converter can be passed n Upscaler allows creating a 1080p output from a standard definition input by using intelligent edge interpolation n Repetition of video samples as required by the HDMI standard n Insertion of HDMI additional information such as InfoFrames n Color gamut metadata packet transmission (xvYCC) n Downstream availability using hot plug detection (HPD input) and receiver detection (RxSense circuit) n Master DDC-bus interface n Deals with multiple levels of HDCP receivers and repeaters n Internal SHA-1 calculation n Controllable via I2C-bus n Low power dissipation n 1.8 V and 3.3 V power supplies n Power-down mode n Hard reset n Pin-to-pin compatible with TDA9983A/B and TDA9981A/B n Software compatible with TDA9983A/B and TDA9981A/B 3. Applications n n n n n n n n n n Set-top box DVD player DVD recorder AV receiver Home theater Digital video camera Digital still camera Personal video recorder Media center PCs, graphic cards Switches TDA9984A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 January 2009 2 of 40 TDA9984A NXP Semiconductors HDMI 1.3 transmitter with 1080p upscaler embedded 4. Quick reference data Table 1. Quick reference data VDD(3V3) = 3.3 V; VDD(1V8) = 1.8 V; VPP = 0 V; Tamb = −5 °C to +85 °C; unless otherwise specified. Typical values are measured at Tamb = 25 °C and fclk = 150 MHz. Symbol Parameter VPP VDDA(FRO)(3V3) Min Typ Max Unit programming voltage 5.0 5.25 5.5 V free running oscillator analog supply voltage (3.3 V) 3.0 3.3 3.6 V VDDA(PLL)(3V3) PLL analog supply voltage (3.3 V) 3.0 3.3 3.6 V VDDD(3V3) digital supply voltage (3.3 V) 3.0 3.3 3.6 V VDDH(3V3) HDMI supply voltage (3.3 V) 3.0 3.3 3.6 V VDDC(1V8) core supply voltage (1.8 V) 1.65 1.8 1.95 V VDDA(PLL)(1V8) PLL analog supply voltage (1.8 V) Pcons Conditions power consumption total power dissipation Ptot 1.65 1.8 1.95 V input 480p, output 1080p [1][3] - 500 630 mW input 1080i, output 1080p [1][2] - 742 940 mW input 1080p, output 1080p [1][4] - 320 400 mW input 480p, output 1080p [1][3] - 630 770 mW input 1080i, output 1080p [1][2] - 872 1080 mW input 1080p, output 1080p [1][4] - 450 540 mW - 30 40 mW TMDS output current added power dissipation in power-down mode Ppd [1] The maximum current consumption is in this configuration for this group of pins. [2] Video format: a) Input 1080i, YCbCr 4 : 2 : 2 embedded sync, 48 kHz S/PDIF 2 channels. b) Output 1080p, YCbCr 4 : 2 : 2, 48 kHz S/PDIF. [3] Video format: a) Input 480p, ITU656 embedded sync, 48 kHz S/PDIF 2 channels. b) Output 1080p, YCbCr 4 : 2 : 2, 48 kHz S/PDIF. [4] Video format: a) Input 1080p, YCbCr 4 : 2 : 2 embedded sync, 48 kHz S/PDIF 2 channels. b) Output 1080p, YCbCr 4 : 2 : 2, 48 kHz S/PDIF. 5. Ordering information Table 2. Ordering information Type number Package[1] Name TDA9984AHW HTQFP80 [1] Description Version plastic thermal enhanced thin quad flat package; 80 leads; body 12 × 12 × 1 mm; exposed die pad SOT841-4 A lead-free package is required to comply with the new legislation. TDA9984A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 January 2009 3 of 40 xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x TM AP0 to AP7 21 VDDD(3V3) VDDC(1V8) 13, 48, 71 3 4 to 11 59, 74 28, 34 12 23 16, 45 38 RST_N A1 A0 42 40 41 I2C_SCL I2C_SDA 43 44 I2C-BUS SLAVE HARD RESET AUDIO CONTENT AUDIO FIFO AUDIO PROCESSING ACLK VDDA(PLL)(3V3) VDDA(FRO)(3V3) VDDH(3V3) DDC_SDA DDC_SCL 19 20 DDC BUS MASTER CTS/N DATA ISLAND PACKET INSERTION ACR I2C-BUS REGISTERS VPB[7:0] VPC[7:0] VSYNC/VREF HSYNC/HREF DE/FREF CLOCK MANAGMENT 57, 58 61 to 65, 67 49 to 56 2 VIDEO INPUT PROCESSOR 1 80 30 29 HDCP PROCESSING 2 × 12-bit YCbCr 4 : 2 : 2 semi-planar 1 × 12-bit YCbCr 4 : 2 : 2 ITU656 UPSAMPLER 4:2:2 to 4:4:4 UPSCALER 4:2:2 VSSD 60, 73 VSSC HPD 25, 31, 37 VSSH 33 32 DOWNSAMPLER 4:4:4 to 4:2:2 COLOR SPACE CONVERTER RGB to YCbCr YCbCr to RGB TMDS SERIALIZER 36 35 24 TXC+ TXC− TX0+ TX0− TX1+ TX1− TX2+ TX2− EXT_SWING TDA9984AHW 22 VSSA(FRO)(3V3) 39 VSSA(PLL)(3V3) 46, 15 VSSA(PLL)(1V8) 001aag595 TDA9984A 4 of 40 © NXP B.V. 2009. All rights reserved. The device can handle HDCP based on 1.2 features. Block diagram 26 VHREF GENERATOR 14, 47, 72 Fig 1. 27 OTP MEMORY KEYS 3 × 8-bit RGB or YCbCr 4 : 4 : 4 2 × 12-bit YCbCr 4 : 2 : 2 semi-planar 1 × 12-bit YCbCr 4 : 2 : 2 ITU656 68 to 70 75 to 79 18 HDMI 1.3 transmitter with 1080p upscaler embedded Rev. 04 — 15 January 2009 VPA[7:0] HPD MANAGEMENT INT RxSENSE OTHER INFO-FRAME 66 17 AUDIO INFO-FRAME VIDEO INFO-FRAME VCLK INTERRUPT GENERATION NXP Semiconductors 6. Block diagram TDA9984A_4 Product data sheet VDDA(PLL)(1V8) VPP TDA9984A NXP Semiconductors HDMI 1.3 transmitter with 1080p upscaler embedded 61 VPB[5] 62 VPB[4] 63 VPB[3] 64 VPB[2] 65 VPB[1] 66 VCLK 67 VPB[0] 68 VPA[7] 69 VPA[6] 70 VPA[5] 71 VDDD(3V3) 72 VSSD 73 VSSC 74 VDDC(1V8) 75 VPA[4] 76 VPA[3] 77 VPA[2] 78 VPA[1] 79 VPA[0] 80 DE/FREF 7. Pinning information HSYNC/HREF 1 60 VSSC VSYNC/VREF 2 59 VDDC(1V8) VPP 3 58 VPB[6] AP7 4 57 VPB[7] AP6 5 56 VPC[0] AP5 6 55 VPC[1] AP4 7 54 VPC[2] AP3 8 53 VPC[3] AP2 9 52 VPC[4] AP1 10 51 VPC[5] TDA9984AHW AP0 11 50 VPC[6] ACLK 12 49 VPC[7] VDDD(3V3) 13 48 VDDD(3V3) VSSD 14 47 VSSD VSSA(PLL)(1V8) 15 46 VSSA(PLL)(1V8) VDDA(PLL)(1V8) 16 45 VDDA(PLL)(1V8) INT 17 44 I2C_SDA HPD 18 43 I2C_SCL Fig 2. A1 40 VSSA(PLL)(3V3) 39 VDDA(PLL)(3V3) 38 VSSH 37 TX2+ 36 TX2− 35 VDDH(3V3) 34 TX1+ 33 TX1− 32 VSSH 31 TX0+ 30 TX0− 29 VDDH(3V3) 28 TXC+ 27 TXC− 26 VSSH 25 EXT_SWING 24 VDDA(FRO)(3V3) 23 41 A0 TM 21 42 RST_N DDC_SCL 20 VSSA(FRO)(3V3) 22 DDC_SDA 19 001aag597 Pin configuration 7.1 Pin description Table 3. Pin description Symbol Pin Type[1] Description HSYNC/HREF 1 I horizontal synchronization or reference input VSYNC/VREF 2 I vertical synchronization or reference input VPP 3 P programming voltage for OTP memory; connect to ground for digital core in normal operation AP7 4 I audio port 7 input AP6 5 I audio port 6 input AP5 6 I audio port 5 input AP4 7 I audio port 4 input AP3 8 I audio port 3 input TDA9984A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 January 2009 5 of 40 TDA9984A NXP Semiconductors HDMI 1.3 transmitter with 1080p upscaler embedded Table 3. Pin description …continued Symbol Pin Type[1] Description AP2 9 I audio port 2 input AP1 10 I audio port 1 input AP0 11 I audio port 0 input ACLK 12 I audio clock input VDDD(3V3) 13 P digital supply voltage for I/O ports (3.3 V) VSSD 14 G digital ground for I/O ports VSSA(PLL)(1V8) 15 G analog ground for PLL VDDA(PLL)(1V8) 16 P PLL analog supply voltage (1.8 V) INT 17 O interrupt output; warns the external microprocessor that a special event has occurred HPD 18 I hot plug detect input; 5 V tolerant DDC_SDA 19 I/O DDC-bus data input/output; 5 V tolerant DDC_SCL 20 I DDC-bus clock input; 5 V tolerant TM 21 I internal test mode input; connect to ground VSSA(FRO)(3V3) 22 G analog ground for free running oscillator VDDA(FRO)(3V3) 23 P analog supply voltage for free running oscillator (3.3 V) EXT_SWING 24 I swing adjust input for TMDS output; a fixed resistor must be connected to VDDH(3V3) VSSH 25 G ground for TMDS (HDMI) transmitter TXC− 26 O negative clock channel for TMDS output TXC+ 27 O positive clock channel for TMDS output VDDH(3V3) 28 P supply voltage for TMDS (HDMI) transmitter (3.3 V) TX0− 29 O negative data channel 0 for TMDS output TX0+ 30 O positive data channel 0 for TMDS output VSSH 31 G ground for TMDS (HDMI) transmitter TX1− 32 O negative data channel 1 for TMDS output TX1+ 33 O positive data channel 1 for TMDS output VDDH(3V3) 34 P supply voltage for TMDS (HDMI) transmitter (3.3 V) TX2− 35 O negative data channel 2 for TMDS output TX2+ 36 O positive data channel 2 for TMDS output VSSH 37 G ground for TMDS (HDMI) transmitter VDDA(PLL)(3V3) 38 P analog supply voltage for PLL (3.3 V) VSSA(PLL)(3V3) 39 G analog ground for PLL A1 40 I I2C-bus slave address bit 1 input A0 41 I I2C-bus slave address bit 0 input RST_N 42 I hard reset input; active LOW I2C_SCL 43 I I2C-bus clock input I2C_SDA 44 I/O I2C-bus data input/output VDDA(PLL)(1V8) 45 P PLL analog supply voltage (1.8 V) VSSA(PLL)(1V8) 46 G analog ground for PLL VSSD 47 G digital ground for I/O ports TDA9984A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 January 2009 6 of 40 TDA9984A NXP Semiconductors HDMI 1.3 transmitter with 1080p upscaler embedded Table 3. Pin description …continued Symbol Pin Type[1] Description VDDD(3V3) 48 P digital supply voltage for I/O ports (3.3 V) VPC[7] 49 I video port C input bit 7 (MSB) VPC[6] 50 I video port C input bit 6 VPC[5] 51 I video port C input bit 5 VPC[4] 52 I video port C input bit 4 VPC[3] 53 I video port C input bit 3 VPC[2] 54 I video port C input bit 2 VPC[1] 55 I video port C input bit 1 VPC[0] 56 I video port C input bit 0 (LSB) VPB[7] 57 I video port B input bit 7 (MSB) VPB[6] 58 I video port B input bit 6 VDDC(1V8) 59 P supply voltage for digital core (1.8 V) VSSC 60 G ground for digital core VPB[5] 61 I video port B input bit 5 VPB[4] 62 I video port B input bit 4 VPB[3] 63 I video port B input bit 3 VPB[2] 64 I video port B input bit 2 VPB[1] 65 I video port B input bit 1 VCLK 66 I video pixel clock input VPB[0] 67 I video port B input bit 0 (LSB) VPA[7] 68 I video port A input bit 7 (MSB) VPA[6] 69 I video port A input bit 6 VPA[5] 70 I video port A input bit 5 VDDD(3V3) 71 P digital supply voltage for I/O ports (3.3 V) VSSD 72 G digital ground for I/O ports VSSC 73 G ground for digital core VDDC(1V8) 74 P supply voltage for digital core (1.8 V) VPA[4] 75 I video port A input bit 4 VPA[3] 76 I video port A input bit 3 VPA[2] 77 I video port A input bit 2 VPA[1] 78 I video port A input bit 1 VPA[0] 79 I video port A input bit 0 DE/FREF 80 I video data enable or field reference input [1] P = Power supply; G = Ground; I = Input; O = Output. TDA9984A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 January 2009 7 of 40 TDA9984A NXP Semiconductors HDMI 1.3 transmitter with 1080p upscaler embedded 8. Functional description The TDA9984A is designed to convert digital data (video and audio) provided by a Set-Top Box or DVD into an HDMI output, which could be used in TV with HDMI or DVI input. The TDA9984A is able to output HDMI with the formats: • RGB • YCbCr 4 : 4 : 4 • YCbCr 4 : 2 : 2 The video data input formats are: • • • • RGB YCbCr 4 : 4 : 4 YCbCr 4 : 2 : 2 semi-planar YCbCr 4 : 2 : 2 ITU656-like It can also handle audio formats: • 4 × I2S-bus channels • One S/PDIF channel • Dolby-True HD and DTS-HD through the use of HBR interface 8.1 Video processing The TDA9984A has three video input ports VPA[7:0], VPB[7:0] and VPC[7:0] and can handle any of the following video input modes: • • • • RGB with 8-bit for each component YCbCr 4 : 4 : 4 with 8-bit for each component YCbCr 4 : 2 : 2 semi-planar with up to 12-bit for each component (Y, Cb and Cr) YCbCr 4 : 2 : 2 ITU656 with up to 12-bit data depth The TDA9984A can be set to latch data at either the rising or the falling edge. 8.1.1 Internal assignment The aim of the video input processor is to map internally the incoming data to the corresponding mode, which can be handled by the video processing. The device expects to have a big endian digital stream at its input. The internal signal name VP[23:0] is assigned depending on the input mode as defined in Figure 3. VPA[7:0] VPB[7:0] VIDEO INPUT PROCESSOR VPC[7:0] Fig 3. 001aag599 Internal assignment of VP[23:0] TDA9984A_4 Product data sheet VP[23:0] © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 January 2009 8 of 40 TDA9984A NXP Semiconductors HDMI 1.3 transmitter with 1080p upscaler embedded The device can swap and invert (in case of a little endian stream) the incoming video data via the I2C-bus registers VIP_CNTRL_0, VIP_CNTRL_1 and VIP_CNTRL_2 (page 00h) to match the expectation of the video processing block; see Table 4. When input ports are not used, it is possible to map them to internal ground via the I2C-bus registers ENA_VP_0, ENA_VP_1, ENA_VP_2, GND_VP_0, GND_VP_1 and GND_VP_2 (page 00h). Table 4. Internal assignment Internal port RGB YCbCr 4:4:4 4 : 2 : 2 semi-planar 4 : 2 : 2 ITU656-like VP[23] G[7] Y[7] Y[11] YCbCr[11] VP[22] G[6] Y[6] Y[10] YCbCr[10] VP[21] G[5] Y[5] Y[9] YCbCr[9] VP[20] G[4] Y[4] Y[8] YCbCr[8] VP[19] G[3] Y[3] Y[7] YCbCr[7] VP[18] G[2] Y[2] Y[6] YCbCr[6] VP[17] G[1] Y[1] Y[5] YCbCr[5] VP[16] G[0] Y[0] Y[4] YCbCr[4] VP[15] B[7] Cb[7] Y[3] YCbCr[3] VP[14] B[6] Cb[6] Y[2] YCbCr[2 VP[13] B[5] Cb[5] Y[1] YCbCr[1] VP[12] B[4] Cb[4] Y[0] YCbCr[0] VP[11] B[3] Cb[3] CbCr[11] - VP[10] B[2] Cb[2] CbCr[10] - VP[9] B[1] Cb[1] CbCr[9] - VP[8] B[0] Cb[0] CbCr[8] - VP[7] R[7] Cr[7] CbCr[7] - VP[6] R[6] Cr[6] CbCr[6] - VP[5] R[5] Cr[5] CbCr[5] - VP[4] R[4] Cr[4] CbCr[4] - VP[3] R[3] Cr[3] CbCr[3] - VP[2] R[2] Cr[2] CbCr[2] - VP[1] R[1] Cr[7] CbCr[1] - VP[0] R[0] Cr[0] CbCr[0] - 8.1.2 Input format mappings See Table 5 for more information concerning input format supported. TDA9984A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 January 2009 9 of 40 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Inputs of video input formatter Space color Format Channels Sync Rising edge RGB 3 × 8-bit external X 4:4:4 Falling edge Double edge[1] X embedded X external X X YCbCr 4:4:4 3 × 8-bit X embedded X external X X YCbCr 4:2:2 up to 1 × 12-bit semi-planar X embedded X X X up to 2 × 12-bit semi-planar external X embedded X X X Double edge means both rising and falling edges. Transmission Pixel clock input format (MHz) Maximum input format Reference - 150 MHz - Section 8.1.2.1 - 150 MHz - - 150 MHz - - 150 MHz - - 150 MHz - - 150 MHz - - 150 MHz - Section 8.1.2.2 - 150 MHz - ITU656-like 54.054 MHz 480p/576p ITU656-like 54.054 MHz 480p/576p ITU656-like 27.027 MHz 480p/576p Section 8.1.2.4 ITU656-like 54.054 MHz 480p/576p Section 8.1.2.5 ITU656-like 54.054 MHz 480p/576p ITU656-like 27.027 MHz 480p/576p Section 8.1.2.6 SMPTE293M 148.5 MHz 1080p Section 8.1.2.7 SMPTE293M 148.5 MHz 1080p SMPTE293M 148.5 MHz 1080p SMPTE293M 148.5 MHz 1080p Section 8.1.2.3 Section 8.1.2.8 TDA9984A 10 of 40 © NXP B.V. 2009. All rights reserved. HDMI 1.3 transmitter with 1080p upscaler embedded Rev. 04 — 15 January 2009 X [1] NXP Semiconductors TDA9984A_4 Product data sheet Table 5. TDA9984A NXP Semiconductors HDMI 1.3 transmitter with 1080p upscaler embedded 8.1.2.1 RGB 4 : 4 : 4 external sync input (rising edge) Table 6. RGB 4 : 4 : 4 mapping Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h. Video port A Video port B Video port C Control Pin RGB 4 : 4 : 4 Pin RGB 4 : 4 : 4 Pin RGB 4 : 4 : 4 Pin RGB 4 : 4 : 4 VPA[0] B[0] VPB[0] G[0] VPC[0] R[0] HSYNC/HREF used VPA[1] B[1] VPB[1] G[1] VPC[1] R[1] VSYNC/VREF used VPA[2] B[2] VPB[2] G[2] VPC[2] R[2] DE/FREF used VPA[3] B[3] VPB[3] G[3] VPC[3] R[3] VPA[4] B[4] VPB[4] G[4] VPC[4] R[4] VPA[5] B[5] VPB[5] G[5] VPC[5] R[5] VPA[6] B[6] VPB[6] G[6] VPC[6] R[6] VPA[7] B[7] VPB[7] G[7] VPC[7] R[7] VCLK CONTROL INPUTS HSYNC/HREF VSYNC/VREF DE/FREF VPA[7:0] B0[7:0] B1[7:0] B2[7:0] B3[7:0] ... Bxxx[7:0] Bxxx[7:0] VPB[7:0] G0[7:0] G1[7:0] G2[7:0] G3[7:0] ... Gxxx[7:0] Gxxx[7:0] VPC[7:0] R0[7:0] R1[7:0] R2[7:0] R3[7:0] ... Rxxx[7:0] Rxxx[7:0] 001aag380 DE could also be generated from HSYNC/HREF and VSYNC/VREF Fig 4. Pixel encoding RGB 4 : 4 : 4 external sync input (rising edge) TDA9984A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 January 2009 11 of 40 TDA9984A NXP Semiconductors HDMI 1.3 transmitter with 1080p upscaler embedded 8.1.2.2 YCbCr 4 : 4 : 4 external sync input (rising edge) Table 7. YCbCr 4 : 4 : 4 mapping Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h. Video port A Video port B Video port C Control Pin YCbCr 4 : 4 : 4 Pin YCbCr 4 : 4 : 4 Pin YCbCr 4 : 4 : 4 Pin YCbCr 4 : 4 : 4 VPA[0] Cb[0] VPB[0] Y[0] VPC[0] Cr[0] HSYNC/HREF used VPA[1] Cb[1] VPB[1] Y[1] VPC[1] Cr[1] VSYNC/VREF used VPA[2] Cb[2] VPB[2] Y[2] VPC[2] Cr[2] DE/FREF used VPA[3] Cb[3] VPB[3] Y[3] VPC[3] Cr[3] VPA[4] Cb[4] VPB[4] Y[4] VPC[4] Cr[4] VPA[5] Cb[5] VPB[5] Y[5] VPC[5] Cr[5] VPA[6] Cb[6] VPB[6] Y[6] VPC[6] Cr[6] VPA[7] Cb[7] VPB[7] Y[7] VPC[7] Cr[7] VCLK CONTROL INPUTS HSYNC/HREF VSYNC/VREF DE/FREF VPA[7:0] Cb0[7:0] Cb1[7:0] Cb2[7:0] Cb3[7:0] ... Cbxxx[7:0] Cbxxx[7:0] VPB[7:0] Y0[7:0] Y1[7:0] Y2[7:0] Y3[7:0] ... Yxxx[7:0] Yxxx[7:0] VPC[7:0] Cr0[7:0] Cr1[7:0] Cr2[7:0] Cr3[7:0] ... Crxxx[7:0] Crxxx[7:0] 001aag381 DE could also be generated from HSYNC/HREF and VSYNC/VREF Fig 5. Pixel encoding YCbCr 4 : 4 : 4 external sync input (rising edge) TDA9984A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 January 2009 12 of 40 TDA9984A NXP Semiconductors HDMI 1.3 transmitter with 1080p upscaler embedded 8.1.2.3 YCbCr 4 : 2 : 2 ITU656-like external sync input (rising edge) Table 8. YCbCr 4 : 2 : 2 ITU656-like rising edge mapping Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h. Video port A Video port B Control Pin YCbCr 4 : 2 : 2 (ITU656-like) Pin YCbCr 4 : 2 : 2 (ITU656-like) Pin VPA[0] Cb[0] Y0[0] Cr[0] Y1[0] VPB[0] Cb[4] Y0[4] Cr[4] Y1[4] HSYNC/HREF used VPA[1] Cb[1] Y0[1] Cr[1] Y1[1] VPB[1] Cb[5] Y0[5] Cr[5] Y1[5] VSYNC/VREF used VPA[2] Cb[2] Y0[2] Cr[2] Y1[2] VPB[2] Cb[6] Y0[6] Cr[6] Y1[6] DE/FREF VPA[3] Cb[3] Y0[3] Cr[3] Y1[3] VPB[3] Cb[7] Y0[7] Cr[7] Y1[7] VPA[4] - - - - VPB[4] Cb[8] Y0[8] Cr[8] Y1[8] VPA[5] - - - - VPB[5] Cb[9] Y0[9] Cr[9] Y1[9] VPA[6] - - - - VPB[6] Cb[10] Y0[10] Cr[10] Y1[10] VPA[7] - - - - VPB[7] Cb[11] Y0[11] Cr[11] Y1[11] YCbCr 4 : 2 : 2 used VCLK CONTROL INPUTS HSYNC/HREF VSYNC/VREF DE/FREF VPB[7:0]; VPA[3:0] Cb0[11:0] Y0[11:0] Cr0[11:0] Y1[11:0] ... Crxxx[11:0] Yxxx[11:0] 001aag383 Fig 6. Pixel encoding YCbCr 4 : 2 : 2 ITU656-like external sync input (rising edge) TDA9984A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 January 2009 13 of 40 TDA9984A NXP Semiconductors HDMI 1.3 transmitter with 1080p upscaler embedded 8.1.2.4 YCbCr 4 : 2 : 2 ITU656-like external sync input (rising and falling) Table 9. YCbCr 4 : 2 : 2 ITU656-like double edge mapping Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h. Video port A Video port B Control Pin YCbCr 4 : 2 : 2 (ITU656-like) Pin YCbCr 4 : 2 : 2 (ITU656-like) Pin YCbCr 4 : 2 : 2 VPA[0] Cb[0] Y0[0] Cr[0] Y1[0] VPB[0] Cb[4] Y0[4] Cr[4] Y1[4] HSYNC/HREF used VPA[1] Cb[1] Y0[1] Cr[1] Y1[1] VPB[1] Cb[5] Y0[5] Cr[5] Y1[5] VSYNC/VREF used VPA[2] Cb[2] Y0[2] Cr[2] Y1[2] VPB[2] Cb[6] Y0[6] Cr[6] Y1[6] DE/FREF used VPA[3] Cb[3] Y0[3] Cr[3] Y1[3] VPB[3] Cb[7] Y0[7] Cr[7] Y1[7] VPA[4] - - - - VPB[4] Cb[8] Y0[8] Cr[8] Y1[8] VPA[5] - - - - VPB[5] Cb[9] Y0[9] Cr[9] Y1[9] VPA[6] - - - - VPB[6] Cb[10] Y0[10] Cr[10] Y1[10] VPA[7] - - - - VPB[7] Cb[11] Y0[11] Cr[11] Y1[11] VCLK CONTROL INPUTS HSYNC/HREF VSYNC/VREF DE/FREF VPB[7:0]; VPA[3:0] Cb0[11:0] Y0[11:0] Cr0[11:0] Y1[11:0] ... Crxxx[11:0] Yxxx[11:0] 001aag382 Fig 7. Pixel encoding YCbCr 4 : 2 : 2 ITU656-like external sync input (rising and falling) TDA9984A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 January 2009 14 of 40 TDA9984A NXP Semiconductors HDMI 1.3 transmitter with 1080p upscaler embedded 8.1.2.5 YCbCr 4 : 2 : 2 ITU656-like embedded sync input (rising edge) Table 10. YCbCr 4 : 2 : 2 ITU656-like embedded rising edge mapping Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h. Video port A Video port B Control Pin YCbCr 4 : 2 : 2 (ITU656-like) Pin YCbCr 4 : 2 : 2 (ITU656-like) Pin YCbCr 4 : 2 : 2 VPA[0] Cb[0] Y0[0] Cr[0] Y1[0] VPB[0] Cb[4] Y0[4] Cr[4] Y1[4] HSYNC/HREF not used VPA[1] Cb[1] Y0[1] Cr[1] Y1[1] VPB[1] Cb[5] Y0[5] Cr[5] Y1[5] VSYNC/VREF not used VPA[2] Cb[2] Y0[2] Cr[2] Y1[2] VPB[2] Cb[6] Y0[6] Cr[6] Y1[6] DE/FREF not used VPA[3] Cb[3] Y0[3] Cr[3] Y1[3] VPB[3] Cb[7] Y0[7] Cr[7] Y1[7] VPA[4] - - - - VPB[4] Cb[8] Y0[8] Cr[8] Y1[8] VPA[5] - - - - VPB[5] Cb[9] Y0[9] Cr[9] Y1[9] VPA[6] - - - - VPB[6] Cb[10] Y0[10] Cr[10] Y1[10] VPA[7] - - - - VPB[7] Cb[11] Y0[11] Cr[11] Y1[11] VCLK VPB[7:0]; VPA[3:0] Cb0[11:0] Y0[11:0] Cr0[11:0] Y1[11:0] ... Crxxx[11:0] Yxxx[11:0] 001aag385 Fig 8. Pixel encoding YCbCr 4 : 2 : 2 ITU656-like embedded sync input (rising edge) TDA9984A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 January 2009 15 of 40 TDA9984A NXP Semiconductors HDMI 1.3 transmitter with 1080p upscaler embedded 8.1.2.6 YCbCr 4 : 2 : 2 ITU656-like embedded sync input (rising and falling) Table 11. YCbCr 4 : 2 : 2 ITU656-like embedded double edge mappings Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h. Video port A Video port B Pin YCbCr 4 : 2 : 2 (ITU656-like) Pin VPA[0] Cb[0] Y0[0] Cr[0] Y1[0] VPA[1] Cb[1] Y0[1] Cr[1] VPA[2] Cb[2] Y0[2] VPA[3] Cb[3] Y0[3] VPA[4] - VPA[5] Control YCbCr 4 : 2 : 2 (ITU656-like) Pin YCbCr 4 : 2 : 2 VPB[0] Cb[4] Y0[4] Cr[4] Y1[4] HSYNC/HREF not used Y1[1] VPB[1] Cb[5] Y0[5] Cr[5] Y1[5] VSYNC/VREF not used Cr[2] Y1[2] VPB[2] Cb[6] Y0[6] Cr[6] Y1[6] DE/FREF Cr[3] Y1[3] VPB[3] Cb[7] Y0[7] Cr[7] Y1[7] - - - VPB[4] Cb[8] Y0[8] Cr[8] Y1[8] - - - - VPB[5] Cb[9] Y0[9] Cr[9] Y1[9] VPA[6] - - - - VPB[6] Cb[10] Y0[10] Cr[10] Y1[10] VPA[7] - - - - VPB[7] Cb[11] Y0[11] Cr[11] Y1[11] not used VCLK VPB[7:0]; VPA[3:0] Cb0[11:0] Y0[11:0] Cr0[11:0] Y1[11:0] ... Crxxx[11:0] Yxxx[11:0] 001aag384 Fig 9. Pixel encoding YCbCr 4 : 2 : 2 ITU656-like embedded sync input (rising and falling) TDA9984A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 January 2009 16 of 40 TDA9984A NXP Semiconductors HDMI 1.3 transmitter with 1080p upscaler embedded 8.1.2.7 YCbCr 4 : 2 : 2 semi-planar external input (rising edge) Table 12. YCbCr 4 : 2 : 2 semi-planar rising edge mapping Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 14h. Video port A Video port B Video port C Control Pin YCbCr 4 : 2 : 2 semi-planar Pin YCbCr 4 : 2 : 2 semi-planar Pin YCbCr 4 : 2 : 2 semi-planar Pin VPA[0] Y0[0] Y1[0] VPB[0] Y0[4] Y1[4] VPC[0] Cb[4] Cr[4] HSYNC/HREF used VPA[1] Y0[1] Y1[1] VPB[1] Y0[5] Y1[5] VPC[1] Cb[5] Cr[5] VSYNC/VREF used VPA[2] Y0[2] Y1[2] VPB[2] Y0[6] Y1[6] VPC[2] Cb[6] Cr[6] DE/FREF VPA[3] Y0[3] Y1[3] VPB[3] Y0[7] Y1[7] VPC[3] Cb[7] Cr[7] VPA[4] Cb[0] Cr[0] VPB[4] Y0[8] Y1[8] VPC[4] Cb[8] Cr[8] VPA[5] Cb[1] Cr[1] VPB[5] Y0[9] Y1[9] VPC[5] Cb[9] Cr[9] VPA[6] Cb[2] Cr[2] VPB[6] Y0[10] Y1[10] VPC[6] Cb[10] Cr[10] VPA[7] Cb[3] Cr[3] VPB[7] Y0[11] Y1[11] VPC[7] Cb[11] Cr[11] YCbCr 4:2:2 used VCLK CONTROL INPUTS HSYNC/HREF VSYNC/VREF DE/FREF VPB[7:0]; VPA[3:0] Y0[11:0] Y1[11:0] Y2[11:0] Y3[11:0] Y4[11:0] Y5[11:0] ... VPC[7:0]; VPA[7:4] Cb0[11:0] Cr0[11:0] Cb2[11:0] Cr2[11:0] Cb4[11:0] Cr4[11:0] ... 001aag386 Fig 10. Pixel encoding YCbCr 4 : 2 : 2 semi-planar external input (rising edge) TDA9984A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 January 2009 17 of 40 TDA9984A NXP Semiconductors HDMI 1.3 transmitter with 1080p upscaler embedded 8.1.2.8 YCbCr 4 : 2 : 2 semi-planar embedded sync input (rising edge) Table 13. YCbCr 4 : 2 : 2 semi-planar embedded rising edge mapping Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 14h. Video port A Video port B Video port C Control Pin YCbCr 4 : 2 : 2 semi-planar Pin YCbCr 4 : 2 : 2 semi-planar Pin YCbCr 4 : 2 : 2 semi-planar Pin VPA[0] Y0[0] Y1[0] VPB[0] Y0[4] Y1[4] VPC[0] Cb[4] Cr[4] HSYNC/HREF not used VPA[1] Y0[1] Y1[1] VPB[1] Y0[5] Y1[5] VPC[1] Cb[5] Cr[5] VSYNC/VREF not used VPA[2] Y0[2] Y1[2] VPB[2] Y0[6] Y1[6] VPC[2] Cb[6] Cr[6] DE/FREF VPA[3] Y0[3] Y1[3] VPB[3] Y0[7] Y1[7] VPC[3] Cb[7] Cr[7] VPA[4] Cb[0] Cr[0] VPB[4] Y0[8] Y1[8] VPC[4] Cb[8] Cr[8] VPA[5] Cb[1] Cr[1] VPB[5] Y0[9] Y1[9] VPC[5] Cb[9] Cr[9] VPA[6] Cb[2] Cr[2] VPB[6] Y0[10] Y1[10] VPC[6] Cb[10] Cr[10] VPA[7] Cb[3] Cr[3] VPB[7] Y0[11] Y1[11] VPC[7] Cb[11] Cr[11] YCbCr 4:2:2 not used VCLK VPB[7:0]; VPA[3:0] Y0[11:0] Y1[11:0] Y2[11:0] Y3[11:0] Y4[11:0] Y5[11:0] ... VPC[7:0]; VPA[7:4] Cb0[11:0] Cr0[11:0] Cb2[11:0] Cr2[11:0] Cb4[11:0] Cr4[11:0] ... 001aag387 Fig 11. Pixel encoding YCbCr 4 : 2 : 2 semi-planar embedded sync input (rising edge) TDA9984A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 January 2009 18 of 40 TDA9984A NXP Semiconductors HDMI 1.3 transmitter with 1080p upscaler embedded 8.1.3 Synchronization The TDA9984A can be synchronized with external input signals HSYNC and VSYNC or with extraction of the sync information from embedded sync codes (SAV/EAV) inside the video. 8.1.3.1 Timing extraction generator This block can extract the synchronization signals HREF, VREF and FREF from SAV and EAV in case of embedded synchronization in the data stream. Synchronization signals can be embedded in YCbCr 4 : 2 : 2 ITU656 (up to 1 × 12-bit) and semi-planar (up to 2 × 12-bit). 8.1.3.2 Data enable generator TDA9984A contains a Data Enable (DE) generator. This circuit generates an internal DE signal for a system which does not provide one. The DE generator is controlled via the I2C-bus register. 8.1.4 Input and output video format Due to the flexible video input formatter, the TDA9984A can accept a large range of inputs formats. This flexibility allows the TDA9984A to be compatible with the maximum number of MPEG decoders. Moreover, these input formats may be changed in many ways (space color converter, upsampler and scaler) to be transmitted across the HDMI link. Table 14 gives the possible inputs and outputs. Table 14. Inputs and outputs capability Input Scaler Space color Format Channels RGB 3 × 8-bit YCbCr YCbCr 4:4:4 4:4:4 4:2:2 3 × 8-bit up to 1 × 12-bit semi-planar up to 2 × 12-bit semi-planar no scaling no scaling scaling scaling Output Space color Format Channels RGB 4:4:4 3 × 8-bit YCbCr 4:4:4 3 × 8-bit YCbCr 4:2:2 2 × 12-bit RGB 4:4:4 3 × 8-bit YCbCr 4:4:4 3 × 8-bit YCbCr 4:2:2 2 × 12-bit RGB 4:4:4 3 × 8-bit YCbCr 4:4:4 3 × 8-bit YCbCr 4:2:2 2 × 12-bit RGB 4:4:4 3 × 8-bit YCbCr 4:4:4 3 × 8-bit YCbCr 4:2:2 2 × 12-bit 8.1.5 Scaler unit 8.1.5.1 Scaler features The scaler unit has the following features: • Up-scaling only: to expand input image horizontally and vertically • Deinterlacer embedded (no need of output memory) • Data processing: 12-bit data width TDA9984A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 January 2009 19 of 40 TDA9984A NXP Semiconductors HDMI 1.3 transmitter with 1080p upscaler embedded • Maximum output operating frequency is 148.5 MHz; HDTV supported 1080p both PAL and NTSC • Input video standards YCbCr 4 : 2 : 2 semi-planar and ITU656 (no RGB, nor YCbCr 4 : 4 : 4) 8.1.5.2 Input and output video scaler The scaler will convert the standard definition (high definition respectively) video signals (480i/576i, 480p/576p and 720p, 1080i respectively) into 1080p as described in Figure 12. Remark: All 4 : 2 : 2 input video formats can be bypassed, as well as all RGB and YCbCr 4 : 4 : 4 input data, which will be directly fed to the color space converter. 31 × 1080p × 720 1920 20 × 1080i 1920 21, 22 (PAL) 19 × 720p 576i 17, 18 × 576p 720 1280 16 × 720 × 1080p 5 × 1080i 1920 1920 4 × 720p 480i 2, 3 × 480p 720 FORMAT 861B VIDEO STANDARD INPUT 1280 FORMAT 861B 6, 7 (NTSC) VIDEO STANDARD OUTPUT 2, 3 720 × 480p (1) (2) (3) (2) 4 1280 × 720p (1) (2) 5 1920 × 1080i 6, 7 (NTSC) 720 × 16 1920 × 1080p 17, 18 720 × 576p (1) (2) (3) (2) 19 1280 × 720p (1) (2) 20 1920 × 1080i 21, 22 (PAL) 720 × 31 1920 × 1080p 480i 576i (1) (4) (4) (5) (6) (1) (5) (1) (1) (4) (4) (5) (6) (1) (5) (1) 001aag603 All upscaling modes are available only for YCbCr 4 : 2 : 2 input format. (1) Pass-through (2) Upscaling (3) Upscaling and interlacing (4) Deinterlacing (5) Deinterlacing and upscaling (6) Deinterlacing, upscaling and interlacing Fig 12. Input and output video scaler 8.1.6 Upsampler The incoming YCbCr 4 : 2 : 2 (2 × 12-bit) data stream format can be upsampled into an 8-bit YCbCr 4 : 4 : 4 (3 × 8-bit) data stream by repeating or linearly interpolating the chrominance pixels. TDA9984A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 January 2009 20 of 40 TDA9984A NXP Semiconductors HDMI 1.3 transmitter with 1080p upscaler embedded 8.1.7 Color space converter The color-space converter is used to convert input video data from one type to another color space (e.g. RGB to YCbCr and YCbCr to RGB). This block can be bypassed and each coefficient is programmable by the I2C-bus registers. C 11 C 12 C 13 GY Oin GY YG CrR = C 21 C 22 C 23 × RCr + Oin RCr CbB C 31 C 32 C 33 BCb Oin BCb Oout YG + Oout CrR Oout CbB (1) 8.1.8 Downsampler This block works only with YCbCr input format. These filters downsample the Cb and Cr signals by a factor of two. A delay is added on the G/Y channel, which corresponds to the pipeline delay of the filters, to put the Y channel in phase with the Cb and Cr channel. 8.2 Audio processing The TDA9984A is compatible with audio features as per HDMI specification, Rev. 1.3: • S/PDIF • I2S-bus up to four channels • Dolby-True HD and DTS-HD through the use of HBR interface S/PDIF, I2S-bus or HBR can be selected via the I2C-bus. Only one audio format can be used at a same time. Table 15 shows the audio port allocation. Table 15. Audio port Audio port configuration Format S/PDIF I2S-bus HBR AP0 - WS (word select) WS (word select) AP1 - I2S-bus channel 0 HBR channel 0 - I2S-bus channel 1 HBR channel 1 AP3 - I2S-bus channel 2 HBR channel 2 AP4 - I2S-bus channel 3 HBR channel 3 AP5 MCLK - - AP6 S/PDIF input - - AP7 AUX (internal test) AUX (internal test) AUX (internal test) ACLK - SCK SCK AP2 All audio ports are LV-TTL compatible. It is possible to map internally an unused port to internal ground via the I2C-bus registers ENA_APx and GND_APx on page 00h (both audio inputs and clock input as well). 8.2.1 S/PDIF The audio port AP6 is used for this feature. In this format, the TDA9984A supports 2-channel uncompressed PCM data (IEC 60958) layout 0, or compressed bit stream up to 8 multi-channels (Dolby Digital, DTS, AC3, etc.) layout 1. TDA9984A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 January 2009 21 of 40 TDA9984A NXP Semiconductors HDMI 1.3 transmitter with 1080p upscaler embedded The TDA9984A is able to recover the original clock from the S/PDIF signal (no need of external clock). In addition, it can also use an external clock to decode the S/PDIF signal. 8.2.2 I2S-bus There are 4 × I2S-bus stereo inputs channels (AP1, AP2, AP3 and AP4) which allow carrying eight uncompressed audio channels. The I2S-bus input interface receives an I2S-bus signal including serial data in, word select and serial clock. Various I2S-bus formats are supported and can be selected by setting the appropriate bits of the register. Typical waveforms for the I2S-bus signals at 64fs are given in Figure 13. DATA LEFT CHANNEL (n−1) RIGHT CHANNEL (n−1) LEFT CHANNEL (n) RIGHT CHANNEL (n) LEFT CHANNEL (n+1) RIGHT CHANNEL (n+1) WS MSB 24-bit audio sample word LSB 0 0 0 ACLK(64fs) 001aag607 a. Philips format DATA LEFT CHANNEL (n−1) RIGHT CHANNEL (n−1) LEFT CHANNEL (n) RIGHT CHANNEL (n) LEFT CHANNEL (n+1) RIGHT CHANNEL (n+1) WS MSB 24-bit audio sample word LSB 0 0 0 ACLK(64fs) 001aag608 b. Left justified format DATA LEFT CHANNEL (n−1) RIGHT CHANNEL (n−1) LEFT CHANNEL (n) RIGHT CHANNEL (n) LEFT CHANNEL (n+1) RIGHT CHANNEL (n+1) WS 0 0 0 MSB 24-bit audio sample word LSB ACLK(64fs) 001aag609 c. Right justified format Fig 13. I2S-bus formats The I2S-bus input interface can receive up to 24-bit wide audio samples via the serial data input with a clock frequency of at least 32 times the input sample frequency fs. Audio samples with a precision better than 24 bits are truncated to 24-bit format. TDA9984A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 January 2009 22 of 40 TDA9984A NXP Semiconductors HDMI 1.3 transmitter with 1080p upscaler embedded If the input clock has a frequency of 32fs, only 16-bit audio samples can be received. If the input clock has a frequency of 64fs and is left justified or Philips, the audio word is truncated to 24-bit format and padded with zeros. If the input clock has a frequency of 64fs and is right justified, audio sample must be strictly 24-bit length. The word select signal WS indicates whether left or right channel information is transferred over the serial data. 8.2.3 High bit rate audio The High Bit Rate audio format is used to support both DTS-HD and Dolby-True HD audio format provided for instance by Blu-Ray DVD. The transmitter is capable to receive a single High Bit Rate IEC 61937 stream at a frame rate of 768 kHz. This is typically stripped across 4 × I2S-bus interface to the HDMI transmitter with a corresponding I2S-bus clock rate of 192 kHz. As for I2S-bus, no additional information is required on the audio infoframe. All relevant information are carried on the stream through the use of the channel status bit via the I2C-bus table. 8.3 HDCP processing 8.3.1 High-bandwidth digital content protection The HDMI transmitter contains an HDCP function, which encrypts the transmitted stream content (both video and audio). This function can be enabled and disabled via the I2C-bus. The keys can be stored internally in OTP non-volatile memory or can be loaded via the I2C-bus. As the keys are stored internally, the security is maximized. 8.3.1.1 Repeater function The TDA9984A can be used in a repeater device according to the HDCP specification, Rev 1.2. The TDA9984A is able to store the KSV list of a maximum of 127 devices in a register memory. 8.3.1.2 SHA-1 To deal with repeater, a SHA-1 calculation is performed by the transmitter and by the downstream repeater. For security purposes and in order to relieve the microcontroller, the SHA-1 has been implemented within the TDA9984A. This calculation is worked out after the transmitter has loaded the KSV list (see HDCP specification, Rev 1.2). If SHA-1 calculated by transmitter equals the SHA-1 calculated by repeater, then an interrupt is sent. 8.4 TMDS serializer 8.4.1 RxSense detection The TDA9984A has the capability to sense the receiver connectivity and working behavior. This feature detects the presence of the 50 Ω pull-up resistor RT on the downstream side onto the TMDS clock channel. TDA9984A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 January 2009 23 of 40 TDA9984A NXP Semiconductors HDMI 1.3 transmitter with 1080p upscaler embedded VDDA RT RT TRANSMITTER Z0 D D RECEIVER 001aag601 Fig 14. Receiver sensitivity detection As long as the receiver is connected to the transmitter and powered up, bit RXS_FIL is set to logic 1 (see register INT_FLAGS_3, page 00h, address 12h). As soon as the cable is unplugged or the receiver side is powered off (assuming in this case that VDD is switched off), the RxSense generates an interrupt inside the TDA9984A, changing the value of bit RXS_FIL to logic 0. This allows the application to stop sending unnecessary video content. This feature is very useful when the receiver has been recovered from an off-state and does not generate a HPD transition HIGH-to-LOW-to-HIGH. In this particular case, RxSense will generate an interrupt so that the TDA9984A restarts sending video. Remark: According to the HDMI specification, only the HPD interrupt allows the application to read the EDID. RxSense is not mandatory to initialize the EDID reading procedure. 8.4.2 TMDS output buffers The TMDS output amplitude can be adjusted via an external resistor connected between pins EXT_SWING and VDDH(3V3); see Figure 15. It is strongly recommended to use REXT_SWING = 610 Ω ± 1 % to get a nominal swing of 500 mV. By doing so, the TDA9984A shall meet the minimum low-level output voltage as per HDMI specification, Rev 1.3a table 4-15. TDA9984A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 January 2009 24 of 40 TDA9984A NXP Semiconductors HDMI 1.3 transmitter with 1080p upscaler embedded 001aag602 650 (1) Vo(se) (mV) (2) 550 450 (3) 350 500 600 700 800 REXT_SWING (Ω) (1) Swing character data (2) Upper limit (600 mV) (3) Lower limit (400 mV) Fig 15. TMDS single-ended output swing as a function of external resistor REXT_SWING 8.4.3 Pixel repetition To transmit video formats with pixel rates below 25 mega samples per second or to increase the number of audio sample packets in each frame, the TDA9984A uses pixel repetition to increase the number of pixels sent by the frame. The pixel clock is multiplied by the same factor as given in Table 16. Table 16. Pixel repetition PR[3:0] Pixel repetition factor 0000 no repetition: pixel sent once 0001 2 times: pixel repeated once 0010 3 times 0011 4 times 0100 5 times 0101 6 times 0110 7 times 0111 8 times 1000 9 times 1001 10 times Others reserved 8.5 Control blocks 8.5.1 Clock management The system clock is composed of a series of three PLLs, which will generates different clocks in the system taking into account the double edge, the scaling ratio and the serialization. TDA9984A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 January 2009 25 of 40 TDA9984A NXP Semiconductors HDMI 1.3 transmitter with 1080p upscaler embedded Here is described briefly the clock system architecture: • PLL double edge: generates a clock at twice the VCLK input frequency to capture correctly the data at the video formatter input • PLL scaling: creates a new video processing scaled clock taking into account the scaling ratio programmed in the scaler • PLL serializer: a system clock generator, which enables the stream produced by the encoder to be transmitted on the TMDS data channel at ten times or above the sampling rate; see Section 8.4.3 Each PLL can be bypassed via the I2C-bus and then external clock VCLK can be provided independently to each block. 8.5.2 Interrupt controller Pin INT is used to alert the microcontroller that a critical event concerning the HDMI has occurred. Some of theses interrupts are maskable. See Table 17 for the interrupt types generated by the TDA9984A. Table 17. Interrupts Interrupt Definition Maskable feature maskable Domain Interrupt name HDCP r0 r0 = R’0 check done pj pj = P’j check fails sha-1 V = V’ check success bstatus bstatus available bcaps bcaps available t0 HDCP goes to initial state security HDCP encryption is off or blue screen removed not maskable HPD hpd transition on HPD input maskable RxSense rx_sense transition on RxSense EDID edid_block_rd EDID block read finished Interrupt sw_intsoftware test purpose 8.5.3 Hot plug detection Pin HPD is the hot plug detect pin; it is 5 V input tolerant. When asserted, the hot plug detect signal tells the transmitter that the receiver is connected. When changing from LOW to HIGH, the TDA9984A has to read EDID to match the video format to the format the receiver can handle. 8.5.4 Initialization After power-up, the TDA9984A is activated by a hard reset. Pin RST_N can be used to activate the TDA9984A in a known state. The device also offers the possibility to perform a soft reset that will affect a certain number of I2C-bus registers, but not all of them. This soft reset is also mandatory for a proper initialization of the device. TDA9984A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 January 2009 26 of 40 TDA9984A NXP Semiconductors HDMI 1.3 transmitter with 1080p upscaler embedded 8.5.5 Power management The TDA9984A can be powered down via the I2C-bus register. In this mode, all PLLs are switched off and the biasing structure of the output stage is disconnected (all activity is reduced). Therefore, the TDA9984A has a very low power consumption which is suitable for portable applications. 8.6 DDC-bus interface 8.6.1 DDC-bus channel The DDC-bus pins DDC_SDA and DDC_SCL are 5 V tolerant and can work at Standard-mode (100 kHz) and Fast-mode (400 kHz). The DDC-bus is used as a master interface in case of EDID reading, and while proceeding for HDCP. It is recommended not going beyond 100 kHz for EDID as claimed by the HDMI specification. This frequency is linked to the internal free running oscillator whose nominal frequency is 30 MHz as: f FRO f DDC = --------------------------------3 × 2N clk – div (2) Where: fFRO = free running oscillator frequency Nclk-div = value set by register Then for convenience, it is recommended to keep the same frequency for HDCP purpose. 8.6.2 E-EDID 8.6.2.1 E-EDID reading As a master interface for the EDID process, the DDC-bus is compliant to the I2C-bus specification and has the possibility of the repeat and start condition to enable quick access to the EDID content, as well as the large EDID reading possibility (with the use of a segment pointer). The TDA9984A has a full I2C-bus page (page 09h) dedicated to the EDID where one block can be stored. The block can be read by the microprocessor to determine the supported video and audio format of the downstream side. Remark: When the block is read by the TDA9984A, it generates an interrupt to warn the main processor that the TDA9984A is ready to transmit the content. Once the content is read-out by the microprocessor, it can allow reading other blocks if required. 8.6.2.2 HDMI and DVI receiver discrimination This information is located in the E-EDID receiver part, more exactly in the ‘Vendor Specific Data block within the first CEA EDID timing extension. If the 24-bit IEEE Registration Identifier contains the value 00 0C03h, then the receiver will support HDMI; otherwise the device shall be treated as a DVI device. However, even though the TDA9984A have directly access to that information, this is the task of the microcontroller to ask to switch from DVI to HDMI mode. TDA9984A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 January 2009 27 of 40 TDA9984A NXP Semiconductors HDMI 1.3 transmitter with 1080p upscaler embedded 8.7 I2C-bus interface The I2C-bus pins I2C_SDA and I2C_SCL are 5 V tolerant. Pin I2C_SCL is only an input pin. Both Fast-mode (400 kHz) and Standard-mode (100 kHz) are supported. The registers of the TDA9984A can be accessed via the I2C-bus. All registers are R/W except some, which cannot be read for confidentiality. The TDA9984A is used as a slave I2C-bus device. Bits A0 and A1 of the I2C-bus device address are externally selected by pins A0 and A1 (see Table 18). Table 18. Device address Device address W/R A6 A5 A4 A3 A2 A1 A0 - 1 1 1 0 0 pin A1 pin A0 0/1 The I2C-bus access format is shown in Figure 16. Firstly, the master writes the TDA9984A address and the subaddress to access the specific register, and then the data. 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SCL SDA SLAVE ADDRESS SUBADDRESS DATA STOP 001aaf292 Fig 16. I2C-bus access 9. I2C-bus registers definitions 9.1 Memory page management The I2C-bus memory is split into several pages and the selection between pages is made with common register CURPAGE_ADR. It is only necessary to write in this register once to change the current page. So multiple read or write operations in the same page need a write register CURPAGE_ADR once at the beginning. Table 19. Memory pages Page address Memory page description 00h general control 01h scaler and PLL scaling 02h PLL settings 09h EDID control page 10h InfoFrames and packets 11h audio settings and content info packets 12h HDCP and OTP 9.2 ID version The ID-version readable via I2C-bus is defined as follows: TDA9984A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 January 2009 28 of 40 TDA9984A NXP Semiconductors HDMI 1.3 transmitter with 1080p upscaler embedded • TDA9984AHW will have the value 1000 XXXX The four LSBs are used for indicating the die version. 10. Limiting values Table 20. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD(3V3) Conditions Min Max Unit supply voltage (3.3 V) −0.5 +4.6 V VDD(1V8) supply voltage (1.8 V) −0.5 +2.5 V ∆VDD supply voltage difference −0.5 +0.5 V Tstg storage temperature −55 +150 °C Tamb ambient temperature −5 +85 °C Tj junction temperature - +125 °C Vesd electrostatic discharge voltage - ±2000 V human body model 11. Thermal characteristics Table 21. Thermal characteristics Symbol Parameter Conditions Typ Unit Rth(j-a) thermal resistance from junction to ambient in free air 26.5 K/W 12. Static characteristics Table 22. Supplies VDD(3V3) = 3.3 V; VDD(1V8) = 1.8 V; VPP = 0 V; Tamb = −5 °C to +85 °C; unless otherwise specified. Typical values are measured at Tamb = 25 °C and fclk = 150 MHz. Symbol Parameter VPP Min Typ Max Unit programming voltage 5.0 5.25 5.5 V VDDA(FRO)(3V3) free running oscillator analog supply voltage (3.3 V) 3.0 3.3 3.6 V VDDA(PLL)(3V3) PLL analog supply voltage (3.3 V) 3.0 3.3 3.6 V VDDD(3V3) digital supply voltage (3.3 V) 3.0 3.3 3.6 V VDDH(3V3) HDMI supply voltage (3.3 V) 3.0 3.3 3.6 V VDDC(1V8) core supply voltage (1.8 V) 1.65 1.8 1.95 V VDDA(PLL)(1V8) PLL analog supply voltage (1.8 V) 1.65 1.8 1.95 V IDDA(FRO)(3V3) free running oscillator analog supply current (3.3 V) - 0.1 1 mA IDDA(PLL)(3V3) PLL analog supply current (3.3 V) IDDD(3V3) digital supply current (3.3 V) IDDH(3V3) HDMI supply current (3.3 V) Conditions input 1080i, output 1080p [1][2] - 6 6.4 mA input 1080p, output 1080p [1][4] - - 5 mA - 14 15 mA - 75 92 mA - 283 345 mA IDDA(PLL)(1V8) PLL analog supply current (1.8 V) input 1080i, output 1080p [1][2] IDDC(1V8) core supply current (1.8 V) input 1080i, output 1080p [1][2] TDA9984A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 January 2009 29 of 40 TDA9984A NXP Semiconductors HDMI 1.3 transmitter with 1080p upscaler embedded Table 22. Supplies …continued VDD(3V3) = 3.3 V; VDD(1V8) = 1.8 V; VPP = 0 V; Tamb = −5 °C to +85 °C; unless otherwise specified. Typical values are measured at Tamb = 25 °C and fclk = 150 MHz. Symbol Parameter Pcons Conditions power consumption total power dissipation Ptot Min Typ Max Unit input 480p, output 1080p [1][3] - 500 630 mW input 1080i, output 1080p [1][2] - 742 940 mW input 1080p, output 1080p [1][4] - 320 400 mW input 480p, output 1080p [1][3] - 630 770 mW input 1080i, output 1080p [1][2] - 872 1080 mW input 1080p, output 1080p [1][4] - 450 540 mW - 30 40 mW TMDS output current added power dissipation in power-down mode Ppd [1] The maximum current consumption is in this configuration for this group of pins. [2] Video format: a) Input 1080i, YCbCr 4 : 2 : 2 embedded sync, 48 kHz S/PDIF 2 channels. b) Output 1080p, YCbCr 4 : 2 : 2, 48 kHz S/PDIF. [3] Video format: a) Input 480p, ITU656 embedded sync, 48 kHz S/PDIF 2 channels. b) Output 1080p, YCbCr 4 : 2 : 2, 48 kHz S/PDIF. [4] Video format: a) Input 1080p, YCbCr 4 : 2 : 2 embedded sync, 48 kHz S/PDIF 2 channels. b) Output 1080p, YCbCr 4 : 2 : 2, 48 kHz S/PDIF. Table 23. LV-TTL digital inputs VDD(3V3) = 3.3 V; VDD(1V8) = 1.8 V; VPP = 0 V; Tamb = −5 °C to +85 °C; typical values are measured at Tamb = 25 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Not 5 V tolerant inputs: pins HSYNC, VSYNC, AP[7:0], ACLK, TM, A0, A1, VPA[7:0], VPB[7:0], VPC[7:0], VCLK, DE and RST_N VIL LOW-level input voltage - - 0.8 V VIH HIGH-level input voltage 2.0 - - V 5 V tolerant input: pin HPD VIL LOW-level input voltage - - 0.8 V VIH HIGH-level input voltage 2.0 - - V Output: pin INT VOL LOW-level output voltage CL = 10 pF; IOL = 2 mA - - 0.4 V VOH HIGH-level output voltage CL = 10 pF; IOH = −2 mA 2.4 - - V Table 24. TMDS outputs VDD(3V3) = 3.3 V; VDD(1V8) = 1.8 V; VPP = 0 V; Tamb = −5 °C to +85 °C; typical values are measured at Tamb = 25 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 480 525 560 mV TMDS output pins: TX0−, TX0+, TX1−, TX1+, TX2−, TX2+, TXC− and TXC+ VO(dif) differential output voltage REXT_SWING = 610 Ω (1 % tolerance); RL = 50 Ω TDA9984A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 January 2009 30 of 40 TDA9984A NXP Semiconductors HDMI 1.3 transmitter with 1080p upscaler embedded 13. Dynamic characteristics Table 25. Timing characteristics VDD(3V3) = 3.3 V; VDD(1V8) = 1.8 V; VPP = 0 V; Tamb = −5 °C to +85 °C; typical values are measured at Tamb = 25 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Video inputs; see Figure 17 fclk(max) maximum clock frequency pin VCLK 150 - - MHz δclk clock duty cycle pin VCLK 40 50 60 % tsu(D) data input set-up time 1.0 - - ns th(D) data input hold time 0.8 - - ns Audio input S/PDIF mode sampling frequency fs 2 channels 32 - 192 kHz - - 75 MHz 13.3 - - ns fclk clock frequency pin AP5 (MCLK) [1] Tclk clock period pin AP5 (MCLK) [1] δclk clock duty cycle 40 - 60 % sampling frequency - 192 192 kHz 32 - 192 kHz 150 - - MHz Standard-mode - - 100 kHz Fast-mode - - 400 kHz Standard-mode - - 100 kHz Fast-mode - - 400 kHz HBR mode fs I2S-bus mode sampling frequency fs TMDS output pins: TX0−, TX0+, TX1−, TX1+, TX2−, TX2+, TXC− and TXC+ fclk(max) maximum clock frequency DDC-bus; 5 V tolerant; master bus: pins DDC_SDA and DDC_SCL SCL clock frequency fSCL I2C-bus; [1] 5 V tolerant; slave bus: pins I2C_SDA and I2C_SCL SCL clock frequency fSCL In case of MCLK is required, this frequency has to be coherent with S/PDIF input. TDA9984A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 January 2009 31 of 40 TDA9984A NXP Semiconductors HDMI 1.3 transmitter with 1080p upscaler embedded VCLK VPA[7:0] VPB[7:0] VPC[7:0] DE, HSYNC, VSYNC tsu(D) th(D) 001aag604 tsu(D) th(D) 001aag605 a. Sync on rising edge VCLK VPA[7:0] VPB[7:0] VPC[7:0] DE, HSYNC, VSYNC b. Sync on falling edge VCLK VPA[7:0] VPB[7:0] VPC[7:0] DE, HSYNC, VSYNC tsu(D) th(D) tsu(D) th(D) 001aag606 c. Sync on rising and falling (double) edge Data is not allowed to change in the shaded area. Fig 17. Set-up and hold time for various clock modes 13.1 Input format Mapping of the video ports: • Port VPA has been mapped to Cb for YCbCr space and B for RGB color space • Port VPB has been mapped to Y for YCbCr space and G for RGB color space • Port VPC has been mapped to Cr for YCbCr space and R for RGB color space Table 26. Input format Input pins Signal RGB YCbCr 4:4:4 4:4:4 4 : 2 : 2 (semi-planar) 4 : 2 : 2 (ITU656-like)[1] Video port A VPA[0] Cb[0]/B[0] B[0] Cb[0] Y0[0] Y1[0] Cb[0] Y0[0] Cr[0] Y1[0] VPA[1] Cb[1]/B[1] B[1] Cb[1] Y0[1] Y1[1] Cb[1] Y0[1] Cr[1] Y1[1] VPA[2] Cb[2]/B[2] B[2] Cb[2] Y0[2] Y1[2] Cb[2] Y0[2] Cr[2] Y1[2] VPA[3] Cb[3]/B[3] B[3] Cb[3] Y0[3] Y1[3] Cb[3] Y0[3] Cr[3] Y1[3] VPA[4] Cb[4]/B[4] B[4] Cb[4] Cb[0] Cr[0] L L L L VPA[5] Cb[5]/B[5] B[5] Cb[5] Cb[1] Cr[1] L L L L VPA[6] Cb[6]/B[6] B[6] Cb[6] Cb[2] Cr[2] L L L L VPA[7] Cb[7]/B[7] B[7] Cb[7] Cb[3] Cr[3] L L L L TDA9984A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 January 2009 32 of 40 TDA9984A NXP Semiconductors HDMI 1.3 transmitter with 1080p upscaler embedded Table 26. Input format …continued Input pins Signal RGB YCbCr 4:4:4 4:4:4 4 : 2 : 2 (semi-planar) 4 : 2 : 2 (ITU656-like)[1] Video port B VPB[0] Y[0]/G[0] G[0] Y[0] Y0[4] Y1[4] Cb[4] Y0[4] Cr[4] Y1[4] VPB[1] Y[1]/G[1] G[1] Y[1] Y0[5] Y1[5] Cb[5] Y0[5] Cr[5] Y1[5] VPB[2] Y[2]/G[2] G[2] Y[2] Y0[6] Y1[6] Cb[6] Y0[6] Cr[6] Y1[6] VPB[3] Y[3]/G[3] G[3] Y[3] Y0[7] Y1[7] Cb[7] Y0[7] Cr[7] Y1[7] VPB[4] Y[4]/G[4] G[4] Y[4] Y0[8] Y1[8] Cb[8] Y0[8] Cr[8] Y1[8] VPB[5] Y[5]/G[5] G[5] Y[5] Y0[9] Y1[9] Cb[9] Y0[9] Cr[9] Y1[9] VPB[6] Y[6]/G[6] G[6] Y[6] Y0[10] Y1[10] Cb[10] Y0[10] Cr[10] Y1[10] VPB[7] Y[7]/G[7] G[7] Y[7] Y0[11] Y1[11] Cb[11] Y0[11] Cr[11] Y1[11] VPC[0] Cr[0]/R[0] R[0] Cr[0] Cb[4] Cr[4] L L L L VPC[1] Cr[1]/R[1] R[1] Cr[1] Cb[5] Cr[5] L L L L VPC[2] Cr[2]/R[2] R[2] Cr[2] Cb[6] Cr[6] L L L L VPC[3] Cr[3]/R[3] R[3] Cr[3] Cb[7] Cr[7] L L L L VPC[4] Cr[4]/R[4] R[4] Cr[4] Cb[8] Cr[8] L L L L VPC[5] Cr[5]/R[5] R[5] Cr[5] Cb[9] Cr[9] L L L L VPC[6] Cr[6]/R[6] R[6] Cr[6] Cb[10] Cr[10] L L L L VPC[7] Cr[7]/R[7] R[7] Cr[7] Cb[11] Cr[11] L L L L Video port C [1] L stands for tying to LOW voltage recommendation, e.g. ground. TDA9984A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 January 2009 33 of 40 TDA9984A NXP Semiconductors HDMI 1.3 transmitter with 1080p upscaler embedded 13.2 Timing parameters for supported video The TDA9984A supports all EIA/CEA-861B standards and ATSC video input formats. Table 27. Timing parameters for EIA/CEA-861B Format Format V frequency H total V total (Hz) H frequency (kHz) Pixel frequency (MHz) Pixel repetition Scaler 59.94 Hz systems 1 (VGA) 640 × 480p 59.9401 800 525 31.469 25.175 1 - 2, 3 720 × 480p 59.9401 858 525 31.469 27.000 1 X 4 1280 × 720p 59.9401 1650 750 44.955 74.175 1 X 5 1920 × 1080i 59.9401 2200 1125 33.716 74.175 1 X 6, 7 (NTSC) 1440 × 480i 59.9401 1716 525 15.734 27.000 2 X 8, 9 1440 × 240p 59.9401 1716 262 15.734 27.000 2 - 8, 9 1440 × 240p 59.9401 1716 263 15.734 27.000 2 - 10, 11 2880 × 480i 59.9401 3452 525 15.734 54.000 4[1] - 12, 13 2880 × 240p 59.9401 3452 262 15.734 54.000 4[1] - 12, 13 2880 × 240p 59.9401 3452 263 15.734 54.000 4[1] - 14, 15 1440 × 480p 59.9401 1716 525 31.469 54.000 2 - 16 1920 × 1080p 59.9401 2200 1125 67.432 148.350 1 - 800 525 31.500 25.200 1 - 60 Hz systems 1 (VGA) 640 × 480p 2, 3 720 × 480p 60.000 858 525 31.500 27.027 1 X 4 1280 × 720p 60.000 1650 750 45.000 74.250 1 X 5 1920 × 1080i 60.000 2200 1125 33.750 74.250 1 X 6, 7 (NTSC) 1440 × 480i 60.000 1716 525 15.750 27.027 2 X 8, 9 1440 × 240p 60.000 1716 262 15.750 27.027 2 - 8, 9 1440 × 240p 60.000 1716 263 15.750 27.027 2 - 10, 11 2880 × 480i 54.054 4[1] - 12, 13 2880 × 240p 54.054 4[1] - 12, 13 2880 × 240p 60.000 3452 263 15.750 54.054 4[1] - 14, 15 1440 × 480p 60.000 1716 525 31.500 54.054 2 - 16 1920 × 1080p 60.000 2200 1125 67.500 148.50 1 - 60.000 60.000 60.000 3452 3452 525 262 15.750 15.750 50 Hz systems 17, 18 720 × 576p 50.000 864 625 31.250 27.000 1 X 19 1280 × 720p 50.000 1980 750 37.500 74.250 1 X 20 1920 × 1080i 50.000 2640 1125 28.125 74.250 1 X 21, 22 (PAL) 1440 × 576i 50.000 1728 625 15.625 27.000 1 X 23, 24 1440 × 288p 50.000 1728 312 15.625 27.000 2 - 23, 24 1440 × 288p 50.000 1728 313 15.625 27.000 2 - 23, 24 1440 × 288p 50.000 1728 314 15.625 27.000 2 - 25, 26 2880 × 576i 54.000 4[1] - 27, 28 2880 × 288p 50.000 3456 312 15.625 54.000 4[1] - 27, 28 2880 × 288p 50.000 3456 313 15.625 54.000 4[1] - 50.000 3456 625 15.625 TDA9984A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 January 2009 34 of 40 TDA9984A NXP Semiconductors HDMI 1.3 transmitter with 1080p upscaler embedded Table 27. Timing parameters for EIA/CEA-861B …continued Format Format V frequency H total V total (Hz) H frequency (kHz) Pixel frequency (MHz) Pixel repetition Scaler 27, 28 720 × 288p 50.000 3456 314 15.625 54.000 4 - 29, 30 1440 × 576p 50.000 1728 625 31.250 54.000 2 - 31 1920 × 1080p 50.000 2640 1125 56.250 148.50 1 - [1] The format can also be defined with a repetition factor of up to 10. Table 28. Standard Timing parameters for ATSC DTV standards, which are not defined in EIA/CEA-861B Format SMPTE-296M 1280 × 720p Table 29. Standard VGA SVGA XGA H frequency Pixel frequency (kHz) (MHz) Pixel repetition Scaler 30.000 3300 750 22.500 74.250 1 - 29.970 3300 750 22.478 74.175 1 - 25.000 3960 750 18.750 74.250 1 - 23.976 4125 750 17.982 74.175 1 - Timing parameters for PC standards below 165 MHz Format V frequency H total V total (Hz) H frequency Pixel frequency (kHz) (MHz) Pixel repetition Scaler 640 × 350p 85.080 832 445 37.861 31.500 1 - 640 × 400p 85.080 832 445 37.861 31.500 1 - 720 × 400p 85.039 936 446 37.937 35.500 1 - 640 × 480p 800 × 600p 1024 × 768p 59.9401 800 525 31.469 25.175 1 - 72.809 832 525 37.861 31.500 1 - 75.000 840 500 37.500 31.500 1 - 85.008 832 520 43.269 36.000 1 - 56.250 1024 625 35.156 36.000 1 - 60.317 1056 628 37.879 40.000 1 - 72.188 1040 666 48.077 50.000 1 - 75.000 1056 625 46.875 49.500 1 - 85.061 1048 631 53.673 56.250 1 - 60.004 1344 806 48.362 65.000 1 - 70.069 1328 806 56.476 75.000 1 - 75.029 1312 800 60.023 78.750 1 - 84.997 1376 808 68.677 94.500 1 - 1024 × 768i 86.957 1264 817 35.522 44.900 1 - 1152 × 864p 75.000 1600 900 67.500 108.000 1 - 85.000 1576 907 77.094 121.500 1 - 60.000 1800 1000 60.000 108.000 1 - 85.002 1728 1011 85.937 148.450 1 - 60.002 1688 1066 63.981 108.000 1 - 75.025 1688 1066 79.977 135.000 1 - 1280 × 960p SXGA V frequency H total V total (Hz) 1280 × 1024p TDA9984A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 January 2009 35 of 40 TDA9984A NXP Semiconductors HDMI 1.3 transmitter with 1080p upscaler embedded 14. Package outline HTQFP80: plastic thermal enhanced thin quad flat package; 80 leads; body 12 x 12 x 1 mm; exposed die pad SOT841-4 c y exposed die pad X Dh A 60 41 61 ZE 40 e Eh E w (A 3) A A2 HE M θ bp A1 Lp L detail X pin 1 index 80 21 1 20 w bp e ZD M D v M A v M B B HD 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 A2 A3 bp c D (1) Dh E (1) Eh e mm 1.2 0.15 0.05 1.05 0.95 0.25 0.27 0.17 0.20 0.09 12.1 11.9 4.79 4.69 12.1 11.9 4.79 4.69 0.5 HD HE 14.15 14.15 13.85 13.85 L Lp v w y 1 0.75 0.45 0.2 0.08 0.1 ZD(1) ZE(1) θ 1.45 1.05 7° 0° 1.45 1.05 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included OUTLINE VERSION SOT841-4 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 06-04-25 06-06-20 MS-026 Fig 18. Package outline SOT841-4 (HTQFP80) TDA9984A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 January 2009 36 of 40 TDA9984A NXP Semiconductors HDMI 1.3 transmitter with 1080p upscaler embedded 15. Abbreviations Table 30. Abbreviations Acronym Description ACR Audio Clock Recovery AV Audio Video CMOS Complementary Metal-Oxide Semiconductor CTS Clock Time Stamp CTS/N Clock Time Stamp integer divider DDC Display Data Channel DE Data Enable DTS Digital Transmission System DTV Desk Top Video DVD Digital Versatile Disc DVI Digital Visual Interface EAV End Active Video EDID Extended Display Identification Data E-EDID Enhanced Extended Display Identification Data FREF Field REFerence HBR High Bit Rate HD High Definition HDCP High-bandwidth Digital Content Protection HDMI High-Definition Multimedia Interface HDTV High-Definition Television HREF Horizontal REFerence HSYNC Horizontal SYNChronization KSV Key Selection Vector LSB Least Significant Bit LV-TTL Low Voltage Transistor-Transistor Logic MSB Most Significant Bit NTSC National Television System Committee OTP One Time Programming PAL Phase Alternated Line PCM Pulse Code Modulation PLL Phase-Locked Loop SAV Start Active Video SHA-1 Secure Hash Algorithm 1 S/PDIF Sony/Philips Digital Interface TMDS Transition Minimized Differential Signalling VHREF Vertical Horizontal REFerence VREF Vertical REFerence VSYNC Vertical SYNChronization YCbCr Y = luminance, Cb = Chroma component blue, Cr = Chroma component red TDA9984A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 January 2009 37 of 40 TDA9984A NXP Semiconductors HDMI 1.3 transmitter with 1080p upscaler embedded 16. Revision history Table 31. Revision history Document ID Release date Data sheet status TDA9984A_4 20090115 Product data sheet Modifications: Change notice Supersedes TDA9984A_3 • • • • • • All document: changed Y-CB-CR in YCbCr, CB in Cb and CR in Cr for consistency • • • • • Section 8.2.2: updated the input clock with a frequency at 64fs Section 1: rewritten the first sentence Section 2: added "Dolby-True HD and DTS-HD" Figure 1, Figure 2 and Table 3: updated the pins 15, 16 and 45: name and description Table 1: added the row VDDA(PLL)(1V8) Section 8.2: changed the reference HDMI 1.2a in 1.3 and in the table 15, added the column HBR Section 8.2.3: added this paragraph High bit rate audio Table 22: updated Table 25: added the part HBR mode Table 1, Table 20, Table 22, Table 23, Table 24 and Table 25: changed the temperature min 0 °C to −5 °C and temperature max 70 °C to +85 °C TDA9984A_3 20080410 Product data sheet - TDA9984A_2 TDA9984A_2 20080115 Preliminary data sheet - TDA9984_1 TDA9984_1 20070723 Objective data sheet - - TDA9984A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 January 2009 38 of 40 TDA9984A NXP Semiconductors HDMI 1.3 transmitter with 1080p upscaler embedded 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 17.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 17.4 Licenses Purchase of NXP ICs with HDMI technology Use of an NXP IC with HDMI technology in equipment that complies with the HDMI standard requires a license from HDMI Licensing LLC, 1060 E. Arques Avenue Suite 100, Sunnyvale CA 94085, USA, e-mail: [email protected]. 17.5 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] TDA9984A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 January 2009 39 of 40 TDA9984A NXP Semiconductors HDMI 1.3 transmitter with 1080p upscaler embedded 19. Contents 1 2 3 4 5 6 7 7.1 8 8.1 8.1.1 8.1.2 8.1.2.1 8.1.2.2 8.1.2.3 8.1.2.4 8.1.2.5 8.1.2.6 8.1.2.7 8.1.2.8 8.1.3 8.1.3.1 8.1.3.2 8.1.4 8.1.5 8.1.5.1 8.1.5.2 8.1.6 8.1.7 8.1.8 8.2 8.2.1 8.2.2 8.2.3 8.3 8.3.1 8.3.1.1 8.3.1.2 8.4 8.4.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Quick reference data . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 8 Video processing . . . . . . . . . . . . . . . . . . . . . . . 8 Internal assignment . . . . . . . . . . . . . . . . . . . . . 8 Input format mappings . . . . . . . . . . . . . . . . . . . 9 RGB 4 : 4 : 4 external sync input (rising edge) 11 YCbCr 4 : 4 : 4 external sync input (rising edge) . . . . . . . . . . . . . . . . . . . . . . . . . . 12 YCbCr 4 : 2 : 2 ITU656-like external sync input (rising edge) . . . . . . . . . . . . . . . . . 13 YCbCr 4 : 2 : 2 ITU656-like external sync input (rising and falling) . . . . . . . . . . . . . 14 YCbCr 4 : 2 : 2 ITU656-like embedded sync input (rising edge) . . . . . . . . . . . . . . . . . 15 YCbCr 4 : 2 : 2 ITU656-like embedded sync input (rising and falling) . . . . . . . . . . . . . 16 YCbCr 4 : 2 : 2 semi-planar external input (rising edge) . . . . . . . . . . . . . . . . . . . . . . . . . . 17 YCbCr 4 : 2 : 2 semi-planar embedded sync input (rising edge) . . . . . . . . . . . . . . . . . 18 Synchronization . . . . . . . . . . . . . . . . . . . . . . . 19 Timing extraction generator . . . . . . . . . . . . . . 19 Data enable generator . . . . . . . . . . . . . . . . . . 19 Input and output video format . . . . . . . . . . . . . 19 Scaler unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Scaler features . . . . . . . . . . . . . . . . . . . . . . . . 19 Input and output video scaler . . . . . . . . . . . . . 20 Upsampler . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Color space converter. . . . . . . . . . . . . . . . . . . 21 Downsampler . . . . . . . . . . . . . . . . . . . . . . . . . 21 Audio processing . . . . . . . . . . . . . . . . . . . . . . 21 S/PDIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 I2S-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 High bit rate audio. . . . . . . . . . . . . . . . . . . . . . 23 HDCP processing . . . . . . . . . . . . . . . . . . . . . . 23 High-bandwidth digital content protection. . . . 23 Repeater function . . . . . . . . . . . . . . . . . . . . . . 23 SHA-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 TMDS serializer . . . . . . . . . . . . . . . . . . . . . . . 23 RxSense detection . . . . . . . . . . . . . . . . . . . . . 23 8.4.2 8.4.3 8.5 8.5.1 8.5.2 8.5.3 8.5.4 8.5.5 8.6 8.6.1 8.6.2 8.6.2.1 8.6.2.2 8.7 9 9.1 9.2 10 11 12 13 13.1 13.2 14 15 16 17 17.1 17.2 17.3 17.4 17.5 18 19 TMDS output buffers . . . . . . . . . . . . . . . . . . . Pixel repetition . . . . . . . . . . . . . . . . . . . . . . . . Control blocks. . . . . . . . . . . . . . . . . . . . . . . . . Clock management . . . . . . . . . . . . . . . . . . . . Interrupt controller . . . . . . . . . . . . . . . . . . . . . Hot plug detection . . . . . . . . . . . . . . . . . . . . . Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . Power management . . . . . . . . . . . . . . . . . . . . DDC-bus interface . . . . . . . . . . . . . . . . . . . . . DDC-bus channel . . . . . . . . . . . . . . . . . . . . . . E-EDID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-EDID reading . . . . . . . . . . . . . . . . . . . . . . . HDMI and DVI receiver discrimination . . . . . . I2C-bus interface. . . . . . . . . . . . . . . . . . . . . . . I2C-bus registers definitions . . . . . . . . . . . . . Memory page management . . . . . . . . . . . . . . ID version . . . . . . . . . . . . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Thermal characteristics . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . Input format . . . . . . . . . . . . . . . . . . . . . . . . . . Timing parameters for supported video . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 25 25 25 26 26 26 27 27 27 27 27 27 28 28 28 28 29 29 29 31 32 34 36 37 38 39 39 39 39 39 39 39 40 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 15 January 2009 Document identifier: TDA9984A_4