PCA9691 8-bit A/D and D/A converter Rev. 02 — 27 January 2010 Product data sheet 1. General description The PCA9691 is a single chip, single supply, low power, 8-bit CMOS1 data acquisition device with four analog inputs, one analog output and a serial I2C-bus interface. Three address pins (A0, A1, and A2) are used for programming the hardware address, allowing the use of up to 64 PCA9691 devices connected to the I2C-bus without additional hardware. Address, control and data to and from the PCA9691 are transferred via the serial two-line bidirectional I2C-bus. The functions of the PCA9691 include: • • • • Analog input multiplexing On-chip sample and hold 8-bit Analog-to-Digital (A/D) conversion 8-bit Digital-to-Analog (D/A) conversion The maximum conversion rate is given by the maximum frequency of the I2C-bus. 2. Features 1. 8-bit successive approximation A/D conversion Four analog inputs programmable as single-ended or differential inputs 64 different addresses by three hardware address pins 1 MHz Fast-mode Plus (Fm+) I2C-bus via serial input/output Sampling rate given by I2C-bus frequency Single supply voltage; operating from 2.5 V to 5.5 V Low standby current Analog voltage from VSS to VDD Multiplying Digital-to-Analog Converter (DAC) with one analog output On-chip sample and hold circuit Auto-incremented channel selection The definition of the abbreviations and acronyms used in this data sheet can be found in Section 14. PCA9691 NXP Semiconductors 8-bit A/D and D/A converter 3. Ordering information Table 1. Ordering information Type number Package Name Description Version PCA9691BS HVQFN16 plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 4 × 4 × 0.85 mm SOT629-1 PCA9691TS TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 PCA9691T SO16 plastic small outline package; 16 leads; body width 7.5 mm SOT162-1 4. Marking Table 2. Marking codes Type number Marking code PCA9691BS 9691 PCA9691TS PCA9691 PCA9691T PCA9691T 5. Block diagram SCL SDA A0 I2C-BUS INTERFACE A1 STATUS REGISTER PCA9691 A2 DAC DATA REGISTER ADC DATA REGISTER EXT VDD VSS POWER-ON RESET AIN0 AIN1 AIN2 CONTROL LOGIC OSCILLATOR OSC ANALOG MULTIPLEXER SAMPLE AND HOLD COMPARATOR AIN3 AOUT SAMPLE AND HOLD SUCCESSIVE APPROXIMATION REGISTER AND LOGIC 8 DAC VREF AGND 001aag462 Fig 1. Block diagram of PCA9691 PCA9691_2 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 02 — 27 January 2010 2 of 31 PCA9691 NXP Semiconductors 8-bit A/D and D/A converter 6. Pinning information AIN2 1 AIN3 2 13 AOUT 14 VDD terminal 1 index area 15 AIN0 16 AIN1 6.1 Pinning 12 VREF 11 AGND PCA9691BS 7 8 SCL 9 SDA 4 6 A1 VSS 10 EXT 5 3 A2 A0 OSC 001aag523 Transparent top view For mechanical details, see Figure 25. Fig 2. Pin configuration for HVQFN16 (PCA9691BS) AIN0 1 16 VDD AIN1 2 15 AOUT AIN2 3 14 VREF AIN3 4 A0 5 A1 6 11 OSC A2 7 10 SCL VSS 8 13 AGND PCA9691TS 12 EXT 9 SDA 001aag522 Top view. For mechanical details, see Figure 26. Fig 3. Pin configuration for TSSOP16 (PCA9691TS) AIN0 1 16 VDD AIN1 2 15 AOUT AIN2 3 14 VREF AIN3 4 A0 5 A1 6 11 OSC A2 7 10 SCL VSS 8 9 PCA9691T 13 AGND 12 EXT SDA 013aaa245 Top view. For mechanical details, see Figure 27. Fig 4. Pin configuration for SO16 (PCA9691T) PCA9691_2 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 02 — 27 January 2010 3 of 31 PCA9691 NXP Semiconductors 8-bit A/D and D/A converter 6.2 Pin description Table 3. Symbol Pin description Pin Type Description HVQFN16 TSSOP16 SO16 (PCA9691BS) (PCA9691TS) (PCA9691T) AIN0 15 1 1 input analog input 0 AIN1 16 2 2 input analog input 1 AIN2 1 3 3 input analog input 2 AIN3 2 4 4 input analog input 3 A0 3 5 5 input address input 0 A1 4 6 6 input address input 1 A2 5 7 7 input address input 2 VSS 6[1] 8 8 ground ground supply (analog and digital) SDA 7 9 9 input/output I2C-bus data input and output SCL 8 10 10 input I2C-bus clock input OSC 9 11 11 input/output oscillator signal selection: input, if pin EXT is HIGH output, if pin EXT is LOW EXT 10 12 12 input oscillator selection input: HIGH: external oscillator LOW: internal oscillator AGND 11 13 13 ground DAC analog ground VREF 12 14 14 input DAC reference voltage input AOUT 13 15 15 output analog output VDD 14 16 16 supply supply voltage [1] The die paddle (exposed pad) is connected to VSS and should be electrically isolated. 7. Functional description 7.1 Addressing Each PCA9691 device in an I2C-bus system is activated by sending a valid address to the device. The address consists of seven programmable bits and one read/write bit. The address must be set according to Table 4. The three input pins (A2, A1, and A0) are used to encode the seven address bits (A[6:0]), where each of the pins can be connected to VDD, VSS, SCL, or SDA. The address is always sent as the first byte after the start condition in the I2C-bus protocol. The last bit of the address byte is the read/write bit which sets the direction of the following data transfer (see Figure 5, Figure 18, and Figure 19). msb A6 lsb A5 A4 A3 A2 A1 A0 R/W 001aag465 Fig 5. Address byte PCA9691_2 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 02 — 27 January 2010 4 of 31 PCA9691 NXP Semiconductors 8-bit A/D and D/A converter 7.1.1 Address map Table 4. PCA9691 address map Pin Bit Address Number A2 A1 A0 A6 A5 A4 A3 A2 A1 A0 R/W VSS VSS SDA 0 1 0 0 0 0 0 0 40h 1 VSS VDD SDA 0 1 0 0 0 0 1 0 42h 2 VDD VSS SDA 0 1 0 0 0 1 0 0 44h 3 VDD VDD SDA 0 1 0 0 0 1 1 0 46h 4 VSS SDA VSS 0 1 0 0 1 0 0 0 48h 5 VSS SDA VDD 0 1 0 0 1 0 1 0 4Ah 6 VDD SDA VSS 0 1 0 0 1 1 0 0 4Ch 7 VDD SDA VDD 0 1 0 0 1 1 1 0 4Eh 8 SDA VSS VSS 0 1 0 1 0 0 0 0 50h 9 SDA VSS VDD 0 1 0 1 0 0 1 0 52h 10 SDA VDD VSS 0 1 0 1 0 1 0 0 54h 11 SDA VDD VDD 0 1 0 1 0 1 1 0 56h 12 VSS SDA SDA 0 1 0 1 1 0 0 0 58h 13 VDD SDA SDA 0 1 0 1 1 0 1 0 5Ah 14 SDA VSS SDA 0 1 0 1 1 1 0 0 5Ch 15 SDA VDD SDA 0 1 0 1 1 1 1 0 5Eh 16 SDA SDA VSS 0 1 1 0 0 0 0 0 60h 17 SDA SDA VDD 0 1 1 0 0 0 1 0 62h 18 SDA SDA SDA 0 1 1 0 0 1 0 0 64h 19 SCL SCL SCL 0 1 1 0 0 1 1 0 66h 20 VSS VSS SCL 0 1 1 0 1 0 0 0 68h 21 VSS VDD SCL 0 1 1 0 1 0 1 0 6Ah 22 VDD VSS SCL 0 1 1 0 1 1 0 0 6Ch 23 VDD VDD SCL 0 1 1 0 1 1 1 0 6Eh 24 VSS SCL VSS 0 1 1 1 0 0 0 0 70h 25 VSS SCL VDD 0 1 1 1 0 0 1 0 72h 26 VDD SCL VSS 0 1 1 1 0 1 0 0 74h 27 VDD SCL VDD 0 1 1 1 0 1 1 0 76h 28 SCL VSS VSS 0 1 1 1 1 0 0 0 78h 29 SCL VSS VDD 0 1 1 1 1 0 1 0 7Ah 30 SCL VDD VSS 0 1 1 1 1 1 0 0 7Ch 31 SCL VDD VDD 0 1 1 1 1 1 1 0 7Eh 32 VSS SCL SCL 1 0 0 0 0 0 0 0 80h 33 VDD SCL SCL 1 0 0 0 0 0 1 0 82h 34 SCL VSS SCL 1 0 0 0 0 1 0 0 84h 35 SCL VDD SCL 1 0 0 0 0 1 1 0 86h 36 SCL SCL VSS 1 0 0 0 1 0 0 0 88h 37 SCL SCL VDD 1 0 0 0 1 0 1 0 8Ah 38 PCA9691_2 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 02 — 27 January 2010 5 of 31 PCA9691 NXP Semiconductors 8-bit A/D and D/A converter Table 4. PCA9691 address map …continued Pin Bit Address Number A2 A1 A0 A6 A5 A4 A3 A2 A1 A0 R/W VSS SCL SDA 1 0 0 0 1 1 0 0 8Ch 39 VDD SCL SDA 1 0 0 0 1 1 1 0 8Eh 40 VSS VSS VSS 1 0 0 1 0 0 0 0 90h 41 VSS VSS VDD 1 0 0 1 0 0 1 0 92h 42 VSS VDD VSS 1 0 0 1 0 1 0 0 94h 43 VSS VDD VDD 1 0 0 1 0 1 1 0 96h 44 VDD VSS VSS 1 0 0 1 1 0 0 0 98h 45 VDD VSS VDD 1 0 0 1 1 0 1 0 9Ah 46 VDD VDD VSS 1 0 0 1 1 1 0 0 9Ch 47 VDD VDD VDD 1 0 0 1 1 1 1 0 9Eh 48 VSS SDA SCL 1 0 1 0 0 0 0 0 A0h 49 VDD SDA SCL 1 0 1 0 0 0 1 0 A2h 50 SCL SDA VSS 1 0 1 0 0 1 0 0 A4h 51 SCL SDA VDD 1 0 1 0 0 1 1 0 A6h 52 SDA SCL VSS 1 0 1 0 1 0 0 0 A8h 53 SDA SCL VDD 1 0 1 0 1 0 1 0 AAh 54 SDA VSS SCL 1 0 1 0 1 1 0 0 ACh 55 SDA VDD SCL 1 0 1 0 1 1 1 0 AEh 56 SCL VSS SDA 1 0 1 1 0 0 0 0 B0h 57 SCL VDD SDA 1 0 1 1 0 0 1 0 B2h 58 SDA SCL SCL 1 0 1 1 0 1 0 0 B4h 59 SCL SDA SCL 1 0 1 1 0 1 1 0 B6h 60 SCL SCL SDA 1 0 1 1 1 0 0 0 B8h 61 SCL SDA SDA 1 0 1 1 1 0 1 0 BAh 62 SDA SCL SDA 1 0 1 1 1 1 0 0 BCh 63 SDA SDA SCL 1 0 1 1 1 1 1 0 BEh 64 7.2 Control byte The second byte sent to a PCA9691 is stored in its control register and is required to control the PCA9691 function. The upper nibble of the control register is used for enabling the analog output, and for programming the analog inputs as single-ended or differential inputs. The lower nibble selects one of the analog input channels defined by the upper nibble (see Figure 6). If the auto-increment flag is set, the channel number is incremented automatically after each A/D conversion. If the auto-increment mode is selected and the internal oscillator is used, the analog output enable flag in the control byte (bit 6) must be set. This allows the internal oscillator to run continuously, thereby preventing conversion errors resulting from oscillator start-up delay. The analog output enable flag can be reset at other times to reduce quiescent power consumption. PCA9691_2 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 02 — 27 January 2010 6 of 31 PCA9691 NXP Semiconductors 8-bit A/D and D/A converter The selection of a non-existing input channel results in the highest available channel number being allocated. Therefore, if the auto-increment flag is set, the next selected channel is always channel 0. After power-on all bits of the control register are reset to logic 0. The DAC and the oscillator are disabled for power saving. The analog output is switched to a high-impedance state. The most significant bits of both nibbles are reserved for oscillator control. Bit 7 and bit 3 can be set when the interface frequency is fSCL ≤ 400 kHz (see Figure 6). Setting these two bits to logic 1 sets the internal frequency to half and the accuracy of the A/D and D/A conversion is 1 LSB as indicated in Table 8 and Table 9. The oscillator output is disabled in normal operation (pin OSC is LOW). Setting bit 7 to logic 0 and bit 3 to logic 1 will enable this output in order to observe the oscillator frequency (divided by 4). PCA9691_2 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 02 — 27 January 2010 7 of 31 PCA9691 NXP Semiconductors 8-bit A/D and D/A converter MSB 0 LSB X X X 0 X X X CONTROL BYTE A/D CHANNEL NUMBER: 00 channel 0 01 channel 1 10 channel 2 11 channel 3 AUTO-INCREMENT FLAG: active if 1 INTERNAL OSCILLATOR FREQUENCY: 00 full oscillator frequency OSC output disabled 01 full oscillator frequency OSC enabled with 1/4 frequency 10 reserved 11 1/2 oscillator frequency OSC output disabled ANALOG INPUT PROGRAMMING: 00 four single-ended inputs AIN0 channel 0 AIN1 channel 1 AIN2 channel 2 AIN3 channel 3 01 three differential inputs AIN0 channel 0 AIN1 channel 1 AIN2 channel 2 AIN3 10 single-ended and differential mixed AIN0 channel 0 AIN1 channel 1 AIN2 channel 2 AIN3 11 two differential inputs AIN0 channel 0 AIN1 AIN2 channel 1 AIN3 ANALOG OUTPUT ENABLE FLAG: analog output active if 1 001aag466 Fig 6. Control byte 7.3 D/A conversion The third byte sent to a PCA9691 is stored in the DAC data register and is converted to the corresponding analog voltage using the on-chip DAC. This DAC consists of a resistor divider chain connected to the external reference voltage (pin VREF) with 256 taps and selection switches. The tap-decoder switches one of these taps to the DAC output line (see Figure 7). The analog output voltage is buffered by an auto-zeroed unity gain amplifier. Setting the analog output enable flag of the control register switches this buffer amplifier on or off. In the active state the output voltage is held until a further data byte is sent. PCA9691_2 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 02 — 27 January 2010 8 of 31 PCA9691 NXP Semiconductors 8-bit A/D and D/A converter In order to release the DAC for a successive approximation A/D conversion cycle, the unity gain amplifier is equipped with a sample and hold circuit. This circuit holds the output voltage while executing the A/D conversion. The formula for the output voltage supplied to the analog output pin AOUT is shown in Figure 8. The waveforms of a D/A conversion sequence are shown in Figure 9. With the rising edge of the 8th clock bit the DAC register is filled with a new value D7 to D0. After some delay the voltage at the analog output starts to change from the previous value to the new value. This delay is random but stays within the following limits: • Minimum 8Tosc from the rising edge of the 8th bit • Maximum 18Tosc from the rising edge of the acknowledge bit (9th bit) Where Tosc is the oscillator period (oscillator frequency is given in Table 6). Remark: When AOUT starts changing, the DAC settling time ts(DAC) (specified in Table 8), is required for AOUT to reach a new accurate value. PCA9691 DAC out VREF SAMPLE AND HOLD unity gain amplifier AOUT R256 FF R255 D7 D6 R3 TAP DECODER 02 R2 01 D0 R1 AGND 00 001aag467 Fig 7. DAC resistor divider chain PCA9691_2 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 02 — 27 January 2010 9 of 31 PCA9691 NXP Semiconductors 8-bit A/D and D/A converter MSB D7 LSB D6 D5 D4 VAOUT VDD VAOUT = VAGND + D3 D2 D1 DAC data register D0 VVREF − VAGND 7 Σ Di × 2i 256 i=0 VVREF VAGND VSS 00 01 02 03 04 FE FF DAC (hex) 001aag468 Fig 8. protocol S ADDRESS SCL 1 2 DAC data and DC conversion characteristics 0 A 8 9 CONTROL BYTE 1 A 8 9 DATA BYTE 1 1 A 8 9 DATA BYTE 2 1 A 8 9 SDA td VAOUT ts(DAC) high-impedance state of previous value held in DAC register td previous value held in DAC register ts(DAC) value of data byte 1 time 001aag469 Fig 9. D/A conversion sequence 7.3.1 Worst case example An example of the worst case is shown in Figure 10. The delay time can have a value between 8Tosc and 18Tosc. When the I2C-bus is driven at 1 MHz (full speed) then the DAC is operating at a rate of 9 μs. The previous AOUT value is valid at least until the rising edge of the acknowledge bit (8Tosc ≥ 1.23 μs). The latest start time of the new value is 5.6 μs from the rising edge of the acknowledge bit: (18Tosc ≤ 5.6 μs) so AOUT is stable after ts(DAC) ≤ 2.4 μs. PCA9691_2 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 02 — 27 January 2010 10 of 31 PCA9691 NXP Semiconductors 8-bit A/D and D/A converter The new AOUT value is valid, at the latest, after 8.0 μs so before the rising edge of the 8th bit of the next transferred byte. Therefore, at the full speed of the I2C-bus, the analog output is valid under all circumstances between the rising edges of the 8th bit and the acknowledge bit. SCL 6 7 8 A 1 2 3 < 18Tosc 4 5 > 8Tosc 6 7 8 valid A 1 2 ts(DAC) VAOUT 001aag470 Fig 10. D/A conversion sequence, example of worst case 7.4 A/D conversion The A/D Converter (ADC) makes use of the successive approximation conversion technique. The on-chip DAC and a high-gain comparator are used temporarily during an A/D conversion cycle. An A/D conversion cycle is always started after sending a valid read mode address to a PCA9691. The A/D conversion cycle is triggered at the trailing edge of the acknowledge clock pulse and is executed while transmitting the result of the previous conversion (see Figure 11). protocol S ADDRESS 1 A DATA BYTE 0 A DATA BYTE 1 A DATA BYTE 2 A SCL 1 2 8 9 1 9 1 9 1 SDA sampling byte 1 sampling byte 2 sampling byte 3 conversion of byte 1 conversion of byte 2 conversion of byte 3 transmission of previously converted byte transmission of byte 1 transmission of byte 2 mbl829 Fig 11. A/D conversion sequence Once a conversion cycle is triggered, an input voltage sample of the selected channel is stored on the chip and is converted to the corresponding 8-bit binary code. Samples picked up from differential inputs are converted to an 8-bit two’s complement code (see Figure 12 and Figure 13). The conversion result is stored in the ADC data register and awaits transmission. If the auto-increment flag is set the next channel is selected. PCA9691_2 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 02 — 27 January 2010 11 of 31 PCA9691 NXP Semiconductors 8-bit A/D and D/A converter The first byte transmitted in a read cycle contains the conversion result code of the previous read cycle. After a Power-On Reset (POR) condition the first byte read is 80h. The protocol of an I2C-bus read cycle is shown in Figure 19. The actual speed of the I2C-bus provides the maximum A/D conversion rate. ADC (hex) FF FE VLSB = VVREF − VAGND 256 04 03 02 01 00 0 1 2 3 4 254 255 VAIN − VAGND VLSB 001aah587 Fig 12. A/D conversion characteristics of single-ended inputs PCA9691_2 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 02 — 27 January 2010 12 of 31 PCA9691 NXP Semiconductors 8-bit A/D and D/A converter ADC (hex) 7F 7E 02 01 00 −128 −127 −2 −1 0 1 2 126 127 VAIN+ − VAIN− FF VLSB FE VLSB = VVREF − VAGND 256 81 80 001aah588 Fig 13. A/D conversion characteristics of differential inputs 7.5 Reference voltage For the D/A and A/D conversion either a stable external voltage reference or the supply voltage has to be applied to the resistor divider chain (pins VREF and AGND). Pin AGND has to be connected to the system analog ground and may have a DC off-set with reference to VSS. A low frequency may be applied to pins VREF and AGND. This allows the use of the DAC as a one-quadrant multiplier (see Figure 12 and Figure 24). The ADC may also be used as a one- or two-quadrant analog divider. The analog input voltage is divided by the reference voltage. The result is converted to a binary code. In this application the user has to keep the reference voltage stable during the conversion cycle. 7.6 Oscillator An on-chip oscillator generates the clock signal required for the A/D conversion cycle and for refreshing the auto-zeroed buffer amplifier. When using this oscillator pin EXT has to be connected to VSS. The oscillator frequency divided by 4 is available at output pin OSC (see Section 7.2). However, in normal operation it is recommended that output pin OSC is disabled. In this case the output pin OSC is LOW. The oscillator starts when a start condition is sent via the I2C-bus interface. If the received address is recognized as valid the oscillator continues to run. If the received address is not recognized the oscillator stops. If a stop condition occurs the oscillator is stopped unless pin AOUT is enabled. PCA9691_2 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 02 — 27 January 2010 13 of 31 PCA9691 NXP Semiconductors 8-bit A/D and D/A converter It is recommended that if the I2C-bus speed fSCL ≤ 400 kHz, you must reduce the oscillator frequency by half (see the definition of the control byte in Figure 6). If pin EXT is connected to VDD the oscillator output OSC is switched to a high-impedance state allowing to feed an external clock signal to the OSC input. The frequency of the external clock must be in the specified range. 7.7 Characteristics of the I2C-bus The I2C-bus is for bidirectional, two-line communication between different IC or modules. The two lines are a Serial DAta Line (SDA) and a Serial Clock Line (SCL). Both lines are connected to a positive supply via a pull-up resistor. Data transfer is initiated only when the bus is not busy. 7.7.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line remains stable during the HIGH period of the clock pulse as changes in the data line at this time are interpreted as control signals (see Figure 14). SDA SCL data line stable; data valid change of data allowed mbc621 Fig 14. Bit transfer 7.7.2 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 15). SDA SDA SCL SCL S P START condition STOP condition mbc622 Fig 15. Definition of start and stop condition PCA9691_2 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 02 — 27 January 2010 14 of 31 PCA9691 NXP Semiconductors 8-bit A/D and D/A converter 7.7.3 System configuration A device which sends data to the bus is a transmitter, a device which receives data from the bus is a receiver. The device which initiates and terminates a transfer is the master; and the devices which are addressed by the master are the slaves (see Figure 16). SDA SCL MASTER TRANSMITTER RECEIVER SLAVE TRANSMITTER RECEIVER SLAVE RECEIVER MASTER TRANSMITTER RECEIVER MASTER TRANSMITTER mba605 Fig 16. System configuration 7.7.4 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge cycle. • A slave receiver, which is addressed, must generate an acknowledge after the reception of each byte. • A master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. • The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). • A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledgement on the I2C-bus is illustrated in Figure 17. data output by transmitter not acknowledge data output by receiver acknowledge SCL from master 1 2 8 9 S START condition clock pulse for acknowledgement mbc602 Fig 17. Acknowledgement on the I2C-bus PCA9691_2 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 02 — 27 January 2010 15 of 31 PCA9691 NXP Semiconductors 8-bit A/D and D/A converter 7.7.5 I2C-bus protocol After a start condition a valid hardware address has to be sent to a PCA9691 device. The read/write bit defines the direction of the following single or multiple byte data transfer. For the format and the timing of the start condition (S), the stop condition (P) and the acknowledge bit (A) refer to the I2C-bus characteristics. In the write mode a data transfer is terminated by sending either a stop condition or the start condition of the next data transfer. acknowledge from PCA9691 S ADDRESS 0 A acknowledge from PCA9691 acknowledge from PCA9691 A A CONTROL BYTE DATA BYTE P/S N = 0 to M data bytes 001aag471 Fig 18. Bus protocol for write mode, D/A conversion acknowledge from PCA9691 S ADDRESS 1 A acknowledge from master no acknowledge A 1 DATA BYTE LAST DATA BYTE N = 0 to M data bytes P 001aag472 Fig 19. Bus protocol for read mode, A/D conversion 8. Internal circuitry VDD SCL SDA A0 A1 A2 EXT OSC VREF AGND AIN0 AIN1 AIN2 AIN3 AOUT VSS 001aah585 Fig 20. Device protection 9. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD VI II Conditions Min Max Unit supply voltage −0.5 +6.5 V input voltage −0.5 VDD + 0.5 V input current - ±10 mA PCA9691_2 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 02 — 27 January 2010 16 of 31 PCA9691 NXP Semiconductors 8-bit A/D and D/A converter Table 5. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter IO Conditions Min Max Unit output current - ±20 mA IDD supply current - +50 mA ISS ground supply current - −50 mA Ptot total power dissipation - 300 mW Po output power - 100 mW HBM [1] - ±1500 V MM [2] - ±200 V latch-up current [3] - 100 mA Tstg storage temperature [4] −65 +150 °C Tamb ambient temperature −40 +85 °C VESD Ilu electrostatic discharge voltage [1] Pass level; Human Body Model (HBM), according to Ref. 5 “JESD22-A114”. [2] Pass level; Machine Model (MM), according to Ref. 6 “JESD22-A115”. [3] Pass level; latch-up testing according to Ref. 7 “JESD78” at maximum ambient temperature (Tamb(max)). [4] According to the NXP store and transport requirements (see Ref. 9 “NX3-00092”) the devices have to be stored at a temperature of +8 °C to +45 °C and a humidity of 25 % to 75 %. For long term storage products deviant conditions are described in that document. 10. Characteristics 10.1 Static characteristics Table 6. Static characteristic VDD = 2.5 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 2.5 5.0 5.5 V no bus activity - 1.5 10 μA bus activity - 10 100 μA - 500 1400 μA - 1400 2500 μA 0.8 - 2.0 V 0 - 0.3VDD V 0.7VDD - - V −100 - +100 nA - - 550 pF 24 - - mA Supply VDD supply voltage IDD supply current VI = VSS or VDD; no load standby operating; fSCL = 1 MHz pin AOUT off pin AOUT active VPOR [1] power-on reset voltage Digital inputs: pins SCL, SDA, A0, A1, A2, OSC and EXT VIL LOW-level input voltage VIH HIGH-level input voltage IL leakage current Ci input capacitance VI = VSS to VDD Digital output: pin SDA IOL LOW-level output current VOL = 0.4 V; VDD = 5 V; CL = 550 pF; fSCL = 1 MHz PCA9691_2 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 02 — 27 January 2010 17 of 31 PCA9691 NXP Semiconductors 8-bit A/D and D/A converter Table 6. Static characteristic …continued VDD = 2.5 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Reference inputs: pins VREF and AGND VVREF voltage on pin VREF VVREF − VAGND ≥ 1.6 V 1.6 - VDD V VAGND voltage on pin AGND VVREF − VAGND ≥ 1.6 V VSS - VDD − 1.6 V ILI input leakage current −100 - +100 nA Rref reference resistance - 40 - kΩ resistance between pin VREF and pin AGND Oscillator: pin OSC fosc(int) internal oscillator frequency pin EXT is LOW 3.2 - 8.0 MHz fosc(ext) external oscillator frequency 3.5 - 5.5 MHz [1] pin EXT is HIGH The power-on reset circuit resets the I2C-bus logic when VDD < VPOR. 001aag463 640 IDD (μA) 480 320 160 0 2 3 4 5 6 VDD (V) Internal oscillator on; analog output disabled; Tamb = 27 °C Fig 21. Operating supply current as a function of supply voltage (typical) PCA9691_2 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 02 — 27 January 2010 18 of 31 PCA9691 NXP Semiconductors 8-bit A/D and D/A converter 001aag464 50 ZAOUT (Ω) ZAOUT (Ω) 40 40 30 30 20 20 10 10 0 EB 0 00 02 04 06 001aag474 50 08 0A hex input code a. Output impedance near negative power rail (VSS) EF F3 F7 FB FF hex input code b. Output impedance near positive power rail (VDD) Tamb = 27 °C; VDD = 5 V; VVREF = 5 V; VAGND = 0 V, (typical values) Fig 22. Output impedance of analog output buffer (near power rails) 10.2 Dynamic characteristics Table 7. I2C-bus characteristics VDD = 2.5 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; reference to 30 % and 70 % with an input voltage swing of VSS to VDD (see Figure 23). Symbol Parameter Conditions Standard mode [1] Min Max Fast mode Fast-mode Plus Unit Min Max Min Max fSCL SCL clock frequency 0 100 0 400 0 1000 tBUF bus free time between a STOP and START condition 4.7 - 1.3 - 0.5 - μs tHD;STA hold time (repeated) START condition 4.0 - 0.6 - 0.26 - μs tSU;STA set-up time for a repeated START condition 4.7 - 0.6 - 0.26 - μs tSU;STO set-up time for STOP condition 4.0 - 0.6 - 0.26 - μs tHD;DAT data hold time 0 - 0 - 0 - ns tVD;ACK data valid acknowledge time [2] 0.1 3.45 0.1 0.9 0.05 0.45 μs tVD;DAT data valid time [3] 300 - 75 - 75 450 ns tSU;DAT data set-up time 250 - 100 - 50 - ns tLOW LOW period of the SCL clock 4.7 - 1.3 - 0.5 - μs tHIGH HIGH period of the SCL clock 4.0 - 0.6 - 0.26 - μs PCA9691_2 Product data sheet kHz © NXP B.V. 2010. All rights reserved. Rev. 02 — 27 January 2010 19 of 31 PCA9691 NXP Semiconductors 8-bit A/D and D/A converter Table 7. I2C-bus characteristics …continued VDD = 2.5 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; reference to 30 % and 70 % with an input voltage swing of VSS to VDD (see Figure 23). Symbol Parameter Conditions Standard mode Fast mode Fast-mode Plus Unit Min Max Min Max Min Max - 300 20 + 0.1Cb 300 - 120 ns tf fall time of both SDA and SCL signals [4][5][6] tr rise time of both SDA and SCL signals [4][5][6] - 1000 20 + 0.1Cb 300 - 120 ns tw(spike) spike pulse width [7] - 50 - 50 - 50 ns [1] The minimum SCL clock frequency is limited by the bus time-out feature which resets the serial bus interface if either the SDA or SCL is held LOW for a minimum of 25 ms. You must disable the bus time-out feature for DC operation. [2] tVD;ACK = time for acknowledgement signal from SCL LOW to SDA (out) LOW. [3] tVD;DAT = minimum time for valid SDA (out) data following SCL LOW. [4] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to bridge the undefined region of the SCL’s falling edge. [5] Cb = total capacitance of one bus line in pF. [6] The maximum tf for the SDA and SCL bus lines is 300 ns. The maximum fall time for the SDA output stage, tf is 250 ns. This allows series protection resistors to be connected between the SDA pin and the SDA bus line and between the SCL pin and the SCL bus line without exceeding the maximum tf. [7] Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns. PROTOCOL START CONDITION (S) tSU;STA BIT 7 MSB (A7) tLOW BIT 6 (A6) tHIGH BIT 0 LSB (R/W) ACKNOWLEDGE (A) STOP CONDITION (P) 1 / fSCL SCL tBUF tr tf SDA tHD;STA tSU;DAT tHD;DAT tVD;DAT tSU;STO mbd820 Rise and fall times refer to 30 % and 70 % Fig 23. I2C-bus timing diagram PCA9691_2 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 02 — 27 January 2010 20 of 31 PCA9691 NXP Semiconductors 8-bit A/D and D/A converter Table 8. D/A characteristics VDD = 5.0 V; VSS = 0 V; VVREF = 5.0 V; VAGND = 0 V; Tamb = −40 °C to +85 °C; RL = 10 kΩ; CL = 50 pF; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit no resistive load VSS - VDD V RL = 10 kΩ VSS - 0.9VDD V output leakage current pin AOUT disabled −100 - +100 nA EG gain error no resistive load - - 1 % EO offset error Analog output VAOUT ILO voltage on pin AOUT Accuracy EL linearity error ts(DAC) DAC settling time fc(DAC) DAC conversion frequency αsup(n) noise suppression - - ±20 mV fSCL ≤ 400 kHz [1] - - ±1.0 LSB fSCL > 400 kHz [1] - - ±1.5 LSB [2] - - 2.4 μs - - 44 kHz - 40 - dB f = 100 Hz; Vn(VDD)(p-p) = 100 mV [1] The linearity error is assured if the internal frequency is changed by setting bit 7 and bit 3 of the control byte to logic 1 (see Figure 6). [2] The time from the start of AOUT to a change of 1⁄2 LSB full scale (see Section 7.3). Table 9. A/D characteristics VDD = 5.0 V; VSS = 0 V; VVREF = 5.0 V; VAGND = 0 V; Tamb = −40 °C to +85 °C; RL = 10 kΩ; CL = 50 pF; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit pins AIN0 to AIN3 VSS - VDD V Analog inputs VAIN voltage on pin AIN ILI input leakage current −100 - +100 nA Ci(a) analog input capacitance - 10 - pF Ci(dif) differential input capacitance - 10 - pF Vi(se) single-ended input voltage measuring range VAGND - VVREF V Vi(dif) differential input voltage measuring range: VFSR = VVREF − VAGND −0.5VFSR - +0.5VFSR V EG gain error fSCL ≤ 400 kHz - - 1 % fSCL > 400 kHz - - 3 % EO offset error - - ±20 mV fSCL ≤ 400 kHz [1] - - ±1.0 LSB fSCL > 400 kHz [1] - - ±2.0 LSB - 40 - dB - 40 - dB - - 8.5 μs - - 111 kHz Accuracy EL linearity error CMRR common-mode rejection ratio αsup(n) noise suppression tc(ADC) ADC conversion time fc(ADC) ADC conversion frequency f = 100 Hz; Vn(VDD)(p-p) = 100 mV fSCL = 1 MHz PCA9691_2 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 02 — 27 January 2010 21 of 31 PCA9691 NXP Semiconductors 8-bit A/D and D/A converter [1] The linearity error is assured if the internal frequency is changed by setting bit 7 and bit 3 of the control byte to logic 1 (see Figure 6). 11. Application information Inputs must be connected to VSS or VDD when not in use. Analog inputs may also be connected to pins AGND or VREF. In order to prevent excessive ground and supply noise and to minimize crosstalk of the digital-to-analog signal paths the printed-circuit board layout must be designed very carefully. Noisy digital circuits and ground loops must be avoided on the supply lines common to the PCA9691 device. Decoupling capacitors (> 10 μF) are recommended for power supply and reference voltage inputs. During data transfer the first bit written out is the MSB and the last bit is the LSB. VDD VDD VDD V0 AIN0 VDD VDD AOUT AIN1 VREF AIN2 AGND VOUT AIN3 PCA9691 EXT OSC A0 SCL A1 A2 Θ VSS Θ SDA VDD AIN0 V0 V1 VDD AOUT AIN1 VREF AIN2 AGND VOUT V2 AIN3 PCA9691 EXT VDD OSC A0 SCL A1 A2 VSS SDA VDD analog ground MASTER TRANSMITTER digital ground I2C-bus 001aag473 Fig 24. Application diagram PCA9691_2 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 02 — 27 January 2010 22 of 31 PCA9691 NXP Semiconductors 8-bit A/D and D/A converter 12. Package outline HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 4 x 4 x 0.85 mm A B D SOT629-1 terminal 1 index area A A1 E c detail X e1 C 1/2 e e 8 y y1 C v M C A B w M C b 5 L 9 4 e e2 Eh 1/2 e 1 12 terminal 1 index area 16 13 X Dh 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 e2 L v w y y1 mm 1 0.05 0.00 0.38 0.23 0.2 4.1 3.9 2.25 1.95 4.1 3.9 2.25 1.95 0.65 1.95 1.95 0.75 0.50 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT629-1 --- MO-220 --- EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-22 Fig 25. Package outline SOT629-1 (HVQFN16) of PCA9691BS PCA9691_2 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 02 — 27 January 2010 23 of 31 PCA9691 NXP Semiconductors 8-bit A/D and D/A converter TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 26. Package outline SOT403-1 (TSSOP16) of PCA9691TS PCA9691_2 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 02 — 27 January 2010 24 of 31 PCA9691 NXP Semiconductors 8-bit A/D and D/A converter SO16: plastic small outline package; 16 leads; body width 7.5 mm SOT162-1 D E A X c HE y v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp L 8 1 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 10.5 10.1 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.41 0.40 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT162-1 075E03 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 27. Package outline SOT162-1 (SO16) of PCA9691T PCA9691_2 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 02 — 27 January 2010 25 of 31 PCA9691 NXP Semiconductors 8-bit A/D and D/A converter 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 13.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities PCA9691_2 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 02 — 27 January 2010 26 of 31 PCA9691 NXP Semiconductors 8-bit A/D and D/A converter 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 28) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 10 and 11 Table 10. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 11. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 350 to 2 000 > 2 000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 28. PCA9691_2 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 02 — 27 January 2010 27 of 31 PCA9691 NXP Semiconductors 8-bit A/D and D/A converter maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 28. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 14. Abbreviations Table 12. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DAC Digital-to-Analog Converter DC Direct Current HBM Human Body Model I2C Inter-Integrated Circuit bus IC Integrated Circuit LSB Least Significant Bit MM Machine Model MSB Most Significant Bit MSL Moisture Sensitivity Level PCB Printed-Circuit Board POR Power-On Reset SCL Serial Clock Line SDA Serial DAta line SMD Surface Mount Device 15. References [1] AN10365 — Surface mount reflow soldering description PCA9691_2 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 02 — 27 January 2010 28 of 31 PCA9691 NXP Semiconductors 8-bit A/D and D/A converter [2] IEC 60134 — Rating systems for electronic tubes and valves and analogous semiconductor devices [3] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena [4] IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices [5] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) [6] JESD22-A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM) [7] JESD78 — IC Latch-Up Test [8] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices [9] NX3-00092 — NXP store and transport requirements [10] SNV-FA-01-02 — Marking Formats Integrated Circuits [11] UM10204 — I2C-bus specification and user manual 16. Revision history Table 13. Revision history Document ID Release date Data sheet status PCA9691_2 20100127 Product data sheet Modifications: PCA9691_1 • Supersedes PCA9691_1 Added new package and product type PCA9691T 20080408 Product data sheet PCA9691_2 Product data sheet Change notice - - © NXP B.V. 2010. All rights reserved. Rev. 02 — 27 January 2010 29 of 31 PCA9691 NXP Semiconductors 8-bit A/D and D/A converter 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 17.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] PCA9691_2 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 02 — 27 January 2010 30 of 31 PCA9691 NXP Semiconductors 8-bit A/D and D/A converter 19. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.1.1 7.2 7.3 7.3.1 7.4 7.5 7.6 7.7 7.7.1 7.7.2 7.7.3 7.7.4 7.7.5 8 9 10 10.1 10.2 11 12 13 13.1 13.2 13.3 13.4 14 15 16 17 17.1 17.2 17.3 17.4 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Address map . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Control byte . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 D/A conversion . . . . . . . . . . . . . . . . . . . . . . . . . 8 Worst case example . . . . . . . . . . . . . . . . . . . . 10 A/D conversion . . . . . . . . . . . . . . . . . . . . . . . . 11 Reference voltage. . . . . . . . . . . . . . . . . . . . . . 13 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Characteristics of the I2C-bus. . . . . . . . . . . . . 14 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 START and STOP conditions . . . . . . . . . . . . . 14 System configuration . . . . . . . . . . . . . . . . . . . 15 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 15 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 16 Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 16 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 16 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 17 Static characteristics . . . . . . . . . . . . . . . . . . . . 17 Dynamic characteristics . . . . . . . . . . . . . . . . . 19 Application information. . . . . . . . . . . . . . . . . . 22 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 23 Soldering of SMD packages . . . . . . . . . . . . . . 26 Introduction to soldering . . . . . . . . . . . . . . . . . 26 Wave and reflow soldering . . . . . . . . . . . . . . . 26 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 26 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 27 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 28 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 29 Legal information. . . . . . . . . . . . . . . . . . . . . . . 30 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 30 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Contact information. . . . . . . . . . . . . . . . . . . . . 30 19 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 27 January 2010 Document identifier: PCA9691_2