STMICROELECTRONICS TEA2028

APPLICATION NOTE
TEA2028 - TEA2029
By : J-M. MERVAL & B. D’HALLUIN
SUMMARY
Page
TEA2028
I
II
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAIN FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
4
III
PIN CONNECTION (TEA2028B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
IV
INTERNAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
V
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
V.1
V.1.1
V.1.1.1
V.1.2
V.2
V.2.1
V.2.1.1
V.2.2
INTERNAL VOLTAGE AND CURRENT REFERENCES . . . . . . . . . . . . . . . . . . . . . . . .
1.26V Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Generator block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LINE SYNC. EXTRACTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Black Level Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memorizing the Sync Pulse 50% Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IC
Ratio calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ID
Sync Pulse Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FIRST PHASE LOCKED-LOOP STAGE ”φ1” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase Locked-loop ”φ1” Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Duty of Individual Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCO centered on 500kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Divider stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description of Building Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase comparator ”φ1” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCO (Voltage Controlled Oscillator) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
a. 503kHz Ceramic Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
b. Simplified Block Diagram of VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
c. Characteristics of the External Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
d. Study of the Internal Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
e. Characteristics of the non-linear Amplifier ”A4” . . . . . . . . . . . . . . . . . . . . . . . . . . . .
f. Voltage-frequency transfer characteristics of VCO . . . . . . . . . . . . . . . . . . . . . . . . .
”φ1” Time Constant Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Identification Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Characteristics of Loop φ1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Locking accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dynamic study. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
a. Long time constant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
b. Short time constant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase Comparator Inhibition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
6
6
6
6
7
7
8
V.2.2.1
V.2.3
V.3
V.3.1
V.3.2
V.3.2.1
V.3.2.2
V.3.2.3
V.3.2.4
V.3.3
V.3.3.1
V.3.3.2
V.3.3.3
V.3.4
V.3.5
V.3.5.1
V.3.6
V.3.6.1
V.3.6.2
V.3.7
AN407/0594
8
9
9
9
10
10
10
10
10
10
10
11
11
11
12
12
13
14
14
14
15
15
15
15
16
16
16
17
1/46
TEA2028 - TEA2029 APPLICATION NOTE
V.4
V.5
V.5.1
V.5.1.1
V.5.1.2
V.5.1.3
V.5.1.4
V.5.1.5
V.5.1.6
V.5.2
V.5.2.1
V.5.2.2
V.5.2.3
V.5.2.4
V.6.3.2
V.6.3.3
V.6.3.4
V.7
V.7.1
V.7.2
V.7.3
V.7.4
V.7.5
V.7.6
V.7.6.1
V.7.6.2
V.8
V.8.1
V.8.2
LINE SAW-TOOTH GENERATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SECOND PHASE LOCKED LOOP ”φ2” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Duty of Different Building Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
”φ2” phase comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flip-flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Line deflection stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation of Building Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase comparator ”φ2” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-pass filter f(p). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Line flip-flop (TEA2028 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
a. Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
b. T10 Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
c. 16ms Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
d. Auto-set to ”1” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
e. Maximum ”T10” value as a function of ”C1” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Line output stage & inhibitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
a. Inhibition at start-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
b. Inhibition during line flyback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
c. Safety inhibition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Line deflection stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Characteristics of Loop ”φ2” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Study of the static error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
a. Phase shift error in case of no adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
b. Study of shift adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VERTICAL DEFLECTION DRIVER STAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frame Sync Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frame Saw-tooth Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
60Hz standard switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functions of Frame Logic Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50/60Hz standard recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
a. 50Hz Standard Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
b. 60Hz Standard Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Vertical synchronization window - Free-running period. . . . . . . . . . . . . . . . . . . . . . . .
Frame blanking signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frame blanking safety (TEA2028 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SWITCHING POWER SUPPLY DRIVER STAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Operating Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics of the Internal Regulation Loop . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protection Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TV Power Supply in Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Regulation by primary controller circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Regulation by TEA2028 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MISCELLANEOUS FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Super Sandcastle Signal Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video and 50/60HZ Standard Recognition Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
19
20
20
20
20
20
20
20
20
20
21
21
21
22
22
22
22
22
22
23
23
23
23
25
25
25
26
26
27
27
28
28
29
29
29
29
30
30
31
31
32
32
33
34
34
34
34
35
35
35
VI
TEA2028 APPLICATION DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
V.5.2.5
V.5.2.6
V.5.3
V.5.3.1
V.6
V.6.1
V.6.2
V.6.2.1
V.6.3
V.6.3.1
2/46
TEA2028 - TEA2029 APPLICATION NOTE
TEA2029
VII
TEA2029 : DIFFERENCES WITH TEA2028 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37
VII.1
GENERAL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37
VII.2
VII.3
PIN BY PIN DIFFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TEA2029C PIN CONNEXTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37
37
VII.4
FRAME PHASE MODULATOR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37
VII.5
VII.6
FRAME BLANKING SAFETY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ON-CHIP LINE FLIP-FLOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
39
VII.7
AGC KEY PULSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40
VIII
APPLICATION INFORMATION ON FRAME SCANNING
IN SWITCHED MODE (TEA2029 ONLY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40
VIII.1
FUNDAMENTALS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40
VIII.2
VIII.3
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TYPICAL FRAME MODULATOR AND FRAME OUTPUT WAVEFORMS . . . . . . . . . . .
40
41
VIII.4
FRAME POWER STAGE WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
42
VIII.5
FRAME FLYBACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VIII.6
FEED-BACK CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VIII.6.1 Frame Power in Quasi-bridge Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VIII.6.1.1 Choice of ”R” value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VIII.6.1.2 Influence of R3 value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VIII.6.1.3 ”S” Correction circuit in quasi-bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . .
VIII.6.2 Frame Scanning in Switched Mode using Coupling Capacitor . . . . . . . . . . . . . . . . . . . .
VIII.6.3 Frame Safety. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VIII.7
FRAME SCANNING IN CLASS B (WITH FLYBACK GENERATOR) . . . . . . . . . . . . . . .
VIII.7.1 Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
43
43
43
43
44
44
45
45
45
IX
46
TEA2029 APPLICATION DIAGRAM COMPLETE APPLICATION WITH TEA2164 . . .
I - GENERAL DESCRIPTION
As depicted in Figure 1, the TEA2028 combines 3
major functions of a TV set as follows :
- Horizontal (line) and vertical (frame) time base
generation for spot deviation. The video signal is
used for the synchronization of both time bases.
- On-chip switching power supply controller synchronized on line frequency.
This integrated circuit has been implemented in
2
bipolar I L technology, and various functions are
digitally processed. In fact, resorting to logic functions has the advantage of working with pure and
accurate signals while full benefit is drawn from
high integration of logic gates (approx. 110 gates
per mm2).
The main objective is to drive all functions using an
accurate time base generated by a master 500kHz
oscillator.
Also, horizontal and vertical time bases, are obtained by binary division of reference frequency.
This has the advantage of eliminating the 2 adjustments which were necessary in former devices.
One section of this integrated circuit is designed to
drive a switching power supply of recent implementation called ”master-slave”. Switching takes place
on the primary side (i.e., directly on mains) of a
transformer. The device ensures SMPS Control,
Start-up and Protection functions. Control signals
go through a small pulse transformer thereby providing full isolation from mains supply.
This new approach fully eliminates the bulky mains
transformers used in the past. In addition, it offers
optimized power consumption and reduction of TV
cost-price.
3/46
TEA2028 - TEA2029 APPLICATION NOTE
Figure 1
UHF
SOUND
I.F.
SOUND
DETECTION
PICTURE
I.F.
PICTURE
DETECTION
I.F.
SEPARATOR
PRIMARY
CONNECTED
SMPS
SMPS
CONTROLLER
SYNC
SEPARATOR
VERTICAL
TIME BASE
VERTICAL
POWER AMP.
HORIZONTAL
TIME BASE
HORIZONTAL
POWER AMP.
TEA2028B
Miscellaneous
Power Supplies
II - MAIN FUNCTIONS
- Detection and extraction of line and frame synchronization pulses from the composite video
signal.
- Horizontal scanning control and synchronization
by two phase-locked loop devices.
- Video identification.
- 50 or 60Hz standard recognition for vertical scanning.
- Generation of a self-synchronized frame sawtooth for 50/60Hz standards.
- Line time constant switching for VCR operation
through an input labeled ”VCR” (Video Cassette
Recorder).
- Control and regulation of a primary-connected
switching power supply by on-chip controller device combining :
• an error amplifier
• a pulse width modulator synchronized on line
frequency
• a start-up and protection system
- Overall TV set protection input
- Frame blanking and super sandcastle output signals
- Frame blanking safety input for CRT protection in
case of vertical stage failure.
III - PIN CONNECTIONS
Pin
1
2
3
4
5
6
4/46
Description
Horizontal output monostable capacitor
Frame blanking safety input
Frame saw-tooth output
Frame blanking output
Frame ramp generator
Power ground
Pin
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Description
SMPS control output
Supply voltage (VCC)
SMPS regulation input
Horizontal output
Super-sandcastle output
Horizontal flyback input
Horizontal saw-tooth generator
Current reference
SMPS soft-start and safety time constant
capacitor
φ2 phase comparator capacitor
(and horizontal phase adjustment)
VCO phase shift network
VCO output
VCO input
Frame sync time constant adjustment capacitor
Substrate Ground
φ1 phase comparator capacitor
VCR switching input
Video and 50/60Hz identification output (Mute)
Video identification capacitor
Horizontal sync detection capacitor
(50% of peak to peak sync level)
Video input
Safety input
Package : DIP28
DIP28.EPS
Mains
Input
MISCELLANEOUS
FUNCTIONS
2028B-05.EPS
Video Signal
Miscellaneous
Power Supplies
COLOR
DECODING
RGB
UHF
2028B-02.EPS
V CC
FRAME
SAWTOOTH
OUTPUT
3
2
1
FRAME
BLANKING
OUTPUT
4
25
FRAME
BLANK
OUTPUT
FRAME
SAWTOOTH
OUTPUT
5
6
S.M.P.S.
OUTPUT
POWER
GROUND
FRAME
SAFETY
50/60
Hz
22
ϕ 1 INHIBITION TIME
CONSTANT SWITCHING
ϕ1 DET
7
V CC
8
S.M.P.S.
ϕ MODULAT.
SOFT STARTING
CIRCUIT
SWITCH ON/OFF
SAFETY CIRCUIT
FRAME TIMING
IDENTIFICATIONLOGIC
SAFETY
LOGIC
50/60Hz
2µs
VIDEO
IDENTIFICATION
VCR
INPUT
23
24
FRAME
SAWTOOTH
FRAME ERROR
AMPLIFIER
SAFETY
INPUT
HORIZONTAL
SYNCHRO
AND FRAME
SYNCHRO
VR 1.26V
28
FRAME
BLANKING
SAFETY
VIDEO INPUT
27
26
H. SYNC
TEA2028B
VCR SWITCHING
INPUT
50/60Hz
MUTING OUTPUT
20
9
V R 1.26V
H. INHIBIT
HORIZONTAL
LOGIC TIMING
SUBST
21
SUBSTRAT
GROUND
REFERENCE
CURRENT
VOLTAGE
10
11
12
13
14
15
16
17
3.3kΩ
V CC
HORIZONTAL
FLYBACK
INPUT
S SC OUTPUT
SUPER
SANDCASTLE
HORIZONTAL
OUTPUT
H. OUTPUT
ϕ2
18
V R 1.26V
H. SAWTOOTH
GENERATOR
LINE
MONOSTABLE
VCO 500kHz
19
503kHz
TEA2028 - TEA2029 APPLICATION NOTE
IV - INTERNAL BLOCK DIAGRAM
Figure 2
5/46
TEA2028 - TEA2029 APPLICATION NOTE
V.1.2 - Current reference
This is implemented using the 1.26V generator in
combination with an external resistor.
V - FUNCTIONAL DESCRIPTION
Majority of the on-chip analog functions were computer simulated and results such as temperature
variation, technological characteristic dispersion
and stability, have led to the enhancement and
implementation of actually employed structures. A
parallel in-depth study of the device implemented
in form of integrated sub-sections is provided to
analyze the overall performance in a TV set.
Figure 4
+
VCC
I REF
VBE1
1.26V
Band
Gap
Σ
V BE
dVO
=0
dt
V O = V BE + A . λ
= 1.26V
A
λ
+0.086mV/°C
T
with λ =
K⋅T
= 25.7mV at + 25oC
q
dλ K
= = + 0.086mV/oC
dT q
dVBE VBE(25’) − 1.26
=
= - 2mV/oC
dT
T
if Aλ = 1.26 - VBE
Then : VO = 1.26V (temperature-independant)
In practice, maximum drift due to temperature can
be + 0.23mV/oC
i.e., ± 1.5% for a ∆T of 80oC.
6/46
2028B-06.EPS
λ
GENERATOR
Thus, it follows that IREF is accurate and independent of both VCC and temperature.
A set of current generators proportional to IREF
current are used in various circuit blocks.
-2mV/°C
T
R EXT
3.32kΩ
1%
V14
1.26 + VBE1 − VBE2
=
REXT
REXY
Let’s I14 = I and VEB1 = VBE2
1.26
then : IREF =
= 380µA
REXT
Figure 3
I
VBE2
I 14
IREF ≈ I14 =
V.1.1.1 - Generator block diagram
V BE
14
V.2 - Line Sync. Extraction
Horizontal and vertical time bases should be synchronized with corresponding sync. pulses transmitted inside the infra-black portion of video signal.
The duty of this stage is to extract these sync
pulses. The output signal, called composite sync,
contains the vertical sync which is transmitted by
simple inversion of line sync. pulses.
The vertical sync pulse is then extracted from this
composite signal.
The main advantage of this arrangement is its
ability to operate at video input signal levels falling
within 0.2V to 3V peak-to-peak range and at any
average value.
The operating principle is to lock the black level of
the input signal (Pin 27) onto internaly fixed voltage
(VN) and then memorize the average voltage of the
sync pulse by using an integrating capacitor connected to Pin 26.
Finally, the composite sync signal is delivered by a
comparator the inputs of which are driven by V50%
and video signals.
2028B-07.EPS
V.1 - Internal Voltage and Current References
V.1.1 - 1.26V Voltage reference
For optimum operation of the device, an accurate
and temperature-stable voltage generator independent from VCC variations is used (Band-gap
type generator).
The generated 1.26V is particularly used as reference setting on input comparators.
TEA2028 - TEA2029 APPLICATION NOTE
Figure 5
Black
Level
tr
VPP
Sync
Level
t S’
Composite Sync.
Output Signal
TH
2028B-08.EPS
Video
Input
Signal
Frame Sync.
V.2.1 - Black level locking
Figure 6
+
VCC
VP
IC + ID
V S1
V N = 2V
V
27
Video
-14
V N = 2V
C27
C1
IC
2028B-09.EPS
V PP
IC
I D = constant
The ∆VS1 producedby ID during the line trace which
ID ⋅ tA
is : 14 ⋅
C27
must be equal to ∆VS1 during the time interval ”t1”,
IC ⋅ t1
i.e. : 14 ⋅
C27
TH − tR
IC tA
= =
It follows that :
ID t1
tR − tS
The video signal is applied to Pin 27 through the
coupling capacitor ”C27”. Since the sync pulse
amplitude is generallyequal to 1/3 of VPP (i.e. 66mV
to 1V) and in order to obtain a good precision of the
black level, the sync pulse should be amplified by
a coefficient of - 14 before being applied to the
comparator ”C1”.
This comparator will charge the ”C27” capacitor as
long as VS1 > VN ⋅ VS1 will stabilize at VN during the
line flyback interval ”Tr” if the average charge of
”C27” capacitor is nil for one TH period.
IC/ID is calculated such that the locking occurs at
the middle of the back porch.
tS +
Figure 7
VS1
tS
VN (2V)
t1 =
VS1
tr tS
2
+ tS
t
tr
t
0
2028B-10.EPS
IC
-5µA
2
substituting TH = 64 µs, tr = 12 µs, tS = 4.7 µs (which
are standard and constant values) into above
IC
equation :
= 6.23V
ID
V.2.1.1 - Application
At IC = 5µA ⇒ ID = 31µA
- With C27 = 220nF, ∆VS will be
5 ⋅ 52
= 16mV
14 ⋅
220
which yields 0.8% maximum error in black level
with respect to VN = 2V at the beginning of retrace
time
- Due to transposition on amplifier stage, the black
level voltage on Pin 27 is equal to 2V.
7/46
TEA2028 - TEA2029 APPLICATION NOTE
- In practice, at low amplitude video signals, it is
recommended to insert a low-pass filter before
the ”C27” capacitor so as to attenuate the chrominance sub-carrier and the noise components.
The aim is to reduce the phase variations of the
detected sync pulse and thus enhance the horizontal scanning stability.
During the line scanning, diode ”D” is reverse biased : VS1 + VD = V1 < V26 and C3 will deliver a
current ID which will discharge the capacitor.
During sync pulse interval, VS1 + VD = VP + VD,
diode ”D” begins conducting and thus :
V1 = (VP + VD) - (2 R i1). Since the capacitor has
been slightly discharged ⇒ V1 > V26, comparator
C3 begins charging the capacitor until C2 is
brought to equilibrium.
V26 − VD − VN
i
At this time, I1 = where i =
R
2
i
thus V1 = VP + VD = 2 = VP + VN + 2 VD - V26
2
VP + VN
+ VD = V50%
and V1 = V26 ⇔ V26 =
2
A high value C26 capacitor will thus memorize the
voltage level correspondingto 50% of the line sync.
pulse.
Figure 8
+
V CC
1kΩ
220nF
100pF
1kΩ
Chroma
2028B-11.EPS
27
Burst
V.2.2 - Memorizing the sync pulse 50% value
The objective is to memorize the voltage corresponding to 50% of the line sync pulse VS1 by using
an external capacitor connected to Pin 26 (see
Figure 9).
The overall arrangement comprises two comparators.
- Comparator C2 : delivers an output voltage ”V1”
by comparing VS1 + VD, V26 and the voltage drop
across two resistors.
- Comparator C3 : which delivers a constant output
current thereby maintaining on capacitor ”C26”,
the voltage V50% corresponding to 50% of peak
to peak sync pulse.
V.2.2.1 -
IC
Ratio calculation
ID
During the line scanning period (TH - TS), the
capacitor C26 will loose a charge equivalent to :
ID (TH - TS).
This energy must be recovered before the end of
sync pulse such that : IC ⋅ tS > ID (TH - TS)
IC
IC TH − tS
> 12.6
therefore >
ID
tS
ID
In practice, for C26 = 100nF, ID = 25µA and
IC = 800µA.
Figure 9
+
VCC
xK
IC
VS1 + V D
VP + VD
tS
V 50%
ID
+
VCC
i1
V 50%
V 50%
D
V1
I 26
C26
i
IC
0
t
ID
R
V 26
VN
8/46
t
26
C2
V S1 + V D
VN + VD
0
V 50%
t
2028B-12.EPS
2R
t
0
V1
TEA2028 - TEA2029 APPLICATION NOTE
V.2.3 - Sync pulse detection
This function is fulfilled by comparing the inverted
video signal (VS1 + VD) whose black level is constant at 2V, with the sync 50% voltage level on
Pin 26 (see Figure 10).
Comparator C4 will deliver the line sync pulse (LS)
which will be used for 3 functions :
- Horizontal scanning frequency locking : output to
ϕ1 phase comparator.
- Frame sync extraction for vertical scanning synchronization.
- Detecting the presence of a video signal at circuit
input.
The LS signal in two latter functions is filtered for
noise by using combination of current generator I
and a zener diode equivalent to a capacitor.
Using this extraction technique at a very noisy
video signal yields remarkable display stability.
The device also provides for scanning synchronization at aerial signal attenuation of approximately
75dB, i.e. 15 to 20dB better than other sync processors.
V.3 - First Phase Locked-loop Stage ”ϕ1”
This stage is commonly called the first Phase
Locked-Loop ”ϕ1”.
Its duty is to lock the frequency and the phase of
the horizontal time base with respect to the line
sync signal.
In the absence of transmission (i.e. lack of line
sync), the horizontal scanning frequency is obtained by dividing the output frequency of a VCO
device. This VCO oscillates at approximately
500kHz and uses a low frequency drift ceramic
resonator. This method eliminates the need of horizontal frequency adjustment.
Figure 10
+
V CC
+
V CC
I
26
V50%
+
VS1 + VD
V50%
C4
i
3V
Frame
Separator
+
Video at Pin 27
I
C
LS
LS
On Video
Recognition Output
2028B-13.EPS
LS
Line Sync. Output
toward Phase Comparatorϕ1
250ns
V.3.1 - Phase locked-loop ”ϕ1” block diagram
Figure 11
Phase Comparator
φ IN
+
∆ϕ
ϕ1
φ OUT
1
P
A
(mA/rd)
ωS
i
LOW-PASS
FILTER
F(P)
BY-32-DIVIDER
STAGES
Horizontal
Frequency
ω1
Ve
VCO
B (kHz/V)
2028B-14.EPS
LS
Ceramic Resonator
9/46
TEA2028 - TEA2029 APPLICATION NOTE
component
- φIN - φOUT difference being low :
sin (φIN - φOUT) ≈ φIN - φOUT
- the output current will be therefore proportionalto
the phase difference between the signals compared.
In other words, the average current over one period
is :
 tS
  tS

IAV ⋅ TH = I  + ∆t  - I  − ∆t  = 2I ∆t
2
2

 

TH
∆t
and ∆t = ∆Φ
IAV = 2I
2π
TH
The comparator conversion gain is thus :
i
I
A=
= (in A/rd)
∆Φ π
Later in our discussion we shall consider the two
possible values of the current I.
For the time being, let’s define these values as
follows :
- I = 500µA for ”long time constant” or normal
operation
- I = 1.5mA for ”short time constant” VCR mode or
synchronization search (Mute).
The values of A are therefore :
- ALONG = 0.16mA/rd
- ASHORT = 0.47mA/rd
Use of comparator inhibition signal is quite useful
under noisy transmission conditions. It eliminates
risk of incorrect comparison during the line scanning phase which would be due to the noise present
on LS signal. Horizontal phase and image stability
are thus highly enhanced.
Characteristics of this inhibition signal will be discussed at the end of this chapter.
V.3.2 - Functional duty of individual blocks
V.3.2.1 - Phase comparator
The duty of this comparator is to issue an output
current proportional to the phase difference between φIN and φOUT.
V.3.2.2 - Low-pass filter
This filter suppresses the parasitic component containing the sum of phases, smoothens the phase
difference component and determines the timing
characteristics of the loop.
V.3.2.3 - VCO centered on 500kHz
This is a voltage-controlled oscillator which generates an output frequency proportional to the voltage applied to its input.
This voltage is delivered by low-pass filter.
V.3.2.4 - Divider stage
It is used to divide the VCO frequency (500kHz) by
32 so that it can be compared with the line sync
signal frequency of 15625Hz.
V.3.3 - Functional description of building blocks
V.3.3.1 - Phase comparator ”φ1”
The comparator is functionally equivalent to a signal multiplier (see Figure 12).
Let’s assume that :
- iLS = I sin (ωH t + φIN) and Vφ1 = k cos (ωHt + φOUT)
then :
- i=
iLS ⋅ k
2
[ sin (ΦIN - Φ OUT) + sin (2ωHt + Φ IN + Φ OUT)]
(see Figure 13)
- the low-pass filter will suppress the 2fH frequency
Figure 12
+
V CC
LS = 1
0
V φI
φ OUT
iO
1.26V
1.26V
φ IN
Video Recognition
VCR Mode
Switching
10/46
1mA
≤1
LS
I
500µA
&
Long ϕ1 inhibition
2028B-15.EPS
2I
I+
I-
i LS
V CR
TH
i
vϕ1 Signal
Mute
tS
∆t
TEA2028 - TEA2029 APPLICATION NOTE
Figure 13
frequency as follow :
1+j
i LS
f(jf) = R
f 
f 

 1 + j f2   1 + j f3 



with R1 = 4.7kΩ, R = 500kΩ, C1 = 2.2µF, C = 10nF
we obtain :
1
- f1 =
= 15.4Hz
2π R1 C1
1
- f2 =
= 0.14Hz
2π (R C1 + R C + R1 C1)
- f3 = 3.43kHz
I
tS
0
t
ϕe
vϕ1
t
ϕ OUT
Figure 15
i
I+
20 log |f|
2028B-16.EPS
I-
20 log R
f2
f1
f
0
2
VCO
22
V
10nF
ϕ1
R1
C
Comparator
R
V
C1
R is the dynamic input resistance of the VCO.
The filter transfer function may be defined as follows :
V
- f(p) = = Z(p)
i
- Z(p) = R
1 + R1 C1 p
V.3.3.3 - VCO (Voltage Controlled Oscillator)
Its function is to generate a frequency proportional
to a control voltage issued externally, by the lowpass filter in our case.
The period of the output signal is used as timing
reference for various functions such as, horizontal
and vertical time bases. The frequency range must
be short and accurate :
- It must be short since the power dissipated within
the horizontal scanning block is inversely proportional to the line frequency.
- The accuracy is required if the adjustment is to
be omitted.
The basic arrangement is to employ a ceramic
resonator (or ceramic filter) which has quite stable
characteristics as a function of frequency.
A filter whose resonating frequency is a multiple of
line frequency (15625Hz) is to be selected. An
example is 32 ⋅ 15625 = 500kHz.
A. 503kHz CERAMIC FILTER
Figure 16
Figure 17
Equivalent Circuit
R1
Symbol
2
1 + p (R C + R1 C1 + R C1) + R R1 C C1 p
The second order terms of the denominator can be
converted to first order products as a function of
2028B-19.EPS
C1
2.2µF
i
C
2028B-17.EPS
R1
4.7kΩ
f
π
VCO
Stage
i
15.4Hz 3.43kHz
Arg (z)
Figure 14
5.6V
(log scale)
0
0.14Hz
V.3.3.2 - Low-pass filter (see Figure 14)
Its main function is to reject the 2fH (31kHz) frequency component delivered by the phase comparator.
It also defines the characteristics of the loop in
transient mode.
The filter is built around two sub-sections which
determine the stability and the response time of the
loop in the following modes of transmission :
Normal or VCR modes. See section V.3.6 ”Dynamic study of φ1”.
f3
2028B-18.EPS
t
L1
C1
2028B-20.EPS
+1
0
-1
f
f1
C0
11/46
TEA2028 - TEA2029 APPLICATION NOTE
Where :
R1 = 7Ω, L1 = 1.26mH, C1 = 78pF, C0 = 507pF
- Series resonance frequency :
1
= 503kHz
fS =
L1 C1
2π √

- Parallel resonance frequency :
The overall arrangement is equivalentto a variablephase amplifier configured in closed loop with the
external passive filter.
The system will oscillate if the open-loop gain is
0dB and if VOUT leads VIN.
In closed-loop oscillating mode, the phase variation
of V18/VIN imposed by V22 will result in same
VOUT/V18 variation but of opposite sign.
This phase change will finally correspond to a
change in frequency.
C1
1+
= 540kHz
√
C0
- Tolerance within the resonance area :
503kHz ± 0.3 %
- Temperature stability : ± 0.3% of fO at ∆T = 100oC
Figure 20
Figure 18
V22 Phase Control
ϕ
A mp.
10 3
10 2
19
10
Filter
550
fP
600
VOUT
(open-loop)
2028B-21.EPS
PHASE ϕ
(Degrees)
+90
0
-90
B - SIMPLIFIED BLOCK DIAGRAM OF VCO
Figure 19
5.6V
R
220Ω
I1
+
Non-linear
Amplifier
A4
φ VOUT / V18 (Degrees)
R1
1.8
kΩ
A3
+
17
+
I3
1.2kΩ
1.2kΩ
ϕ1
V S1
-30
C1
150
pF
φ
-24°
-90
R
220Ω
1.1 VDC
20 log
Working Area
I2
Comparator
C. - CHARACTERISTICS OF THE EXTERNAL
FILTER
The ceramic resonator behaves as a capacitor at
f < fS (fS : series resonance frequency) and as an
inductor at frequenciesfalling between its two resonance frequencies.
Combined with a ”R.C” network to generate a 90o
phase lag, the overall arrangement will exhibit the
following characteristics : see Figure 21
Figure 21
18
22
i
2028B-23.EPS
500
fS
450
V 18
VIN
-150
503kHz
2.4kΩ
480
R
440Ω
-10
12/46
V18
C
1.5nF
2028B-22.EPS
500Ω
500
Frequency
(kHz)
520
503kHz
19
A1
19
V18
-20
-135°
Atten
uatio
n
A2
2mA
VOUT
(dB)
V18
VOUT
2.4kΩ Resistor = Pin 19 Input Resistance
2028B-24.EPS
1
V 22
18
2.4kΩ
IMPEDANCE |Z| (Ω)
10 4
Atten
uatio
n
fP = fS ⋅
TEA2028 - TEA2029 APPLICATION NOTE
The Figure 24 illustrates the characteristics of
V18/VIN phase versus VC.
- Phase variation determined by VC falls between
+24o and +135o range
- The gain is higher than 10dB. The Pin 18 output
signal of 30 to 40dB has a rectangularcomponent
(see Figure 24).
Figure 22
R1
18
17
i 18
i1
V 18
R
i
18
i2
C1
17
i 18
i1
V 18
R
Z
i 2’
2028B-25.EPS
D. - STUDY OF THE INTERNAL AMPLIFIER
V18
Let’s study the gain and phase response of
as
VIN
a function of V22.
VC
where K is a non-linear coefficient
V22 =
K
To start with, the ”VC” voltage of comparator ”A3”
is taken as reference parameter.
The dynamic representation of the output stage
can be depicted as below (Figure 22).
i2
with : I2’ =
(at f = 500kHz)
1 + jω R1 C1
i2
R1 C1 ω = 1 ⇒ i2’ =
1+j
1
and Z = R1 +
<< R ⇔ i ≈ i2’
jω C
R1C1 network produces -45o phase lag of ”i” with
respect to ”i2”, around 500kHz.
V18 ≈ - R ⋅ (i1 + I2’)
i1 and i2 calculation as a function of ”VIN” on Pin 19
VS1 RC 1200
- A1 Amplifier :
=
=
= 21
VIN dr1
57
λ
dr : dynamic resistance =
I
- A2 Amplifier :
i2
VS1 i2
i2
1
1
⇔
=
=
=
⋅
= 0.395
VS2 2dr2 54
VIN VIN VS1
⇒ i2 = 0.39 VIN, i2 is in phase with VIN therefore :
i3 = -i2 = -0.39 VIN
- A3 Amplifier :
 − VC 1 
 − VC 1 
+  = - 0.39 VIN 
+ 
i1 = i3 
2
2
Aλ


 Aλ
”VIN” always leads the ”i1” by 180, only the amplitude of i1 is a function of VC (see Figure 23).
VOUT
i1 (1 + j R1C1ω) + i2
=- R
VIN
1 + j (R1 + R) C1ω
 i VC 
- i1 = - 0.39 VIN  −
 and i2 = 0.39 VIN
 2 4λ 
Figure 23 : Vector Representation of V18/VIN
V18 @ i 1 = 0
VOUT
phase variation = f(VC )
VIN
+136°
Ri 1
V18 @ i 1 (Max. )
R (i 1 + i 2)
-45° VIN
R ( i 1 + i 2)
2028B-26.EPS
Thus, a variable (24o to + 135o) phase lead with a
gain higher than 10dB, must be implemented onchip so as to enable the system to enter into
oscillation.
The frequencydead points correspond to the maximum internal phase variations. This phase shift is
controlled by voltage V22 whose value of 5.6V ± 0.7
is determined by two diodes.
From the Figure 21, the non-linearity of phase-frequency characteristics is clearly apparent. If linear
voltage-frequency response is required for a symmetrical gain of φ1 loop, it would then be necessary
to implement a non-linearity, on the phase control
amplifier A4, but in the opposite direction.
Ri 2
13/46
TEA2028 - TEA2029 APPLICATION NOTE
Figure 24
Figure 26 : I22 = F(V22)
ΦV OUT / VIN (Degrees)
20 log
VIN
(dB)
V1 8
0.7
I 22 (µA)
200
40
120
A
30
0.5
80
20
0.4
-100
-50
0
50
100
VC (mV)
2028B-27.EPS
-150
F - VOLTAGE-FREQUENCY TRANSFER
CHARACTERISTICS OF VCO (see Figure 27)
The transfer characteristic is linear and centered at
5.6V at 500kHz operating frequency.
∆f
Ttransfer =
= 22.4kH/Vz and once it goes through
∆V
22.4
five divide-by-two stages : T =
= 0.7kHz/V
32
5.6
520
6
6.5
518kHz
T = 22.4kHz/V
500
480
4
5
6
7
Pin 22 VOLTAGE ” V22 ” (V)
V. 3.4. - ”φ1” Time constant switching
When switching between stations or receiving signal via a VCR, the loop locking interval must be as
short as possible so as to avoid unwanted visible
effect on the picture. In fact, since the synchronization between the VCR motor drive and the playback head is rather imperfect, it will produce
frequency and phase fluctuations in the output
composite video signal. Under these conditions,
phase locking interval must be ”short” (VCR Mode).
Figure 25 : VC = F(V22)
VC (mV)
A = 25mV/V
50
A = 50mV/V
In the case of broadcast transmission, this loop
must also filter all phase variations produced by
noisy sync signal. In this case, its locking time
constant must be ”long” (normal mode).
0
-50
V22 (V)
-150
5
5.5
6
6.5
7
2028B-28.EPS
A=
300mV/V
-100
14/46
5
Figure 27
PIN 18 FREQUENCY (kHz)
E - CHARACTERISTICS OF THE NON-LINEAR
AMPLIFIER ”A4” (see Figures 25 and 26)
This is a differential amplifier whose equivalent
feed-back resistors of emitters vary as a function of
its input voltage.
The maximum output voltage swing is set by two
”clamp” diodes connected to ”V22” input.
100
dV22
di 2 2
= 820kΩ
V2 2 (V)
ϕ
0
-200
dV2 2
= 33MΩ
di 2 2
2028B-29.EPS
0.6
A
40
dV2 2
= 500kΩ
di 2 2
In other ”jungle” circuits, this time constant switching is carried out by capacitor switching within the
filter loop. In our case, this function is achieved by
changing the current amplitude of the phase comparator.
2028B-30.EPS
160
TEA2028 - TEA2029 APPLICATION NOTE
This amplitude changing modifies the open-loop
system gain and therefore the damping coefficient
and the locking time constant.
The device will be in short time constant mode
under the following two conditions :
- VCR Mode or SCART Connector Mode :
This mode is enabled by a low state on Pin 23.
V23 < 2.1V.
- Transmitter search and tunning.
In order to accelerate the capture, a ”Video Identification” stage will detect the presence or the
absence of a video signal on input Pin 27, and
deliver accordingly a signal called ”Mute”.
Figure 29
ϕ1
Line Sync.
LS
4.7µs
2µs
2µs
IC(25)
IC
with Video
IC(25)
without Video
V.3.5 - Video identification stage
This stage will detect the coincidence between the
line sync pulse (if present) and a 2µs pulse issued
from the logic block. This 2µs pulse at line frequency is positionned at the center of line sync
pulse when the first loop ”ϕ1” is locked.
This sampled detection is stored by an external
capacitor connected to Pin 25. The video recognition status is also available on Pin 24 so as to
enable Sound Muting during station search process and the inhibition of Automatic Frequency Tuning.
ID
Mute
Output
1
VL VH
4.6V
V.3.5.1 - Block diagram
Figure 28
+
&
2µs
LS
&
ϕ1
Comparator
IC
750µA
ID
i C(25)
Pin
24
500µA 25
C25
4.7nF
4.6V
Frame
Logic
The video recognition signal is delivered by a hysteresis comparator.
The recognition time ”TR” is adjustable by an external capacitor, as soon as ϕ1 is locked :
2µs
- IC25(AV) = IC ⋅
64µs
and :
VH
- TR = C25 ⋅
= 1.96 ⋅ 105 ⋅ C25
IC25(AV)
with C25 = 4.7nF ⇒ TR = 1ms
(which is clearly quite fast)
2028B-31.EPS
LS
2028B-32.EPS
VHYST = 0.3V
0
V25
V.3.6 - Characteristics of loop φ1
V.3.6.1 - Locking accuracy
Let’s study the phase error ”ϕOUT - ϕIN” under
steady state conditions :
The open-loop gain is :
AB f(p)
- T(p) =
f
Where :
A = 0.16mA/rd (long time constant)
A = 0.47mA/rd (short time constant)
B = 0.7kHz/V or B = 4.4 103rd/s
1 + τ1 p
- f(p) = R ⋅
(1 + τ2 p) (1 + τ3 p)
Where : R = Dynamic input resistance of VCO.
If a phase step of ∆ϕ is applied to the input, the
following would be obtained as a function of (p) :
∆Φ
ΦIN(p) =
p
Using the last value theorem : lim f(t) = lim p . f(p)
Let’s calculate lim (ϕIN − ϕOUT)
p→0
- The closed-loop gain is :
ΦOUT(p)
ABf(p)
T(p)
=
=
- H(p) =
1 + T(p) p + ABf(p)
ΦIN(p)
p∆Φ
that is : lim p (ΦIN − ΦOUT) = lim
→0
p
+
AB f(0)
p→0
p−>0
15/46
TEA2028 - TEA2029 APPLICATION NOTE
It is therefore deduced that the system can follow
all input phase variations without producing any
static error.
In practice, there will be a slight error due to the
input bias current ”IB” of VCO, which is 0.55µA at
fO = 500kHz. This DC current is delivered by a
phase comparator which will generate a phase
error of :
- long time constant :
IB
10−3
= 0.55 ⋅
∆ΦLONG =
ALONG
0.16
= 3.4 ⋅ 10-3 rd or 35ns in ∆t
IB
= 12ns
- short time constant : ∆ΦSHORT =
ASHORT
These two errors cause a horizontal picture displacement. On a large screen of 54cm wide, this
will be : 64 - 12 = 52µs, which for both modes
corresponds to a shift of :
∆ΦLONG−∆ΦSHORT
⋅ 520 = 0.24mm
∆LINE =
52
It is obvious that such displacement can be fully
neglected.
Response to a Frequency Step
- The input phase is : ΦIN(t) = ∆ωt
which as a function of (p) is : ΦIN(p) =
- The accuracy is :
∆ω
p2
∆ω
∆ω
=
o
)
p
+
ABf(
ABR
p−>0
p−>0
where R = 500kΩ at f(o)
In this case, the phase error depends on both, the
magnitude of the frequency step and the static gain
ABR.
∆f
In general, which is the open-loop static gain, is
∆f
taken into consideration.
2π∆f
∆ω
= A ⋅ 2 π ⋅ B’ ⋅ R
= ABR =
∆t × 2π
∆Φ
∆f
2π
⇒
= AB’R ⋅
(B’ in kHz/V)
∆t
TH
- In normal mode : ALONG = 0.16 mA/rd
∆f
⇒
= 5.5kHz/µs, R = 500kΩ
∆t
lim (ΦIN − ΦOUT) = lim
16/46
- In VCR mode : ASHORT = 0.47 mA/rd
∆f
⇒
= 16.5kHz/µs
∆t
Note : The capture range is specified within
± 500Hz with respect to 15625Hz.
Numerical Example
Let’s suppose that in VCR mode there is a frequency variation of ± 100Hz, this will yield a phase
variation of 0.1/16.5, i.e. ± 6ns which, on a 54cm
wide screen, will produce a horizontal shift of
∆LINE = ± 0.06mm !
It is obvious that an excellent image stability is thus
obtained.
V.3.6.2 - Dynamic study
The loop response in transient mode is quite important. It determines the overall system stability
and the phase recovery time, which are imposed
by the external filter ”f(p)”.
The close-loop transfer function is equivalent to a
second order system. These time constants are in
practice displayed on screen by a bar delivered by
a special pattern generator representing the phase
errors.
The following optimizedresults were obtained from
filter f(p) connected to Pin 22.
Filter component values are :
R1 = 4.7kΩ, C1 = 2.2µF, C = 10nF
A. LONG TIME CONSTANT
- At ∆t of 4µs ⇒ N=18 lines, i.e. τLONG = 1.15ms.
System oscillations are perfectly damped. Image
stability with a noisy video signal is very satisfactory.
B. SHORT TIME CONSTANT
- At ∆t = 4µs ⇒ N = 5 lines, i.e. τSHORT = 0.32ms
- n = 5 lines
One should notice fast phase recovery, naturally
followed by bounced oscillations due to the characteristics of a second order device.
As given in application diagram section 6, an other
alternative would be to use the following component values : R1 = 3.9kΩ, C1 = 4.7µF, C = 15nF.
TEA2028 - TEA2029 APPLICATION NOTE
V.3.7 - Phase comparator inhibition
The phase comparator is disabled under two conditions :
- During frame sync pulse (see Figure 30)
Inverting the line sync pulse contained within the
video signal will provide the frame sync pulses
required for the synchronization of vertical scanning.
Since the current supply to comparator φ1 is
controlled by the line sync pulse, the comparator
must be inhibited at the time of line sync inversions so as to avoid occurence of phase errors at
the beginning of each frame.
This inhibition is activated during FRI (Frame
Retrace Inhibition) issued by frame logic circuitry.
If φ1 is locked before the vertical scanning synchronization occurs, (e.g. when switching between channels), and since FRI phase is not yet
correctly positioned, the ϕ1 must be further inhibited by FS signal which is the extracted frame
sync pulse.
- During line scanning (see Figures 31 and 32)
This inhibition will eliminate the occurrence of all
possible phase errors due to a noisy sync signal
or parasitics during the line scanning phase. It
yields excellent display stability at noisy video
signals.
• f1 Inhibition in long time constant mode
(VCR = 0)
SINH(LONG) = Mute . (FRI + FS + BLK . LINEINH)
and SINH(SHORT) = 1
Inhibition is activated during, frame sync, FRI
and each time line trace interval - except at
frame beginning between lines 8 and 21.
• φ1 Inhibition in short time constant mode
(VCR = 1)
SINH(SHORT) = Mute . (FRI + FS) = SINH(LONG)
In VCR mode, inhibition is disabled during line
trace since phase or frequency variations are
not taken into account instantenously.
Figure 30 : On Screen Display of Time Constants
- 4µs shift
+ 4µs
- 4µs
N
n
N
Normal Mode
Long Time Constant
2028B-33.EPS
+ 4µs
VCR Mode
Short Time Constant
Figure 31
Inverted Pulses for Frame Sync.
VIDEO
COMPOSITE
SYNC.
FRAME
SYNC. (FS)
FRAME ϕ1
INHIBITION (FR)
FRAME
BLANKING
S INHIBITION
(normal mode)
Inhibition
In the abscence of Frame Inhibition
ϕ1 COMPARATOR
CURRENT
2028B-34.EPS
ϕ1 INHIBITION
SIGNAL (FRI + FS)
[VCR mode]
17/46
TEA2028 - TEA2029 APPLICATION NOTE
Figure 32
VIDEO
ON PIN 27
0.3µs
LINE SYNC .
2 .35µs 2.35µs
LINE
5.8µs
INHIBITI ON
2028B-35.EPS
ϕ1 SIGNAL
6.5µs
Inhibit ion
Inhibition
Figure 33 : ϕ1 Inhibition Logic Block Diagram
FRI
Video Recognition
Mute
ϕ1
LS
Line Sync.
500µA
&
≥1
FS
&
BLK
&
100µA
(short)
(Long)
Line Inhibition
SINH(L)
&
V.4 - Line saw-tooth generator
Before going through a detailedstudy of the second
phase locked loop ”φ2”, let’s have an overview of
the linesaw-tooth generator which has been mainly
implemented for φ2 phase variations and also the
phase modulation of the switching power supply.
It uses the combination of an external capacitor
connected to Pin 13 and an internally implemented
constant current generatorto generatea saw-tooth
voltage at line frequency.
Its frequency is determined by the reset frequency
Phase Comparator (ϕ1)
S INH(S)
2028B-36.EPS
&
VCR
of the capacitor ”C13”. This reset signal is issued
by the line logic circuitry at a period multiple of VCO
period (×32).
1.26
= 200µA
- IC = K ⋅ IR = K ⋅
R14
IC (TH − treset) K ⋅ 1.26 (TH − treset)
- V13PP =
=
C13
R14 ⋅ C13
= 3.48V
- VCE(SAT)T1 ≈ 20mV ⇒ V13(MAX) = 3.5V
- In sync mode :
TH = 64µs, tRESET = 6.5µs, K = 0.527 ± 2%
Figure 34
+
VCC
xK
IR
IC
V13
x1
To ϕ2
and SMPS
3.5 VPP
TH
64µs
0
Reset
IR
Constant
1.26V
t
13
R14
3.32kΩ
C13
3.3nF
T1
Reset
t
6.5µs
18/46
2028B-37.EPS
14
TEA2028 - TEA2029 APPLICATION NOTE
image centering, the line flyback must be phaselocked with respect to the video signal.
The second phase-locked loop also offers the possibility of horizontal phase-shift adjustment.
Figure 35
Blanking Time
Center of
Screen
VIDEO SIGNAL
ON CATHODES
LINE YOKE
CURRENT
0
Line Transistor
Collector Current
LINE
FLYBACK
t LF
12µs
0
LINE TRANSISTOR
CONTROL OUTPUT
64µs
Saturation
Turn-off
2028B-38.EPS
V.5 - Second Phase Locked Loop ”φ2”
This stage controls the horizontal deflection of the
electron beam i.e., the horizontal picture scanning.
The frequency of operation, in the absence of video
signal, is a multiple of the VCO frequency, i.e.
15625Hz - 500Hz.
When video signal is present, the scanning frequency is synchronized with the video signal
through the first phase locked-loop ”φ1”.
The output rectangular waveform signal drives the
line switching transistor. This transistor, when
turned-off, generates what is commonly called the
”line flyback”.
In order to obtain a horizontally centered picture,
the line flyback (LF) must coincidewith the blanking
time on tube cathodes.
The turn-off delay is due to transistor base storage
time. This time varies in different TV sets as the
transistors employed may have different operating
characteristics which are functions of temperature
variations, power rating and base drive.
Therefore, it follows that in order to obtain stable
Turn-off Delay
Figure 36 : Second Phase Locked Loop ”ϕ2” Block Diagram
Horizontal Phase
Adjustment
Video
(Pin 27)
16
1
f(p)
t IN
Line
Flyback
Phase
Modulator t’
OUT
ϕ2 Phase Comparator
∆t
A
mA/µs
i
Low-pass
Filter
t’OUT
Monostable
(29µs)
Output
Stage
(x 1)
10
29µs
V
t OUT
Inhibition
LF Pulse
Shaping
x1
Line
Yoke
EHT
Transformer
12
LF
t OUT
Line
Deflection
Stage
19/46
2028B-39.EPS
ϕ2
Signal
Constant
Delay
by ϕ1
TEA2028 - TEA2029 APPLICATION NOTE
V.5.1.3 - Phase modulator
Uses the line saw-tooth voltage to convert the
voltage delivered by the low-pass filter into a phase
corresponding to the line transistor turn-off control
signal.
V.5.1.4 - Flip-flop
Generates the turn-off control signal for a constant
time (fixed by the external capacitor), the phase of
which is set by the modulator.
V.5.1.5 - Output stage
- Delivers the control signal for line transistor driver
- Disables the output during start-up and protection
phases
V.5.1.6 - Line deflection stage
- Generates the saw-tooth current for line yoke
- Generates the high voltage required by picture
tube and other supply voltages
The line flyback information is provided by the
EHT transformer.
V.5.2 - Operation of building blocks
To provide an easier understanding of the subject,
the ”φ2” loop study will be covered as a function of
various time intervals and not as a function of
phase.
V.5.2.1 - Phase comparator ”φ2”
The operation is identical to that of ”φ1” loop.
The Vφ2 signal issued by logic block is phased with
respect to the middle of line sync pulse on Pin 27
and delayed by a 2.6µs interval so as to be at the
middle of blanking time on video cathodes.
The output current component ”2fH ” is rejected by
the low-pass filter.
20/46
VCC
i
Filter F(p)
Constant
Voltage
Vϕ2
Line
Flyback
(LF)
I
550µA
- The average current is i = 2I
2028B-40.EPS
V.5.1.2 - Low-pass filter
- Rejects the parasitic component ”sum of phases”
- Smoothens the ”phase difference” component
- Allow ”phase adjustment” by generating an error
within the loop
Figure 37
∆t
TH
Where : ∆t = tIN - tOUT
- The conversion gain is therefore :
i
2I
= 17µA/µs
A=
=
∆t TH
At : I = 550µA and TH = 64µs, ”A” will remain
constant since ”I” is a multiple of ”IREF” current on
Pin 14.
Figure 38
Videp on
Pin 27
Vϕ1
0.3µs
Vϕ2
2.6µs
i
+I
0
-I
TH
LF
∆t
t IN
t OUT
Video on
Cathodes
2028B-41.EPS
V.5.1 - Duty of different building blocks
V.5.1.1 - ”φ2” Phase comparator
This block generates a current proportional to the
phase difference between the phase reference ”φ2”
and the middle of the line flyback to be phaselocked.
TEA2028 - TEA2029 APPLICATION NOTE
V.5.2.2 - Low-pass filter f(p)
The horizontal phase-shift adjustment is taken into
account : see Figure 39
- Filter V = f(i) transfer characteristic is given as :
Z
V = Zi + ⋅ K ⋅ VCC - Z ⋅ IIN
R
Where :
1
• Z = RIN // R //
C⋅p
• RIN, IIN : modulator input characteristics
Figure 40
t’ OUT
16
V’OUT
2028B-43.EPS
V
V13 (t)
Figure 41
Figure 39
Phase Modulator
i
ϕ2
Comparator
V
R IN
V 13 (t)
3.5V
V
I IN
0
t1
t 2 = f(v)
V’OUT
16
TH
+
VCC
Vϕ2
t IN(ϕ2)
KVCC
Line Output
Signal (Pin 10)
C
In Dynamic Mode
V
R′
- V = Zi ⇒ f(p) = = Z(p) =
i
1 + τp
Where :
• R’ = RIN // R (R >> Potentiometer P)
• τ = R’ . C : Filter time constant
The network behaves as a first order low-pass filter
1
whose cut-off frequency at -3dB is : f-3dB =
2πR′C
Filter component values
- R = 470kΩ and C = 22nF
• In practice, (K ∈ [0,1]) VCC = 12V
- RIN = 25MΩ , IIN = 0.65µA (base input current)
• F−3db = 15.7Hz with adjustment and 0.3Hz without adjustment
V.5.2.3 - Phase modulator
This is built around a comparator which converts
the filter voltage to a rectangular waveform such
that its rising edge phase, variable as a function of
filter voltage ”V”, will trigger the line transistor turnoff control circuitry.
The conversion gain is determined by the slope of
the line saw-tooth applied to comparator.
t IN = 0
T 10 = constant
Line Flyback
(LF)
tD
t’OUT t OUT
Transfer characteristic is given by :
∆t′OUT ∆t13
=
= B = 16.4µs/V therefore t2 = B.V
∆V
∆V13
Let’s consider the delay interval between ”t OUT”
and the reference time ”tIN”
where tOUT is the middle of line flyback :
tOUT - tIN = t2 + td + t1 - tH
Where :
- t1 = 4.3µs
Reset for V13 and Vφ2 are signals coming from line
logic block and are synchronized on line sync
- td = 2 to 15µs
Delay between leading edge of output signal Pin 10 - and the middle of line flyback
- tH = 64µs
- tOUT - tIN = B.V + td - 59.7µs
V.5.2.4 - Line flip-flop (TEA2028 only for TEA2029
refer to Section VII.6)
It generates a constant duration rectangular signal
used to turn-off the line transistor. It is triggered by
the rising-edge of the phase comparator output
voltage and reset after capacitor on pin 1 is
charged.
21/46
2028B-44.EPS
R
2028B-42.EPS
Horizontal
Phase P
Adjust
TEA2028 - TEA2029 APPLICATION NOTE
A. BLOCK DIAGRAM
”V’OUT” will set the flip-flop thereby allowing the
capacitor ”C1” to be charged by current ”IC” delivered through current generator. The voltage across
capacitor begins rising until it reaches ”VREF ”. At
this time, comparator ”C” is triggered, the output of
which will in turn reset the flip-flop. The capacitor
”C” is consequently discharged by current ID - IC .
Figure 43
16µs
Set
Window
4µs
Auto-Set
V’OUT
Figure 42
(1.26V)
V1
t’OUT
16µs
Window
&
V’OUT
T 10
≥1
S
R
t’OUT
Q
V1 0
Q
VREF
t
0
V 10
To Output
T 10
Stage
IC
T 10
144µA
16µs
V REF
ID
1
V1
380µA
C1
B. T10 CALCULATION (see Figure 43)
C1 ⋅ ∆V1 C1⋅ VREF
T10 =
=
IC
IC
”IC” is a fraction of ”IREF” on pin 14
IREF
VREF
IC =
=
= 144µA
α
α ⋅ R14
⇒ T10 = α ⋅ R14 ⋅ C1 = 2.64 ⋅ R14 ⋅ C1
with R14 = 3.32kΩ, C1 = 3.3nF ⇒ T10 = 29µs
- T10 is independent from temperature and VCC
- α has a maximum dispersion of ± 3% from device
to device
C. 16µs WINDOW
This window is generated by the line logic circuitry
and sets the maximum phase variations of the
output signal ”V10 ”.
Also, for protection purposes, should ”V16” voltage
equal ”0”, the output signal will be always present
and have a maximum phase shift of 16µs with
respect to the falling-edge of the line saw-tooth.
D. AUTO-SET TO ”1”
To provide protection, this function will trigger the
f lip -flop if the modulato r is d isa bled, i. e.
V16 > V13(MAX).
22/46
2028B-45.EPS
C
Maximum
Phase
Variation
T 10
+
2028B-46.EPS
Signal
AS
E. MAXIMUM ”T10” VALUE AS A FUNCTION
OF ”C1”
T10 (Min.) : 16µs (window) + 4µs (auto set) = 20µs
⇒C1(Min.) = 2.3nF
C1 ⋅ VREF C1 ⋅ VREF
T10 (Max.) : for
+
≤ 64µs
ID − IC
IC
⇒T10 (Max.) = 40µs ⇒ C1(Max.) = 4.6nF
For normal operation, C1 value has to be chosen
between 2.3nF and 4.6nF.
If Pin 1 is grounded, output signal (Pin 10) is
inhibited and goes high.
V.5.2.5 - Line output stage & inhibitions
Figure 44
Line Flyback
Input
+
VC C
12
3V
RL
T10
I1 0
LF
T1 0
Monostable
Q
Logic 1 for
V C C < 6V
≥1
Output
10
To
≥1
Line ”DRIVE”
6
Inhibition
Logic 1 for
Security at Pin 28
Power
Ground
2028B-44.EPS
Auto-Set
TEA2028 - TEA2029 APPLICATION NOTE
- When K is closed :
ryt 
E
iL(t) =  1 − e − L 


ry
L
- is always higher than half of trace time :
ry
ttrace TH − tLF 64 − 12
=
=
= 26µs
2
2
2
- ”iL” variations as a function of time :
Figure 46
Open-collector output :
V10(SAT) < 1.5V at I10(MAX) = 20mA
The line output (Pin 10) will go high if either the
following three inhibitions is activated :
A. INHIBITION AT START-UP
This is generated by a hysteresis comparator which
is driven by ”KVCC” and the ”1.26V” reference
voltage.
This inhibition is mandatory since the device will
operate only at VCC ≥ 5V.
i L(t)
Deflection Yoke Resistance
ry
Deflection Yoke
Inductance (L)
1
V HYST = 0.5V
5.5 6
SUPPLY VOLTAGE (V)
B. INHIBITION DURING LINE FLYBACK
The output signal Pin 10 is high during line transistor turn-off. The leading edge of output signal
Pin 10 turns off the line transistor after a delay
interval (storage time).
The line transistor turn-off generates an overvoltage on the collector corresponding to the line
flyback pulse. During this interval, in order to avoid
transistor destruction, the Pin 10 output must absolutely remain high.
This is done internally with the line flyback pulse
(Pin 12), which forces Pin 10 output to high level
during the line flyback time.
C. SAFETY INHIBITION
The device has a security input terminal ”Pin 28”.
If a signal lower than VREF (1.26V) is applied to this
pin, line and power supply outputs are all inhibited.
This function is particularly useful for TV chassis
protection. Refer to section V.7.5 for further details.
V.5.2.6 - Line deflection stage
This chapter will cover a general description of the
”horizontal deflection stage” employed almost
commonly in all recent TV sets.
Deflection of electron beam is proportional to the
intensity of magnetic field induced by the line yoke.
This yoke is equivalent to an inductor. The deflection is therefore proportional to the current through
inductor.
In order to obtain a linear deflection from left to right
as a function of time, a saw-tooth current must be
generated within the yoke. The approachis toapply
a switched DC voltage to the line yoke.
K
2028B-49.EPS
0
E
2028B-48.EPS
LINE INHIBITION
(Logic Level)
Figure 45
C
diL E − ryt E 
L
= e L ≈  for t << 
dt L
ry 
L
The current will therefore be linear as a function
E
of time iL(t) = ⋅ t from ”t1” to ”t2” which is the
L
second portion of the line trace interval.
E tTRACE
- Current at the end of trace : IM = ⋅
2
L
1
- Energy stored within inductor : W = ⋅ L ⋅ IM2
2
If the switch is opened at t = t2, the ”L.C” combination will enter into oscillation, the energy stored
within inductor is transfered to the capacitor,
which will return it to the inductor and so on.
The circuit period is classically given by :
T = 2π ⋅ √

LC
If ”K” is closed at time ”t3”, the inductor will once
again have a voltage ”E” across its terminals. The
current falls linearly until ”t4”. This phase corresponds to the first half of line trace interval.
The overvoltage across C is :
ttrace
VP = E
+ E during tLF ≈ π 
√
LC
2√
LC
ttrace ⋅ π
+E
That is : VP = E
2tLF
In practice, E is higher than 100V.
ttrace = 52µs, tLF = 12µs ⇒ VP ≥ 780V
Note that this overvoltage is almost 8 times higher
than the source voltage ”E”. This overvoltage is
applied to the primary winding of a ”step-up transformer” (EHT Transformer) in order to generate the
high voltage required by picture tube anode.
23/46
TEA2028 - TEA2029 APPLICATION NOTE
In practice, the power switch ”K” is built by a
combination of ”High Voltage Switching Transistor”
and ”Fast Recovery Diode”.
If considered in average value, it is seen that the
voltage across capacitor”CS” is almost equalto the
source voltage ”E”. The saw-tooth current through
this capacitor will produce a parabolicripple around
”E”, which will thus modify the equivalent source of
the line yoke and induce a modified current of ”S”
shape within the yoke. This ”S” current is used to
produce a linear picture as a function of the picture
tube geometry.
The basic arrangement can be reconstructed by
assuming that the equivalent inductor ”L” is the
transformer ”LP” and line yoke inductors put in
parallel (since VC S(AV) = E).
The output Pin 10 of TEA2028 is applied to a
matching stage called ”line driver” the output of
which drives the power transistor ”Tr”. The matching stage is necessary for optimized base drive.
At middle of trace, the transistor enters into saturation and its current rises linearly. V10 will then issue
a control signal to turn the transistor off. The transistor will be in fact turned-off after a delay interval
”tS” (storage time) varying from 2 to 8 µs depending
on application. The system will then enter into
oscillation during its half-period thereby generating
the line flyback. At the end of flyback time, the line
yoke current is negative while the voltage across
capacitor”C” has fallen to zero. The energy transfer
automatically takes place by the recovery diode
during the first portion of trace time.
Also, it is clear that the line scanning phase with
respect to video signal is determined by the risingedge of Pin 10 output signal.
Figure 47
End of
Trace
iL
if K remains
open
t3
t4
0
t1
t2
Begining of
Trace
iK
0
iC
0
VC
VP
E
0
VL
t LF
2028B-50.EPS
E
0
Figure 48 : Simplified Diagram of the Horizontal Deflection Stage
EHT
TRANSFORMER
VEHT (anode)
E
(regulated by SMPS)
[15 to 25kV]
Miscellaneous Power Supplies
LP
Line Flyback
(Pin 12, TEA2028B)
ITr
Line Yoke
+12V
IY
Tr
D
ID
RL
10
C
C5
V C(5)
T DRIVER
Coup ling
TEA2028B
Li ne Flyba ck
Input
2028B-51.EPS
Capacitor
12
24/46
IC
TEA2028 - TEA2029 APPLICATION NOTE
Figure 49
R′
1 + τp
- R’ = RIN // R
- A = 17µA/µs
- τ = R’C
- B = 16.4µs/V
The open-loop dynamic gain is :
ABR′
(4)
T = ABf(p) = ABZ =
1 + τp
The system exhibits the characteristics inherent to
a first order circuit and is therefore stable.
Combining equations (1), (2), (3) and (4), the tOUT
delay is found as follows :
-Z=
S Correction
IY
Tr C
0
C
t
D
VCE
(Tr)
0
12V
0
t
tS
(turn-off delay)
I Tr
t OUT = t IN
0
2028B-52.EPS
0
t
High level duration (T10) of Pin 10 output signal
must be higher than the delay interval ”tS(MAX)” +
the flyback time (i.e. 8 + 12 = 20µs) and must
turn-off before the end of diode conduction :
ttrace
⇒ < 40µs
T10 < tS(Min.) + tLF +
2
1+T
+
Z
KV CC
R
1 +T
Figure 50
t OUT
A
i
f(p)
B
Delay
(td )
Middle
of
Scanning
Flyback
V
LF
- i = A . (tIN - tOUT)(1)
Z
- V = Z ⋅ i + ⋅ K ⋅ VCC - Z ⋅ IIN
R
- tOUT - tIN = B ⋅ V + td - 59.7µs
t OUT
(2)
(3)
2028B-53.EPS
∆t
Error term
Dynamic Error term
gain = 1 due to the due to delay
input current
”I IN ”
Error term due
to phase shift
adjustment
(if applicable)
V.5.3.1 - Study of the Static Error
tIN = 0 (phase of Vφ2) is taken as timing reference.
The equivalent impedance of F(p) filter is :
- R’ = 460kΩ (R // RIN) : if an adjustment is applied
to Pin 16, or
- Modulator input resistance RIN = 25MΩ : without
adjustment
V.5.3 - Characteristics of loop ”φ2”
The function to calculate is a time with respect to
the origin time set by ”Vφ2”. In fact, it is an easy task
to inter-relate the horizontal displacement (in mm)
to a time interval specified in µs.
For a large screen width of 540mm, the horizontal
scanning time : 64 - 12 = 52µs, which corresponds
to : ≈ 10mm/µs.
t IN
+
B
It is therefore clear that the second phase-locked
loop does not cause any dynamic delay.
This can be explained by the fact that the phase
modulator responds instanenouslyto all variations
of ”φ2”.
In practice, one will select the pin 1 capacitor
C1 = 3.3nF to yield T10 = 29µs.
Vϕ2
1+ T
t D 59.7µs
t
ID
t IN
BZI IN
A. PHASE SHIFT ERROR IN CASE OF
NO ADJUSTMENT
Equation (5) becomes :
BRIN IIN tD − 59.7µs
TOUT =
+
1 + T1
1 + T1
with : T1 = ABRIN
Where :
- RIN = 25MΩ
tOUT = - 46ns
- IIN = 0.65mA
which corresponds to a
- td = 10µs
picture shift of 0.46mm !
- T1 = 6.8 ⋅ 103 = 76dB
The error is quite negligible and thanks to rather
high open-loop gain, the display accuracy with
respect to the phase set by ”φ2”, is very satisfactory.
25/46
2028B-97.EPS
V10
t
12µs
T10
29µs
TEA2028 - TEA2029 APPLICATION NOTE
B. STUDY OF SHIFT ADJUSTMENT
With R, P network connected to Pin 16, the tout
becomes :
R′
B
⋅ KVCC
− BR′ IIN tD − 59.7µs
R
+
+
tOUT =
1+T2
1 + T2
1 + T2
With : T2 = ABR’ (where R’ = R // RIN) and K ∈ [0;1]
Substituting the following values into above equation :
- R = 470kΩ
- R’ = 470kΩ // 25MΩ = 46kΩ
- A = 17×10-6 A/µs
- B = 16µs/V
- td = 10µs
- T2 = 125
- VCC = 12V
- tOUT = - 38ns - 390ns + 1.5µs×K
therefore t out = 1.5⋅ K - 0.43 ( in µs )
If K varies between 0 and 1
⇒ tout [- 0.43ms to 1.07µs]
which corresponds to a picture displacement of :
∆LINE [- 4mm to + 11mm].
Shift variations as a function of VCC
(with adjustment)
R′
R′
⋅K B
⋅K
B
dtOUT
R
R
K
=
≈
≈
1 + T2
T2
dVCC
AR
= K ⋅ 0.12µs/V
dL
= 0.34mm/V
dVCC
at KNOMINAL = 0.28
Therefore, a constant VCC must be applied to the
potentiometer.
V.6 - Vertical deflection driver stage
This stage must constantly drive the vertical spot
deflection. Such deflection will horizontallyscan the
screen from top to bottom thus generating the
displayed image. Similar to horizontal deflection,
the vertical deflection is obtained by magnetic field
variations of a coil mounted on the picture tube.
A saw-tooth current at frame frequency will go
through this coil commonly called ”frame yoke”.
Frame period is the time required for the entire
26/46
screen to be scanned vertically.
C.C.I.R. and N.T.S.C. TV standardsrequire respectively 50Hz and 60Hz Frame Scanning Frequencies. Also, a full screen display is obtained by two
successivevertical scannings such that the second
scanning is delayed by a half line period with
respect to the first.
This method increases the number of images per
second (50 half images/s or 50 frames/s in 50Hz
standard). This scanning mode called ”Interlaced
Scanning” eliminates the fliker which would have
been otherwise produced by scanning 25 entire
images per second.
The circuit will generate a saw-tooth voltage which
is linear as a function of time and called ”frame
saw-tooth”. A power amplifier will deliver to the
”frame yoke” a current proportional to this sawtooth voltage. It is thus clear that this saw-tooth
voltage reflects the function of the vertical spot
deflection; which must itself be synchronized with
the video signal. Synchronization signals are obtained from an extraction stage which will extract
the useful signal during line pulse inversion of the
composite sync signal.
Synchronization occurs at the end of scanning, in
other words, when the saw-tooth voltage at Pin 5
is reset. This function is accomplished by the
”frame logic circuitry” of full digital implementation.
This processing method offers various advantages :
- Accurate free-running scanning frequency
eliminates the frequency adjustment required by
previous devices.
- Digital synchronization locked onto half line
frequency thereby yielding perfect interlaced display and excellent stability with noisy video signal.
- Automatic 50/60Hz standard recognition and
switching the corresponding display amplitude.
- Optimized synchronization in VCR mode.
- Generation of variousaccurate time intervals,
such as narrow ”sync windows” thus reducing
considerably the vertical image instability in case
of for instance, mains interference,superimposed
on frame sync pulse.
- Generation of vertical blanking signal for spot
flyback and to protect the picture tube in case
of scanning failure.
TEA2028 - TEA2029 APPLICATION NOTE
Figure 51 : Block Diagram of the Vertical Deflection Stage
H/2
Reference
Block
50/60Hz
Frame
Sync.
Separator
≥1
&
50/60Hz
Output
24
Frame Logic
Power
Amplifier
I 60
t
IY
Composite
Sync.
Bottom of Picture
Frame
Sawtooth
Frame
Sawtooth
Generator
Reset
V→I
3
x1
Free
Reset
Top of Picture
IY
Frame
Yoke
5
R5
2028B-54.EPS
+E
C5
to be present on input signal.
An external capacitor Pin 20 can be added to the
integrated capacitor C to increase the frame sync
time constant.
V.6.1 - Frame sync extraction
The main duty of this stage is to extract the frame
sync pulses contained in composite sync signal.
Figure 52 : Sync. Extractor Block Diagram
V.6.2 - Frame saw-tooth generator
5.6V
Frame
Figure 53
Sync.
2.8V
Sync.
IC + ID
C
V C 2.8V
I C = 2µA
I C + I D = 9µA
C = 35pF
Two current generators are used to charge and
discharge the integrated capacitor ”C”. The discharge generator (IC + ID) is driven by the composite sync signal.
ID ⋅ tSYNC
The ∆VC across capacitor is : −
C
During frame trace, the capacitor is discharged at
each line sync pulse thereby generating a ∆V of
-0.94V with respect to 5.6V and then recovers the
charge by current ”IC”. The comparator output remains low.
The discharge time is 27µs at the first line sync
inversion applied to comparator input. The voltage
”VC ” then falls from 5.6V to 0.2V and triggers the
comparator ”C0” which will deliver a frame sync
pulse when ”VC” crosses the 2.8V level.
The overall arrangement behaves as an integrator
and will therefore suppress any noise susceptible
2028B-55.EPS
Composite
FRAME LOGIC
BLOCK
+
+
60Hz
∆I 60
Frame
Reset
(64µs)
5
3
+E
(200V)
Frame Sawtooth
R5
2.7MΩ
C5
470nF
Output
R3
2.2kΩ
2028B-56.EPS
IC
The frame saw-tooth is generated by an external
RC network on Pin 5.
The time constant ”R5 ⋅ C5” is much higher than
the frame period. Therefore, the generated sawtooth is quite linear.
The network is discharged by an internal transistor,
controlled by the frame logic block.
27/46
TEA2028 - TEA2029 APPLICATION NOTE
Figure 54
E
200V
= 74µA ⇒ I60 = 88µA
=
R5 2.7MΩ
I50 =
therefore ∆I60 = 14µA
V3
4.4V
2028B-57.EPS
t
64µs
20ms (50Hz)
V.6.2.1 - 60Hz STANDARD SWITCHING
The NTSC standard requires a vertical picture
scanning frequencyof 60Hz, i.e. a saw-tooth period
of 16.66ms.
In order to obtain an identical deflection amplitude
whatever the standard (50 or 60Hz), the saw-tooth
amplitude for both periods must be the same.
60Hz standard recognition is performed automatically by the frame logic block, which will issue a
signal to drive a current generator ”∆I60”. This
current will be summed with the external charge
current and will increase the saw-tooth slope, so as
to yield same saw-tooth amplitude to that set in
50Hz standard. This current is centered around
14µA and is a fraction of IREF applied to Pin 14.
Employing the recommended component values
for network connected to Pin 5, this current will
result in identical amplitude in both standards.
∆V 5 =
I60 × T 60
C5
=
Figure 55
SYNC.
L625
RESET
(Counter)
L1
L2
32µs
H/2
FRAME
SAWTOOTH
(Pin 3)
I50 × T50
60
= 1.2 × I50
⇒ I60 = I50 ×
50
C5
L1
L2
LX
tx
2028B-58.EPS
1.26V
( VREF )
V.6.3 - Functions of frame logic block
This section is fully implemented by I2L logic gates.
It is clocked by an accurate ”H/2” clock running at
half line period (32µs). The required periods and
time intervals are obtained by counting the clock
pulses.
For the sake of clarity, timing signals so obtained
are labeled by the line number corresponding to
video signal.
The time corresponding to ”x” scanned lines with
respect to the beginning of frame saw-tooth (RESET) is therefore :
tx = 64µs (x - 1) + 32µs
Figure 56 : Block Diagram
BINARY DIVIDERS
H/2 (32µs)
Reset
Q1
Q10
64µs
Frame Blanking
32.768ms
MISCELLANEOUS
FUNCTIONS
FRI Inhibition
(ϕ1)
SYNC
WINDOW
GENERATOR
VCR
VCR
Video
Recognition
(Mute)
Sync. Window
f 50Hz
2-bit Register
(50Hz)
&
&
&
Sync.
f 60Hz
Extracted
Frame Sync.
3-bit Register
(60Hz)
Sync.
FREE-RUNNING
FREQUENCY
PULSES
28/46
50/60Hz
Identification
&
≥1
Reset
2µs
DISCHARGE
FLIP-FLOP
∆I 60
Control
64µs or
48µs (VCR)
Sawtooth Generator
Capacitor Discharge
2028B-59.EPS
DIGITAL SYNC.
OR
DIRECT SYNC.
TEA2028 - TEA2029 APPLICATION NOTE
V.6.3.1 - 50/60Hz Standard recognition
This function is performed by two shift registers
which are loaded by sync pulses (if present) and if
these pulses fall within the time interval specific to
each standard. These intervals are called ”Register
Windows” and labeled ”WR(50)” and WR(60).
Three pulses are necessary to ascertain the identification prior to switching the saw-tooth amplitude.
The identification signal [ID (60) = 1] is also used to
reduce the synchronization window and, in case of
one or two missing pulses close to 60Hz, to set the
free-running frequency.
Figure 57
V.6.3.2 - Vertical synchronization window Free-running period
In the absence of sync pulse various free-running
periods are specified. Since vertical scanning must
be always active, these free-running periods must
be higher than those of 50 and 60Hz standards so
as to ensure synchronization.
An other window, allowing synchronization only at
the end of scanning, is also necessary. Upon synchronization, this window will allow vertical flyback
only at the bottom of screen. This window should
be narrow for good noise immunity but also wide
enough to yield, upon synchronization, a capture
time unperceptible on screen.
In our case, as long as no standard identification
takes place the window will remain wide, and once
one of the standards has been identified, the window will be considerably reduced.
In VCR mode, this window will bealways wide since
frame frequencies delivered in high-speed search,
slow review and picture pause modes are very
much variable and must be taken into consideration.
In the absence of transmission (Mute = 0), synchronization is disabled (so as to avoid incorrect synchronization due to noise) and the free-running
frequency is around 50Hz. This will eliminate the
occurrence of picture overlay at the end of trace at
a lower free-running frequency.
L 247
L 27 7
L309
L315
WR(50Hz)
1 7. 6 9 6 ms 1 9.7 44ms 2 0. 12 8ms
60H z
Sync
2028B-60.EPS
WR(60Hz)
1 5. 7 73m s
50 H z
16 .6 6ms
Sync
20ms
A. 50Hz STANDARD RECOGNITION
This identification is considered valid if two sucessive sync pulses applied to 50Hz shift register fall
within the 50Hz window ”WR(50)”. At the time of
synchronization capture, the first pulse will reset
the counters. The second pulse, if present, will
then trigger the 50Hz identification 20ms later
[ID(50) = 1].
The identification is not valid if two sucessive 50Hz
pulses are not detected. Identification signal is also
used to reduce the vertical synchronization window
in 50Hz standard thereby offering excellent noise
immunity against noise susceptible to be present
in sync signal and hence good display stability.
B. - 60Hz STANDARD RECOGNITION
This identification is validated after three sucessive
sync pulses at 16.6µs period have been detected.
Figure 58 : Definition of Synchronization Windows and Free-running Periods
L247
Register’s
Window
L277
60Hz
L309 L315
L361
50Hz
WR = 0
No Transmission
(Mute = 0)
Free-running Period
Reset
or VCR Mode
Mute = 1
I D50 = 1
50Hz Standard
Mute = 1
I D60 = 1
60Hz Standard
W R(WIDE)
Reset
W R(50)
Reset
W R(60)
2028B-61.EPS
Mute = 1
I D50 = 0, I D60 = 0
Reset
29/46
TEA2028 - TEA2029 APPLICATION NOTE
output.
It is also present within the normalized super sandcastle signal on Pin 11 (TEA2028 and TEA2029).
MAXIMUM CAPTURE TIME
The worst case capture time occurs when the first
sync pulse just precedes the sync window.
Let’s find the number of periods necessary for the
capture to occur, i.e. tn = 0.
TL − TW
, TL = 23ms , TW = 7.3ms
⇒n=
TL − TSYNC
- 50Hz : the number of periods is 6
⇒ TCAPTURE(MAX) = 120ms
- 60Hz : the number of periods is 3
⇒ TCAPTURE(MAX) = 50ms
Figure 59
TL
Wide
Window
Frame
Sawtooth
T SYNC
0
t2
tW
2028B-62.EPS
t1
Sync
Pulses
tN=0
(capture)
V.6.3.3 - Frame blanking signal
This signal is necessay to blank the display during
each frame flyback. It is triggered at the beginning
of frame saw-tooth flyback. The duration of this
signal is 1.344ms (or 21 lines).
This ”frame blanking” signal is available through
Pin 4 (TEA2028 only) which is an open-collector
V.6.3.4 - Frame blanking safety (TEA2028 only,
for TEA2029 refer to section VII.5)
Its duty is to protect the phosphor coating of picture
tube in case of any problem with vertical deflection
function such as scanning failure.
A signal to monitor correct scanning is provided by
the frame yoke and applied to Pin 2.
In case of any failure, all frame blanking outputs are
disabled and go high thereby blanking the entire
screen.
During trace phase, the voltage across frame yoke
has a parabolical shape due to the coupling capacitor in series with yoke. During frame flyback, the
current through frame yoke must be rapidly inverted. Conventionally, a two-fold higher supply
voltage is applied across the yoke. This will produce an overvoltage called ”flyback”.
The safety monitoring status is detected on the
falling-edge of flyback, i.e. at the beginning of
scanning. A differentiator network is used to transmit only fast voltage variations.
The required pulse is then compared to 1.26Vlevel.
Frame blanking goes high in the absence of negative pulse (zero deflection current) or if the pulse
does not fall within the first 21 lines (exagerated
over-scanning).
Figure 60
First Frame
Second Frame
Frame Blanking
(Pin 4)
1.344ms
(21 lines)*
20µs
* 24 lines for TEA2029C
30/46
L335
12µs
2028B-63.EPS
L22
TEA2028 - TEA2029 APPLICATION NOTE
Figure 61 : Block Diagram
1nF 100kΩ
1/1k Ω
V2
0
-70 µA
70µA
Frame
Yoke
0.5V
1.26V
I2
1.9 V
1kΩ
1/1k Ω
2
1.26V
Input Characteristics
V2
Frame
Blanking
(no safety)
Frame Blanking
Output
(with safety)
&
R
Frame
Reset
(2µs)
S
1.26V
(1.26V)
≥1
Q
Frame
Yoke
Current
4
2028B-64.EPS
Flyback
S.S.C.
(Pin 11)
V.7 - SWITCHING POWER SUPPLY DRIVER STAGE
Switching takes place on the primary side (mains
side) of a transformer by using TEA2164 SMPS
Controller manufactured by SGS-THOMSON.
Required voltage values are obtained by rectifying
different voltage outputs delivered through secondary windings. The horizontal deflection stage is
powered by one of these outputs delivering around
hundred volts.
This voltage source must be regulated since any
voltage fluctuation will yield variations of the horizontal display amplitude.
The TE2028 monitors this voltage and transmits
the regulation signal to the primary controller circuitry via a small pulse transformer. The characteristics of this regulation signal are directly related
to the conduction period of switching transistor.
V.7.1 - Power supply block diagram
Figure 62
Line Deflection
Stage
Line
Sawtooth
135V
13
P
9
12V
TEA2028B
A
1.26V
14
VREF
M1
TEA2164
7
x1
&
M2
28µs
Window
SAFETY
FLIP-FLOP
START-UP
CIRCUITRY
1.26V
28
15
2028B-65.EPS
Mains
Input
31/46
TEA2028 - TEA2029 APPLICATION NOTE
Figure 64 : Conduction Periode (Pin 7) versus
Input Voltage (Pin 9)
V.7.2 - General operating principles
A fraction of the 135V output voltage to be regulated is compared to the 1.26V reference voltage.
Resulting error signal is amplified and then applied
to phase modulator ”M1”, which will deliver a
square waveform at line frequency whose duty
cycle depends on the value of input voltage ”V9”.
A second phase modulator ”M2” will determine the
conduction period as a function of voltage on
Pin 15. This function is mandatory for system startup.
A 28µs window is used to limit the conduction
period of the primary-connected transistor.
Supply output (Pin 7) and line output (Pin 10) will
be disabled if any information indicating abnormal
operation is applied to safety input (Pin 28). Consequently, all power stages are disabled and the
TV set is thus protected.
t ON (Pin 7)
28µs
-1.9µs/mV
1.26V
9.5mV
V IN
(Pin 9)
5.2mV
2028B-67.EPS
10µs
SMPS WAVEFORMS
For discontinous mode ”flyback” configuration
The primary-connected transistor is turned-off during the line flyback.
All interference signals due to switching and susceptible to affect the video signal will not therefore
be visible on screen.
V.7.3 - Electrical characteristics of the internal
regulation loop
Figure 65
Figure 63
B
40µA
2µs
-1
I1
V→ I
I
I2
V→ I
9
VIN
Low-pass
Filter
V13
The phase modulator implemented by a simple
transistor ”T1” will compare in current mode, the
image of amplified input (i1) with saw-tooth current
(i2) at line frequency. With ”i2” rising, as soon as the
sum of ”i1 + i2 - IDC” goes positive, the transistor
enters into saturation thus determining the output
conduction period.
A low-pass filter implemented by combination of a
100pF capacitor and the input impedance of transistor ”T1”, attenuat es all frequency variations
higher than the line frequency.
di1
- Input Amplification : A =
= 3.3µA/mV
dVIN
- Modulator conversion gain :
dtOUT
= −0.558µs/µA
B=
di1
- Overall gain of the internal loop :
dtOUT
1
= −1.9µs/mV ×
(f0 = 15kHz)
f
dVIN
1+j
f0
32/46
t ON
T1
28µs (max.)
V7
100pF
∆V
VREF
(1.26V)
LF
7
PRIMARY PULSES
PRIMARY CURRENT
SECONDARY
RECTIFIER DIODE
CURRENT
SECONDARY 135V
WINDING
0
VOLTAGE
Regulation Characteristics
The following characteristics have been measured
on a large screen and yield excellent results :
- 135V voltage regulation as a function of mains
voltage : better than 0.5% for mains voltage variations of 170VRMS to 270VRMS (P = 60W at 135V)
- 135 V voltage regulation as a function of load :
better than 0.5% for a delivered power of 35W to
120W.
This type of power supply offers the following advantages :
- Overall efficiency enhancement: better than 80%
- Reduction of interferences by synchronizationon
horizontal frequency
2028B-68.EPS
I DC
V13
t OUT
2028B-66.EPS
A
TEA2028 - TEA2029 APPLICATION NOTE
- Full protection of the primary-connected transistor in case of short-circuit or open-load on secondary terminals
- Can provide 1W to 7W, for TV standby mode
operation (refer to TEA2164 application note).
V.7.4 - Power supply soft-start
When the TV set is initially turned on, control pulses
are not yet available and consequently the controller block on primary side will impose a low-power
transfer to the secondary winding. This power is
produced by an intermittent switching mode called
”Burst Mode”.
As soon as the VCC supply to TEA2028B exceeds
6V level, line and SMPS outputs are enabled.Since
the filtering capactitors on secondary side cannot
charge up instantaneously, the voltage to be regulated would not yet be at its nominal value. Without
conduction period limitation upon start-up, the device will set a maximum cycle of 28µs which will
result in a high current flow through the primary
winding and thus through the switching transistor
which will in turn activate the protection function
implemented on primary side.
Consequently, the primary controller block will be
inhibited and the set will not turn-on.
A start-up system has been implemented within
TEA2028B to overcome this problem.
This soft start system, will upon initial start-up, use
the image of the falling voltage on Pin 15 to increase progressively the conduction cycle. The
phase modulator ”M2” compares this voltage with
line saw-tooth voltage and delivers the corresponding limitation cycle.
During supply voltage rising cycle [VCC (Pin 8)
< 6V], the capacitor Pin 15 will charge up rapidly
while the voltage across it follows VCC.
At VCC ≥ 6V, the capacitor is discharged via an
internal current generator and the voltage across it
decays linearly.
At V15 ≤ 3.5V (line saw-tooth peak-to-peak voltage), phase comparator ”M2” delivers a low conduction period which will gradually increase.
The conduction period (Pin 7) will rise until the
secondary voltage reaches the value set by potentiometer ”P”. When this occurs, the loop is activated.
The Pin 15 discharge current value is 100µA for a
duration of 2µs line frequency.
2
= 3.1µA
Therefore ID(AV) = 100 ×
64
Conduction period limitation voltage (Pin 15)
TON(LIM) = 56µs - 16 x V15 (in µs)
Figure 66
12V
PIN 8 SUPPLY
VOLTAGE (V)
6
5.5V
t
PIN 15
VOLTAGE (V)
VCC
6
3.5
5.5V
V CC
V
CC
t
Soft-start area
LINE OUTPUT
VOLTAGE (PIN 10)*
Regulated Mode
Active area
t
2028B-69.EPS
SMPS CONTROL
OUTPUT VOLTAGE
(PIN 7)
t
* Lin e output (Pin 10) an d Thyristo rco ntrol output (Pin 4) for TEA2029C
33/46
TEA2028 - TEA2029 APPLICATION NOTE
V.7.6 - TV Power supply in standby mode
V.7.6.1 - Regulation by primary controller circuit
This mode of regulation called ”Burst Mode” is
performed only by the primary controller circuit and
is activated in the case of missing control pulses or
in the absence of power supply to TEA2028B.
In this mode, power available through secondary
winding is limited. Refer to TEA2164 Application
Note for further details.
Higher powers can be obtained by using the regulation feature offered by TEA2028B. In this case,
the horizontal output (Pin 10) must be disabled.
Figure 67
t ON
1.75
2028B-70.EPS
28µs
3.5
Pin 15 VOLTAGE (V)
V.7.5 - Protection features
As soon as a safety signal (V ≤ 1.26V) is applied to
Pin 28, line and supply outputs (Pins 10 and 7) are
both disabled. Capacitor ”C15” begins charging up
until the voltage across it reaches 4V (K ⋅ VCC).
Outputs are again enabled and conduction period
gradually increases as it occurs upon initial startup.
The device will be definitively inhibited if the cycle
of events is repeated 3 times.
For the device to restart, the internal 3-bit register
should be reset which requiresthe VCC to fall below
4V (see Figure 68).
Pin 15 charging current : IC(AV) = - ID(AV) = - 3.1µA
V.7.6.2 - Regulation by TEA2028 (see Figure 69)
In this case, all that is required is to disable the line
scanning function thus reducing the overall power
by 90%.
The device power supply regulation loop remains
active, for minimum conduction period to be 1.5ms
the power delivered through secondary must be
higher than 3W.
Line Output Inhibition
Two alternatives are possible :
- Grounding flip-flop Pin 1
- Apply a voltage higher than 3V to Pin 12.
Figure 68
Inverted
for
TEA2029C
PIN 8
VOLTAGE (V) 1.26
0
2
4
3.5
PIN 15
VOLTAGE (V)
IC
ID
t
3
6V
t
Soft-start area
PIN 7
VOLTAGE
t
Active area
Full Inhibition
2028B-71.EPS
PIN 10 *
VOLTAGE
t
* Line output (Pin 10) and thyristor cont rol outpu t (Pin 4) for TEA2029C
Figure 69
+
VCC
S
Q
≥1
R
10
Standby
Mode
LF
1.26V
R2
1
3.3nF
Line Inhibition
(Standby Mode)
R1
≥1
V12
3V
34/46
29µs
10
2028B-72.EPS
12
VL
TEA2028 - TEA2029 APPLICATION NOTE
V.8 - Miscellaneous functions
V.8.1 - Super sandcastle signal generator
This signal used in video stage, is available on
Pin 11.
It has 3 levels at specified time intervals :
- 2.5V level
Used for vertical blanking at each frame flyback.
Its duration is 21 lines and is generated by the
frame logic.
This level will be maintained if vertical scanning
failure is detected on Pin 2.
- 4.5V level
Used for horizontal blanking, its duration is determined by comparing the line flyback signal on
Pin 12 to an internal voltage of 0.25V.
- 10V level
This signal is used by color decoding stage. Its
duration of 4µs is determined by line logic circuitry. With respect to the video signal on Pin 27,
this level is positioned such that it is used to
sample the burst frequency transmitted just after
the sync pulse.
V.8.2 - Video and 50/60Hz standard recognition
output
A 3-level signal is available at Pin 24 for video
identification(Mute) and for 50 and 60Hz standards
recognition.
Figure 70
Burst
VIDEO SIGNAL
(Pin 27)
4.7µs
0.3µs
10V
4µs
4.5V
2.5V
2028B-73.EPS
Line Blanking (12µs)
SUPER
SAND CASTLE
(Pin 11)
Frame Blanking (21 lines)
Figure 71
+
VCC
+
VCC
VCC
R
24
60Hz
1
0
V24
R
Mute
VCC /2
Without
Video
60Hz
Standard
50Hz
Standard
Transmit
Identification
2028B-74.EPS
V24
0
50Hz
35/46
5.6k Ω
2028B-75.EPS
INPUT
VIDEO
IDENTIFICATION
50Hz/60Hz
MUTE OUTPUT
V CC
V CC
10µF
10pF
1.5nF
10nF
1kΩ
1.8k Ω
4.7nF
SWITCH
VCR
SUBSTRAT
GROUND
220 Ω
503kHz
220 Ω
25
24
23
22
21
20
19
18
15
14
INPUT
SAFETY
28
1.26V
1
2
13
V REF
3.3nF
TEA2028B
10k Ω
27
26
V CC
16
17
150pF
100nF
470Ω
22nF
220nF
470k Ω
47k Ω
2.2k Ω
10µF
3.32k Ω
3.3nF
3
12
LR
+12V
SAFETY INPUT
4
5
6
7
8
9
10
11
CAST.
SAND
SUPER
10 V PP
390 Ω
47nF
2.2nF
1k Ω
V CC
+200V
Pin 14
TO TEA2161
1kΩ
ADJUST
VOLTAGE
OUTPUT
SMPS
1nF 100k Ω
150k Ω
13k Ω
(TEA2028B)
V CC
1kΩ
100µF
150k Ω
LINE YOKE
2mH - 2.5 Ω
TRANSFORMER
EHT
1
7
15k Ω
6
100Ω
4
TDA8172
2
1N4001
5
470kΩ
3
LF
100µF
100nF
TRANSFORMER
+140V FROM SMPS
680k Ω
FRAME AMPLITUDEADJUST
FRAME SAWTOOTH
OUTPUT
BLANKING
FRAME
10k Ω
2.7M Ω
470nF
330 Ω
1kΩ
V CC
33k Ω
36/46
1nF
V CC
2.2Ω
100nF
1000µF
1Ω
VERT.
SHIFT
FRAME YOKE
32µH
15Ω
0.7App
+24V
+200V
TEA2028 - TEA2029 APPLICATION NOTE
VI - TEA2028 APPLICATION DIAGRAM
Figure 72
220Ω
TEA2028 - TEA2029 APPLICATION NOTE
VII - TEA2029 : DIFFERENCES WITH TEA2028
VII.1 - General
The TEA2029 has quite the same functions compared to TEA2028.
The main difference is that the TEA2029 incorporates a frame phase modulator intended to work with a
switched mode vertical stage using a thyristor.
The TEA2029 can also be used with a linear vertical power amplifier such as the TDA8170.
VII.2 - Pin by Pin Differences
2
4
10
11
12
20
28
TEA2029C
Dfferential inputs of the frame error amplifier (including
frame blanking safety in case of vertical stage failure).
TEA2028B
Capacitor for horizontal output duration adjustment
(29µs typ. with c1 = 3.3nF)
Vertical blanking safety input
Frame output for thyristor control
Vertical blanking output (21 lines duration)
Horizontal output (26µs typ. duration)
Horizontal output (duration is adjustable)
Supersandcastle output (with a frame blanking duration
Supersandcastle output (with a frame blanking
of 24 lines)
duration of 21 lines)
Negative horizontal flyback input (115 VPP through a 47
positive horizontal flyback input (10Vpp through a
kΩ resistor)
47kΩ resistor)
Positive AGC key pulse output (low level when no video) Capacitor for frame sync. time constant adjustment
Safety input (inhibition of SMPS, Horizontal outputs
Safety input (inhibition of SMPS, Horizontal and Frame
when V28 < 1.26V)
outputs when V28 > 1.26V)
VII.3 - TEA2029C Pin Connections
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Description
Frame error amplifier non-inverting input
Frame error amplifier inverting input
Frame saw-tooth output
Frame output (for thyristor control)
Frame ramp generator
Power Ground
SMPS control output
VCC Supply voltage
SMPS regulation input
Horizontal output
Supersandcastle output
Horizontal flyback input
Horizontal saw-tooth generator
Current reference
SMPS soft-start and safety time constant
φ2 phase comparator capacitor
(and horizontal phase adjustment)
VCO phase shift network
VCO output
VCO input
AGC key pulse output
Substrate Ground
φ1 phase comparator capacitor
VCR switching input
Video and 50/60Hz identification output (Mute)
Video identification capacitor
Horizontal sync detection capacitor
(50% of peak to peak sync level)
Video input
Safety input
Package : DIP28
DIP28.EPS
Pin
1
VII.4 - Frame Phase Modulator
The Tranconductance Amplifier ”A1” converts the
differential input voltage into two output currents
”IS1” and ”IS3”.
IS1
- A1 transconductance =
= 10µA/mV
VIN
IS2
- B transconductance =
= 40µA/V
V2
∆tOUT
- Transfer characteristic =
= 6.4µs/V
∆VIN
The filter time constant is maximum near the operating point when IS1 ≅ IS2
In this case :
- The base current of T1 = ”IS2 - IS1”
- The filter band-pass = 15kHz
The maximum conduction period of ”40µs” is determined by the horizontal logic circuitry.
The frame frame flyback is detected by transistor ”T3”.
There is no feed-back during frame flyback and
”IS3” is maximum (higher than I4) which will drive
the ”T3” into conduction.
37/46
TEA2028 - TEA2029 APPLICATION NOTE
Figure 73
VIN
Transconductance
Amplifier
I S1
2
V→ I
B
I S2
Horizontal
Sawtooth
V→I
3.5V
1
I S3
64µs
T3
T1
C
150pF
Safety Frame
Logic to Super
Sand Castle I.F.
I4
VCC
40µs
Phase Limitation
(Horizontal Logic)
&
Q
R
Q
4
4.7kΩ
≥1
Safety & On/Off
Switching Voltage
Frame
Output
∆ t OUT
2028B-76.EPS
Horizontal Flyback
S
Figure 74
HORIZONTAL
FLYBACK
V4
FRAME
OUTPUT
t
40µs max.
V13
0
t
6µs
VII.5 - Frame Blanking Safety
- During trace : IS3 < I4 ⇒ T3 is blocked.
- During flyback : IS3 > I4 ⇒ T3 conducts.
In the absence of flyback detection or if the flyback
interval is longer than the blanking time, the sandcastle low level remains constant at 2.5V so as to
38/46
protect the picture tube in the absence of frame
scanning.
- ”IF” signal is delivered by Frame Error Amplifier
(see Frame phase modulator figure)
- IF is high during the Frame Flyback interval
2028B-77.EPS
3.5V
HORIZONTAL
SAWTOOTH
TEA2028 - TEA2029 APPLICATION NOTE
Figure 75 : Frame Blanking Safety Block Diagram
BLK’
S
IF
Q
&
≥1
BLK’
R
R
Q
≥1
&
Q
Blanking Output
to Super Sand Castle
S
2028B-78.EPS
From
Frame
Counters
IF
Reset
Figure 76
NORMAL OPERATION
TOO LONG FLYBACK PULSE (FR)
RESET
BLANK’
IF
24 lines
2028B-79.EPS
S1
BLANKING OUTPUT
VII.6 - On-chip Line Flip-flop
Figure 77
16
16µs Window
for ∆ϕmax
φ2
LF
(Line Flyback)
&
10
S
Q
≥1
Output
x1
R
13
Safety
(Pin 28)
VIN
2028B-80.EPS
C13
I
Figure 78
V16
V10
∆φmax = 16µs
26µs
2028B-81.EPS
VIN
T10 = 35 ⋅ TVCO - K ⋅ R14 ⋅ C13
= 70 ⋅ 10-6 - 4 ⋅ R14 ⋅ C13
Where TVCO is the VCO period of oscillation on
pin 18.
- If in synchronized mode :
TVCO = 2µs,
R14 = 3.32kΩ
C13 = 3.3nF
ThereforeT10 = 26µs (nominal value)
39/46
TEA2028 - TEA2029 APPLICATION NOTE
VII.7 - AGC Key Pulse
Figure 79
Burst
VIDEO SIGNAL
(Pin 27)
4.7µs
12V
0V
1.3µs
2.3µs
Without
Video Signal
As illustrated below, this signal is used in some TV
sets to perform sampling window for Automatic
Gain Control of picture demodulation network.
This system is called ”clamped” AGC, and locks the
demodulated line sync amplitude and hence sets
the video signal amplitude.
This signal generated by line logic circuitry is correctly positioned by the first phase locked loop ”φ1”
and includes the line sync pulse of the video signal.
This is an open-collector output.
VIII - APPLICATION INFORMATION ON FRAME
SCANNING IN SWITCHED MODE
(TEA2029 ONLY)
VIII.1 - Fundamentals (see Figure 80)
The secondary winding of EHT transformer provides the energy required by frame yoke.
The frame current modulation is achieved by
modulating the horizontal saw-tooth current and
subsequent integration by a ”L.C” network to reject
the horizontal frequency component.
VIII.2 - General Description
The basic circuit is the phase comparator ”C1”
which compares the horizontal saw-tooth and the
output voltage of Error Amplifier ”A”.
The comparator output will go ”high” when the
horizontal saw-tooth voltage is higher than the ”A”
40/46
output voltage. Thus, the Pin 4 output signal is
switched in synchronization with the horizontal frequency and the duty cycle is modulated at frame
frequency.
A driver stage delivers the current required by the
external power switch.
The external thyristor provides for energy transfer
between transformer and frame yoke.
The thyristor will conduct during the last portion of
horizontal trace phase and for half of the horizontal
retrace.
The inverse parallel-connected diode ”D” conducts
during the second portion of horizontal retrace and
at the beginning of horizontal trace phase.
Main advantages of this system are :
- Power thyristor soft ”turn-on”
Once the thyristor has been triggered, the current
gradually rises from 0 to IP, where IP will reach
the maximum value at the end of horizontal trace.
The slope current is determined by, the current
available through the secondary winding, the
yoke impedance and the ”L.C.” filter characteristics.
- Power thyristor soft ”turn-off”
The secondary output current begins decreasing
and falls to 0 at the middle of retrace. The thyristor
is thus automatically ”turned-off”.
- Excellent efficiency of power stage due to very
low ”turn-on” and ”turn-off” switching losses.
2028B-82.EPS
AGC SIGNAL
(Pin 20)
TEA2028 - TEA2029 APPLICATION NOTE
Figure 80 : Block Diagram
L
500µH
EHT
Transformer
C
0.47µF
VLF
VC
I TD
TEA2029C
Horizontal
Sawtooth
ESM
740
4
I
D
Y
120mH
60Ω
VCONTROL
Frame
Yoke
90°
Frame
Amplitude
Adjust
Feedback
1
RM
4.7Ω
VREF
Σ
Frame Reference
Sawtooth (Pin 3)
+24V
VB
C1
1000µF
2028B-83.EPS
2
VIII.3 - Typical Frame Modulator and Frame Output Waveforms
Figure 81
FRAME REFERENCE
SAWTOOTH
HORIZONTAL
SAWTOOTH
THYRISTOR
GATING SIGNAL
HORIZONTAL
FLYBACK
I THYRISTOR
2028B-84.EPS
I TD
I DIODE
Beginning of Frame Trace
End of Frame Trace
41/46
TEA2028 - TEA2029 APPLICATION NOTE
VIII.4 - Frame Power Stage Waveforms
Figure 84
2028B-86.TIF
Figure 83
2028B-85.TIF
Figure 82
42/46
2028B-90.TIF
Figure 87
2028B-89.TIF
Figure 86
2028B-88.TIF
2028B-87.TIF
Figure 85 : Different Horizontal Conducting
Times during Frame
TEA2028 - TEA2029 APPLICATION NOTE
The overall configuration is built around two symmetrical networks :
- ”R1, R2, R3” network : determines the dynamic
saw-tooth voltage
- ”R’1, R’2, R’3” network : sets the bias voltage and
the d.c. shift control.
IY
R2
=
⋅ α ⋅ RM
A.C. gain : G =
R1 VIN
where :
- IY : Peak-to-peak Yoke Current
- VIN : Peak-to-peak saw-tooth voltage (Pin 3)
- α ∈ [0,1] : amplitude adjustment
The bias voltage ”VB” is supplied by the secondary
winding of EHT transformer. The parabolic effect is
due to the integration of frame saw-tooth by the
filtering capacitor ”C1”.
IY ⋅ T
= 0.95V
DVB =
8 ⋅ C1
Where :
- IY : Peak-to-peak yoke current = 380mApp
- T : 20ms
- C1 = 1000µF
VIII.5 - Frame Flyback
During flyback, due to the loop time constant, the
frame yoke current cannot be locked onto the
reference saw-tooth. Thus the output of amplifier
”A” will remain high and the thyristor is blocked.
The scanning current will begin flowing through
diode ”D”. As a consequence, the capacitor ”C”
starts charging up to the flyback voltage. The thyristor is triggered as soon as the yoke current reaches
the maximum positive value.
EHT transformer winding (see Figure 88)
(for 90o tube : Yoke ⇒ L = 120mH, rY = 60Ω)
VIII.6.1.1 - Choice of ”R” value
The saw-tooth generator output is an emitter follower stage. Pin 3 output current must therefore be
always negative.
VIN(Min.)
R << R1
VBIAS − VIN(Min.)
Where :
- VBIAS : Bias voltage for Pins 1 and 2
- VIN(MIN) : Saw-tooth voltage low level
Example :
- R1 = 22kΩ
R1
⇒R≈
- VBIAS = 5V
10
- VIN(Min.) = 1.26V
Figure 88
L
C
Load
Yoke
I DIODE
I THYRISTOR
- VLF = 210VPP
- IYOKE = 380mAPP
- L = 500µH
VB
- C = 0.47µF
- VLF ≈ 9.2 IY(PP) ⋅ rY
- Flyback duration = 1ms
VIII.6 - Feed-back Circuit
VIII.6.1 - Frame power in quasi-bridge configuration (see Figure 89)
This stage measures the frame scanning current in
differential mode and compares it to the reference
saw-tooth on Pin 3.
2028B-91.EPS
VLF
VIII.6.1.2 - Influence of R3 value
R3 sets the bias voltage for Pins 1 and 2. This
voltage should be lower than 5.5V so as to enable
the frame to function upon initial start-up at
VCC = 6V.
If the bias voltage is higher than this 5.5V level, the
d.c. open-loop gain will fall thereby rendering the
system more sensitive to d.c. drift.
Satisfactory results are obtained at VBIAS values
falling within 4V to 5V range.
VBIAS
R3 = R2
VB [VIN(MEAN) ⋅ G] − VBIAS [1 − G]
Where : VIN(MEAN) : saw-tooth mean value (Pin 3)
Capacitor ”C” connected between Pins 1 and 2
determines the system stability. Its value must be
appropriately calculated as a function of ”R1, R2
and R3” values so as to reject the line frequency
component.
43/46
TEA2028 - TEA2029 APPLICATION NOTE
Figure 89
Frame
Yoke
Frame Reference
Sawtooth
R1
R2
3
V-
R
IY
Frame
Amplitude
Adjust
R3
2
VOUT
VIN
C
P1
R M RM . I Y
α, RM . IY
A
V+
1
R’1
R’2
P2
V+
VB
2028B-92.EPS
R’3
VP
VIII.6.1.3 - ”S” Correction circuit in quasi-bridge configuration
Figure 90
of ”D1” and ”D2” diodes.
The signal pre-corrected by ”D1”, ”D2” diodes and
the feed-back signal through ”R5”, are summed at
”A”. The ”S” correction level is determined by the
ratio between ”R4” and ”R5” resistors.
TEA2029C
D1
R1
R
YOKE
2
R3
R2
R5
220Ω
R4
D2
2.2kΩ
100Ω
100Ω
VIII.6.2 - Frame scanning in switched mode
using coupling capacitor (see Figure 91)
RM
VB
2028B-93.EPS
3
The parabolic voltage at (a) is integrated by ”R2,
C2” network and used for ”S” correction.
The ”S” waveform voltage at (b) is added to the
saw-tooth voltage at(c). The ”S” levelis determined
by ”C2, R2, R3” network.
The ”S” correction waveform is obtained using the
non-linear ”VDIODE” versus ”I DIODE” characteristics
Figure 91
TEA2029C
FRAME
SWATOOTH
1
2
3
27kΩ
Linearity
Adjustment
150kΩ
+V B
R3
YOKE
220kΩ
(b)
R2
(a)
820kΩ
680kΩ
C2
0.1µF
CP
R4
To Safety
Input
(c)
56kΩ
100Ω
Vertical
Amplitude
Adjust
44/46
10Ω
R5
2028B-94.EPS
10kΩ
TEA2028 - TEA2029 APPLICATION NOTE
VIII.6.3 - Frame safety
coupling capacitor ”C P” will reach an excessively
high value.
In case of failure in the loop, the thyristor may
remain turned-off while the inverse parallel-connected diode conducts. This will result in a hazardeous situation where the voltage across the
To avoid such situation, the voltage at point (a)
should be applied to the ”Safety” input Pin 28 after
it has gone through the matching network ”R4, R5”.
VIII.7 - Frame Scanning in Class B with Flyback Generator
VIII.7.1 - Application diagram
Figure 92
200V
TEA2029C
(Pin 14)
+24V
6
3
1
4
4
680kΩ
470kΩ
15kΩ
Vertical Amplitude
Adjust
Vertical
Phase
Shift
2028B-95.EPS
2.2kΩ
3.3kΩ
150kΩ
1Ω
Frame Sawtooth
+12V
Frame
Yoke
32mH
15Ω
0.7App
1000µF
10kΩ
15nF 10kΩ
100Ω
3
100nF
2
5
220Ω
TDA8172
100nF 2.2kΩ
1nF
13kΩ
TEA2029C
1
N.C.
100µF
2
7
470nF
5
33kΩ
2.7MΩ
1N4001
45/46
13
12
10
5
4
470kΩ
300kΩ
1nF
3
Ω
2
2028B-96.EPS
2µH
10Ω
220µF
100kΩ
(2W)
1N4444
14
16
100Ω
6
15
2 x 47µF
(385V)
6.8Ω
1
330
Ω
390
11
TEA216 4
4.7µF
9
7
8
12kΩ
PrimaryGround (connected to mains)
Secondaryground (isolated from mains)
2.2µF
1.2nF
110kΩ
2.2Ω
2.2Ω
0.27Ω
100Ω
47µF
3 x 1N404
BA157
BA157
220Ω
BU508A
2
1
7
9
6
470Ω
10µF
BA159
2.2nF
4.7µF
V CC
470µ F
1000µF
100µ F
VCC
1N4148
24
20
7
22
19
18
17
15
16
100nF
VIDEO
INPUT
27
23
VCR
Switch
13V
2N1711
MUTE OUT
&
50/60Hz
IDENTIFICATION
8.2k Ω
AGC
PULSE
15kΩ
1.5nF
15nF
330Ω
5.6kΩ
1.8kΩ
220Ω
3.9kΩ
5.6kΩ
503
kHz
150pF
+25V
470kΩ
10kΩ
680Ω
27Ω
33kΩ
+135V / 0.6A
HorizontalPhase
Adjust
BY218
BY218
BY218
220Ω
VCC
22
21
19
20
13
22nF
100nF
3
OREGA
G.4173.04
3.3nF
220nF
4 x 1N4007
14
26
25
1.5kΩ
8
11
9
28
21
5
3
1
2
6
4
10
100kΩ
220pF
10kΩ
1k Ω
220pF
150kΩ
SUPER
LINE SANDCASTLE
OUTPUT
FLYBACK
12
TEA2029C
13
22nF
220
µF
V CC
SMPS
Output Voltage
Adjust
4.7nF
1kΩ
1kΩ
220VAC
MAINS INPUT
3.32kΩ (1%)
100nF
820 Ω
220Ω
1kΩ
100nF
LINE
YOKE
1nF
1kΩ
220 Ω
FramePhase
Adjust
6.8kΩ
33 Ω
ESM
740
82kΩ
220Ω
BA157
EHT
TRANSFORMER
3.3kΩ
3.3kΩ
47nF
390Ω
E/W
CORRECTION
2.2kΩ
220kΩ
470nF
2.7MΩ
820 Ω
1kΩ
46/46
6.8kΩ
FUSE 1.6A
200V
+24V
4.7 Ω
Frame
Amplitude
Adjust
FRAME
YOKE
120mH
60Ω
0.47µF
500µH
LINE FLYBACK
+24V
+200V
TEA2028 - TEA2029 APPLICATION NOTE
IX - TEA2029 APPLICATION DIAGRAM
Complete application with TEA2164
Figure 93
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility
for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result
from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics.
Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all
information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life
support devices or systems without express written approval of SGS-THOMSON Microelectronics.
 1994 SGS-THOMSON Microelectronics - All Rights Reserved
Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips
I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to
the I2C Standard Specifications as defined by Philips.
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