STV2000 I2C SINGLE FREQUENCY DEFLECTION PROCESSOR AND 70 MHz RGB PREAMPLIFIER PRELIMINARY DATA The STV2000 is an I2C-controlled monolithic integrated circuit assembled in a TQFP44 plastic package. It combines both a deflection block (horizontal and vertical, single frequency with very powerful geometry correction) and a 70MHz RGB pre-amplifier. Vertical deflection ■ Vertical ramp generator. ■ Wide range AGC loop. ■ TTL compatible positive going sync, no extra pulses. 2 ■ I C controls: vertical position and S-correction. ■ DC controls: height breathing compensation. I2C Main features 2 ■ I C interface (slave) 100kHz max. 2 ■ All I C controlled DAC are 7bit, except for RGB gain and cut-off. ■ Power- on- reset at 5 V (VDD). ■ 0.5 to 4 V static DAC output. Supply voltage & power ■ 5 V/10.5 V dual supply. ■ Max power consumption: 1.2W ORDER CODE : Vin Vref VAGCAP VGND VCAP Vout VBRTHin VRB VAVcc Out1 Cut-off 1 FILTER PLL2C HGND Hfly Href Hout Ro Co PLL1F PIN CONNECTIONS Hin FC1 Video preamplifier ■ 3-channel 70MHz bandwidth RGB preamplifier. ■ 5ns typical rise and fall time at 4VPP. 2 ■ I C controls: RGB contrast, cut-off, brightness, contrast up-date during vertical retrace time. ■ ABL will reduce gain (contrast). ■ 0.514V typical video input signal for normal display. TQFP44 44 43 42 41 40 39 38 37 36 35 34 33 1 32 2 31 3 30 4 29 5 28 6 27 7 8 26 9 25 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22 LGDN SAVcc SCL SDA V DD (5V) EWout EWFBin HBRTHin N.C. VBDC In3 PGDN Out3 Cut-off3 PVcc In1 ABLin In2 DAC Horizontal deflection ■ Single frequency, self adaptive oscillator. ■ TTL compatible positive going sync. 2 ■ I C controlled: H-position, Pin Cushion, Keystone, Parallelogram, Side Pin Balance,Hamplitude. ■ DC East/West feedback. ■ DC controls: H-width breathing compensation. ■ X-Ray protection DESCRIPTION AGND Out2 Cut-off2 FEATURES Version 3.0 April 2000 This is preliminary information on a new product now in development. Details are subject toDetails changeare without notice. in development or undergoing evaluation. subject to change without notice. 1/38 1 TABLE OF CONTENTS PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 THERMAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 SYNC INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 I2C READ/WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 HORIZONTAL SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 VERTICAL SECTION) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VIDEO PRE-AMP SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 LOGIC SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 I2C BUS ADDRESS TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 TYPICAL OUTPUT WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 OPERATING DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SCANNING PART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 PRE-AMPLIFIER PART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 STAND-BY MODE AND PROTECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 INTERNAL SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2 2/38 2 STV2000 PIN DESCRIPTION Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Name Vin Vref VAGCCAP VGND VCAP Vout VBRTHin VRB VAVcc OUT1 Cut-off1 AGND OUT2 Cutoff2 PGND OUT3 Cutoff3 PVcc IN1 ABLin IN2 DAC IN3 VBDC N.C. HBRTHin EWFBin EWout VDD SDA SCL SAVcc LGND Hout Href Hfly HGND PLL2C Filter PLL1F Co Ro FC1 Hin Function Vertical Sync Input Vertical Section Reference Voltage Vertical AGC Loop Capacitor Vertical Section Ground Vertical Sawtooth Generator Capacitor Vertical Output Vertical Breathing DC Input Vertical Ramp Filter Video Section Analog Supply (10.5V typ) Video Output 1 Cut-off1 DAC voltage output pin Video Analog Ground Video Output 2 Cut-off2 DAC voltage output pin Video Section Power Ground Video Output 3 Cut-off3 DAC voltage output pin Video Section Power Supply (10.5V typ) Video Input 1 Video Automatic Beam Current Compensation Input Video Input 2 7bits DAC Voltage Output Video Input 3 Vertical Blanking Output with DC level adjusted by DAC Not to be connected Horizontal Breathing Compensation DC Input EW Correction Feedback Input EW Buffer Output Bus, Scanning Logic and Video Logic Supply (5V typ) I2C Data Input I2C Clock Input Scanning Section Analog Supply (10.5Vtyp) Bus and Scanning Power Ground Horizontal Driver Output, open collector Horizontal Section Reference Voltage Horizontal Flyback Input, Positive Horizontal Section Ground PLL2 Loop Filter Horizontal Filter Capacitor (HPOS) PLL1 Loop Filter Horizontal Oscillator Capacitor Horizontal Oscillator Resistor PLL1 filter capacitor Horizontal Sync Input 3/38 3 39 43 42 Co HFly 41 PLL2C Hout 38 34 36 Phase Freq Comp Vref 2 Hin 44 Vin 1 Vpos HGND 37 VGND 4 VOSC RAMP Generator VCO SPB Vamp Scorr X2 Geometry Tracking VCAP 5 VAGCCAP 3 VBRTHin 7 KeyBal EW OUTPUT EWPCC KEYST H Breathing + ABL HFly Hsync Vsync I2C BUS DECODER SDA 30 SCL 31 Hsync Clamp Blanking Brightness Drive BPCP 26 HBRTHin 20 ABLin 24 VBDC LATCHES & DACs Contrast 28 EWout 27 EWFBin X Vout 6 8 IN1 19 Safety X2 VRB VDD 29 LGND 33 HOUT Buffer Phase Shifter Phase Comp DAC 22 DAC 9 VAVCC 12 AGND Output Stage 10 OUT 1 11 Cut-off 1 18 PV CC IN2 21 13 OUT 2 14 Cut-off 2 15 PGND 16 OUT 3 IN3 23 17 Cut-off 3 STV2000 STV2000 40 FC1 Ro Href Href 35 Vref Filter BLOCK DIAGRAM 4/38 3 SAVCC 32 PLL1F STV2000 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit SAVcc Scanning Section Analog Supply Voltage 13.5 V VAVcc Video Section Analog Supply Voltage 13.5 V PVcc Supply Voltage for Video Pre-Amp Section 13.5 V Vdd Logic Section Supply Voltage 5.5 V ESD susceptibility HBM model 100pF & 1.5kΩ 2 300 kV V oC VESD EIAJ Norm 200pF & 0Ω Tstg Storage Temperature -40 to 150 Tj Junction Temperature 150 o C 0 to 70 o C Toper Operating Temperature (Device ambient) THERMAL DATA Symbol R TH(j-a) Parameter Junction to Ambient Thermal Resistance (MAX) Value 46 Unit oC/W SYNC INPUT Operating Conditions (VDD = 5V, Tamb = 25°C) Symbol Parameter Test Conditi ons Min HSVR Voltage on Hin Pin 44 0 MinD Min Hin pulse duration Pin 44 0.7 Mduty Max Hin Duty Cycle Pin 44 VSVR Voltage on Vin Pin 1 0 VSW Min Vin pulse duration Pin 1 5 VSD Max Vin Duty Cycle Pin 1 Typ Max Unit 5 V us 25 % 5 V us 15 % 0.8 V V Electrical Characteristics (VDD = 5V, Tamb = 25°C) V INTH RIN Horizontal & Vertical Input Logic Level Horizontal & Vertical Pull-Up Resistor Low Level High Level 2.2 200 kΩ 5/38 4 STV2000 I2C READ/WRITE Electrical Characteristics (VDD = 5V, Tamb = 25°C) Symbol Parameter Test Conditi ons Min Typ Max Unit 100 kHz FSCL Maximum Clock Frequency TLOW Low Period of the SCL Clock 1.3 us THIGH High Period of SCL Clock 0.6 us VINL SDA & SCL Input Low Level Voltage VINH SDA & SCL Input High Level Voltage VACK Acknowledge Output Voltage on SDA input with 3mA 1.5 3 V V 0.4 V Max Unit HORIZONTAL SECTION Operating Conditions Symbol Parameter Test Conditi ons Min Typ VCO Ro(min) Minimum Oscillator Resistor Co(min) Minimum Oscillator Capacitor Fmax 6 kΩ 390 pF Maximum Oscillator Frequency 150 kHz Horizontal FlyBack Input Maximum Current 5 mA Horizontal Drive Output Maximum Sink Current 15 mA OUTPUT SECTION IHFB IHOUT Electrical Characteristics (VDD = 5V, Tamb = 25°C) Symbol Parameter Test Conditi ons Min Typ Max Unit SUPPLY AND REFERENCE VOLTAGES Supply Voltage 9.5 10.5 11.5 V Vdd Supply Voltage 4.5 5 5.5 V Icc Supply Current 30 mA Idd Supply Current 5 mA VHREF Horizontal Reference Voltage I=-2mA 7.4 8 8.6 V VVREF Vertical Reference Voltage I=-2mA 7.4 8 8.6 V 6/38 4 Vcc IHREF Horizontal Reference Maximum Source Current 5 mA IVREF Vertical Reference Maximum Source Current 5 mA STV2000 Operating Conditions Symbol Parameter Test Conditi ons Min Typ Max Unit 3.8 V 1st PLL SECTION V clamp VCO clamp Voltage range VHREF=8V VVCO VCO clamp Voltage, at POR VHREF=8V 3.8 V AVCO VCO Gain Ro=6490Ω, Co=820pF, dF/dV=1/11RoCo 17.1 kHz/V HPHASE Horizontal Phase Adjustment Range % of Horizontal Period +/-10 % VPMIN VPTYP VPMAX Horizontal Phase Minimum Typical Maximum SubAdd 07 X1111111 X1000000 X0000000 2.8 3.4 4.0 V V V IPLL1-UL I PLL1-L PLL1 Charge Pump Current Unlocked Locked +/-140 +/-1 µA mA 65 kHz fO dfo/dT Free Running Frequency, no input at POR, lower clamp voltage at max. 3.0 Ro=6490Ω, Co=820pF Free Running Frequency Thermal Drift -150 ppm/ oC 2nd PLL SECTION & HORIZONT AL OUTPUT SECTION VTHFB Flyback Input Threshold Voltage JitterH Horizontal Jitter H DC Vphi2 0.65 At 60KHz Horizontal Drive Output Duty Cycle (Ratio of Power Transistor OFF time to Period) Internal Clamp Level on PLL2 Filter VSCinh Threshold Voltage to Stop H-Out, V-Out, Reset ABL when Vcc<VSCinh VsatHD Horizontal Drive Output Saturation Voltage Low Level High Level Iout=15mA 0.75 V 70 ppm 48 % 1.6 4.0 V V 6.9 V 0.4 V 7/38 4 STV2000 VERTICAL SECTION Symbol Parameter Test Conditi ons Min Typ Max Unit Electrical Characteristics (VDD = 5V, Tamb = 25°C) VERTICAL RAMP SECTION VRBOT Voltage at Ramp Bottom Point V VREF=8V 2 V VRTOP Voltage at Ramp Top Point with Sync V VREF=8V 5 V VRTOPF Voltage at Ramp Top Point without Sync V VREF=8V VRTOP0.1 V TVDIS Vertical Sawtooth Discharge Time COSC=150nF 70 µs FFRV Vertical Free Running Frequency (S correction inhibited) C OSC=150nF 100 Hz ASFR Auto-Sync Frequency Range COSC=150nF RAFD Ramp Amplitude Drift Versus Frequency at Maximum Vertical Amplitude C OSC=150nF 50Hz 165Hz 200 ppm/Hz 2.5V < VOSC < 4.5V 0.5 % Sub-Add=09 X0000000 X1000000 X1111111 3.3 3.65 3.2 3.5 3.8 V V V 2.5 3.5 2.25 3 3.75 V V V RLIN VPOS VOR Ramp Linearity at Vcap pin with S Correction inhibited Vertical Position Adjustment Voltage with VOUT mean value Vertical Output Peak to Peak Voltage IVOUT Vertical Output Maximum Current V VRB Vertical Ramp Filter Voltage dVS Max Vertical S-Correction Amplitude S-Correction inhibited, DV/Vpp at TV/4 S-correction Maximum, DV/Vpp at 3TV/4 50 Sub-Add=08 10000000 11000000 11111111 165 Hz +/-5 mA 2 V Sub-Add 0A 0XXXXXXX -4 % 11111111 +4 % DC Output Voltage with Typical VPOS and Keystone inhibited With external driver connected as unity gain buffer 2.0 V TDEWDC DC Output Voltage Thermal Drift (Non-test Parameter) 100 ppm/ oC EWPARA Parabola Amplitude with Max VAMP, Typ VPOS, Keystone inhibited 1.0 0.5 0 V V V EAST/WEST FUNCTION (output is internal, can be checked at EWFB pin indirectly) EWDC 8/38 4 Sub-add 0C 11111111 11000000 10000000 STV2000 Symbol Parameter Test Conditi ons EWtrack Parabola Amplitude Function of VAMP Control (tracking between VAMP & EW) with Typ VPOS, Keystone, Typ EW Amplitude. Sub-address 08 10000000 11000000 11111111 KeyAdj Keystone Adjustment Capability with Typ VPOS, EW inhibited and Max Vertical Amplitude Sub-address 0B 10000000 11111111 Sub-add 09 KeyTrack Intrinsic Keystone Function of VPOS Control (tracking between VPOS and EW) with Max EW Amplitude and Max Vertical Amplitude A/B Ratio B/A Ratio Min Typ Max Unit V V V 0.2 0.2 X0000000 X1111111 Vpp Vpp 0.52 0.52 INTERNAL DYNAMIC HORIZONTAL PHASE CONTROL SBPpara Side Pin Balance Parabola Amplitude with Max VAMP, Typ VPOS and Parallelogram inhibited Sub-add 0E 11111111 10000000 Sub-add 08 10000000 SPBtrack Side Pin Balance Parabola Amplitude function of VAMP Control (tracking between VAMP & SPB) with Max SPB, Typ VPOS and Parallelogram inhibited ParAdj Partrack +1.4 -1.4 %TH %TH 11111111 0.5 0.9 1.4 %TH %TH %TH Parallelogram Adjustment Capability with Max VAMP, Typ VPOS and Max SPB Sub-add 0F 11111111 10000000 +1.4 -1.4 %TH %TH Intrinsic Parallelogram Function of VPOS Control (tracking between VPOS and DHPC) with Max VAMP, Max SPB and Parallelogram inhibited A/B Ratio Sub-add 09 B/A Ratio 11000000 X0000000 X1111111 0.52 0.52 VERTICAL BREATHING COMPENSATION VBRrng Input DC Breathing Control Range VBRadj Vertical Output Variation versus DC Breathing Control 1 10.5 V Vbrin>V VREF Vbrin=4V 0 -10 % % sub-add 0D X0000000 X1111111 0 2.4 V V HORIZONTAL SIZE CONTROL Hsize Hsize output DC voltage sitting on top of EWDC=2.0V EW OUTPUT BUFFER Iewout EWout pin max source current EWFB EWoutput referred DC voltage 3.0 mA 2.0 V 9/38 4 STV2000 Symbol Parameter Test Conditi ons Min Typ Max Unit 10.5 V HORIZONTAL BREATHING COMPENSATION HBRdc HSC Breathing input DC Control Range 1 Horizontal size compensation, EW DC voltage variation under full range of HBRdc 0.4 V VIDEO PRE-AMP SECTION Symbol Parameter Test Conditi ons DC Electrical Characteristics (VAVCC = PVCC = 10.5V, Tamb = VAV cc Video Section Analog Supply Voltage PVcc Power Section Supply Voltage Min Typ Max Unit 9.5 10.5 11.5 V 9.5 10.5 11.5 V 25oC) IS Supply Current of VAVcc & PVcc 60 VIN Video Input Voltage Amplitude 0.7 VOUT Typical Output Voltage Range V DC Output DC level (Black level) 0.5 Vpp 7 V Condition Min Typ V 25oC) Max Unit Maximum Gain Max Contrast and Drive I2C Gainwin = 1 18 dB CAR Contrast Attenuation Range VIN = 0.7Vpp Contrast and Drive at POR 30 dB DAR Drive Attenuation Range 30 dB GM Gain Match VIN = 0.7Vpp, VOUT = 4Vpp, Contrast and Drive= 0.87Max +-0.1 dB BW Large Signal Bandwidth VIN=0.7Vpp, VOUT = 4Vpp, Contrast and Drive = 0.87Max At -3dB 70 MHz DIS Video Output Distortion 0.3 % tR, tF Video Output Rise and Fall Time dVo Overshoot of output with respect to actual output amplitude BRT Brightness max DC level Brightness min DC level AV RL Tsample 10/38 4 Parameter 1 1.5 AC Electrical Characteristics (VAVCC = PV CC = 10.5V, CL = 12pF, RL = 1KΩ, Tamb = Symbol mA Equivalent Load on Video Output Hold time f=1MHz, VIN=1Vpp, VOUT = 1Vpp VIN = 0.7Vpp, VOUT =4Vpp,Contrast and Drive=0.87Max CLOAD=5pF 5 Tj<TjMAX 100 5 ns 7 % 2.5 0 V V 1 kΩ ms STV2000 Symbol Thold CT Parameter Test Conditi ons Sample time Crosstalk Between Video Channels VIN = 0.7Vpp, VOUT = 2.5Vpp, Contrast and Drive=0.7Max f=1MHz Min Typ Max Unit 1 µs 44 dB CUTOFF VCUTOFF CUTOFF DAC output voltage ICUTOFF Output sink current Output source current 00000000 10000000 11111111 0.5 2.5 4.5 V V V 100 2 µA mA ABL COMPENSATION R ABL ABL Input resistor GABL ABL minimum Attenuation ABL maximum Attenuation THABL ABL latch function activation threshold (High beam current detection) VABL=5.3V VABL=2.8V 10 kΩ 0 12 dB dB 0 1 V DAC VDAC ILOAD=100uA IDAC Source current sub-add 12 00000000 01000000 01111111 0.5 2.25 4.0 V V V 1.5 2 mA Min Typ LOGIC SECTION DC Electrical Characteristics (VAVCC = PVCC = 10.5V, Tamb = 25oC) Symbol Parameter Condition Max Unit V BLANKING OUTPUT SECTION Blanking output high voltage VBDC Blanking output low voltage I2C adjustable IBLK Output sink current TBLK Vertical blanking time (gated with Hflyback) 7 sub-add10 1X000000 1X111111 V 1 4.5 V V 0.3 mA 22 H cycle SUPPLY VOLTAGE THRESHOLD VTHPD1 Supply first threshold voltage 8.5 V VTHPD2 Supply second threshold voltage 6.9 V 11/38 4 STV2000 I2C BUS ADDRESS TABLE [0] denotes POR value, X denotes unused data bit and must be set to 0. D8 D7 D6 WRITE MODE (SLAVE ADDRESS= 8C) Video: 1, on 00 [0], off [1] [0] 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12/38 4 D4 D3 D2 D1 [1] Contrast [1] [0] [1] [0] [0] [1] [0] [0] [0] [1] [0] [0] [1] [0] [1] Cut off 1 [0] [1] [0] Cut off 2 [0] [1] [0] Cut off 3 [0] [1] [0] Horizontal Phase Adjustment [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] Horizontal Amplitude [0] [0] Side Pin Balance [0] [0] [0] [0] [0] [0] [0] [0] [1] [1] [1] [1] [0] [1] Drive 1 [1] [0] [1] [1] Drive 2 [1] [0] [1] [1] Drive 3 [1] [0] [1] [0] [0] [0] [0] [0] [0] [0] Hout 0, off [1], on Vramp 0, off [1], on Xray 1, reset [0] S Select 1, on [0], off EW Key 0, off [1], on EW Select 0, off [1], on [0] [0] [1] [0] x SPB Sel 0, off [1], on Parallelog 0, off [1], on VBDC 1, on [0], off POR [0], off 1, reset 12 13 D5 x [0] [0] Vertical Ramp Amplitude Adjustment [1] [0] [0] [0] [0] Vertical Position Adjustment [1] [0] [0] [0] S Correction [1] [0] [0] [0] Keystone [1] [0] [0] [0] EW Amplitude [1] [0] [0] [1] [0] [0] [1] [0] [0] [0] [0] Parallelogram [1] Gainwin [0], 1X 1, 1.5X Powsav 1, on [0], off [0] [0] [0] Vertical Blanking DC level [1] [1] [1] Brightness [1] [0] [1] [1] [0] [0] DAC [0] x x x [0] [0] [0] PLL1 filter voltage clamp (FVC) [0] [0] [0] [0] STV2000 D8 D7 D6 D5 D4 READ MODE (SLAVE ADDRESS = 8D) Xray 1, on [0], off Hlock 0, lock [1], unlock D3 D2 D1 Figure 1. EW Output Referred Voltage B EWPARA A EWDC Figure 2. Dynamic Horizontal Phase Control Output EWPARA B A DHPC DC SPBPARA Figure 3. Keystone Effect on EW Output (PCC Inhibited) Keyadj 13/38 4 STV2000 TYPICAL OUTPUT WAVEFORMS Function Sub Address Pin Byte Specification Effect on Screen 2.25 V 10000000 Vertical Size 3.75 V 11111111 Vertical Position Vertical S Linearity x0000000 x1000000 x1111111 V OUTDC = 3.2 V V OUTDC = 3.5 V VOUTDC = 3.8 V 00000000 Inhibited 11111111 EW Inhibited 10000000 VPP 2.0V 0.2Vpp 2.0V 0.2Vpp Keystone 11111111 EW Inhibited EW Pin Cushion 10000000 11111111 14/38 4 2.0 V 1.0 V 2.0 V STV2000 Function Sub Address Pin Byte Specification Effect on Screen 10000000 H Amplitude 11111111 5 V 5 V 00000000 H Phase 01111111 Parallelogram Inhibited Side Pin Ballance Control 3.7 V 1.4% 10000000 11111111 1.4% 3.7 V SPB Inhibited Parallelogram Control 10000000 3.7 V 1.4% 11111111 3.7 V 1.4% 15/38 4 Contrast Register (Video IN = 0.5VPP, Drive at maximum, I2C Gainwin=1) Hex b7 b6 b5 b4 b3 b2 b1 b0 Vpp G(dB) 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 1 0.015 -30 0 0 0 0 0 0 1 0 0.031 -24 0 0 0 0 0 1 0 0 0.062 -18 0 0 0 0 1 0 0 0 0.125 -12 0 0 0 1 0 0 0 0 0.25 -6 0 0 1 0 0 0 0 0 0.5 0 0 1 0 0 0 0 0 0 2 12 0 1 0 1 1 0 1 0 2.812 15 0 1 1 1 1 1 1 1 4 18 POR X Brightness Register (Drive at maximum) Hex b5 b4 b3 b2 b1 b0 Vpp 0 0 0 0 0 0 0 0 0 0 0 0 1 0.010 0 0 0 0 1 0 0.020 0 0 0 1 0 0 0.040 0 0 1 0 0 0 0.08 0 1 0 0 0 0 0.16 1 0 0 0 0 0 0.32 0 0 0 0 0 0 0.64 0 0 0 0 0 0 1.28 1 0 1 1 0 1 1.8 1 1 1 1 1 1 2.56 POR X Drive1, Drive2, Drive3 Registers (Video IN = 0.5VPP, Contrast at maximum, I2C Gainwin=1) Hex b7 b6 b5 b4 b3 b2 b1 b0 00 0 0 0 0 0 0 0 0 0 - 01 0 0 0 0 0 0 0 1 0.015 -30 02 0 0 0 0 0 0 1 0 0.031 -24 04 0 0 0 0 0 1 0 0 0.062 -18 08 0 0 0 0 1 0 0 0 0.125 -12 10 0 0 0 1 0 0 0 0 0.25 -6 20 0 0 1 0 0 0 0 0 0.5 0 40 0 1 0 0 0 0 0 0 1 6 80 1 0 0 0 0 0 0 0 2 12 G(dB) B4 1 0 1 1 0 1 0 0 2.812 15 FF 1 1 1 1 1 1 1 1 4 18 16/38 5 Vpp POR X STV2000 Cutoff1, Cutoff2, Cutoff3 Output values Hex b7 b6 b5 b4 b3 b2 b1 b0 FB pin 00 0 0 0 0 0 0 0 0 0.5 01 0 0 0 0 0 0 0 1 02 0 0 0 0 0 0 1 0 04 0 0 0 0 0 1 0 0 08 0 0 0 0 1 0 0 0 10 0 0 0 1 0 0 0 0 20 0 0 1 0 0 0 0 0 40 0 1 0 0 0 0 0 0 80 1 0 0 0 0 0 0 0 B4 1 0 1 1 0 1 0 0 FF 1 1 1 1 1 1 1 1 0.625 POR X 4.5 DAC Output DC voltage Hex b6 b5 b4 b3 b2 b1 b0 Output dc 0 0 0 0 0 0 0 0.5 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 1 0 0 1 1 1 1 1 1 1 2.25 POR X 4.0 Vertical Blanking Output DC voltage Hex b5 b4 b3 b2 b1 b0 Output dc 0 0 0 0 0 0 1.0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 1 1 1 1 1 4.5 POR X 17/38 5 STV2000 OPERATING DESCRIPTION A SCANNING PART 1. GENERAL CONSIDERATIONS 1.1 Power Supply Typical power supply voltages are 10.5 V for the Deflection and Preamplifier sections (SAVCC, VAVCC and PVCC) and 5.0 V for the logic section (Vdd). Optimum operation is obtained between 9.5 and 11.5 for VCC, and between 4.5 and 5.5 V for VDD. VCC is monitored during the transient phase when switched either on or off, to avoid erratic operation of the circuit. If VCC is inferior to 6.9 V typ., the circuit outputs are inhibited. Similarly, before VDD reaches 4 V, all the I2C registers are reset to their default value (see I2C Control Table). The circuit is internally supplied by several voltage references (typ. value: 8 V) to ensure a good power supply rejection. Two of these voltage references are externally accessible respectively for the vertical and horizontal parts. They can be used to bias external circuitry if ILOAD is inferior to 5 mA. To minimize the noise and consequently the ”jitter” on vertical and horizontal output signals, the reference voltages must be filtered by external capacitors connected to the ground. 1.2 I2 C Control STV2000 belongs to the I2C-controlled device family. Each adjustment can be made via the I2C Interface, instead of being controlled by DC voltages on dedicated control pins. The I 2C bus is a serial bus with a clock and a data input. General function and bus protocol are specified in the Philips-bus data sheets. The interface (Data and Clock) is TTL-compatible. Spikes up to 50 ns are filtered by an integrator and the maximum clock speed is limited to 100 kHz. The data line (SDA) can be used bidirectionally. In read mode, the IC sends reply information (1 byte) to the micro-processor. The bus protocol prescribes a full-byte transmission in all cases. The first byte after the start condition is used to transmit the IC address (hexa 8C for write, 8D for read). All bytes are sent MSB bit first and the write data transfer is closed by a stop. 18/38 6 1.3 Write Mode In write mode, the second byte contains the subaddress of the selected function to adjust (or controls to effect) and the third byte the corresponding data byte. More than one data byte can be sent to the IC. If after the third byte no stop or start condition is detected, the circuit automatically increments the momentary subaddress in the subaddress counter (auto-increment mode) by one. Thus it is possible to immediately transmit the following data bytes without sending the IC address or subaddress. This can be useful for reinitializing all the controls very quickly (flash manner). This procedure is ended with a stop condition. There are 19 adjustment capabilities for the circuit: 3 for the horizontal part, 3 for the vertical, 3 for the E/W correction, 2 for the dynamic horizontal phase control, 7 for the preamplifier and 1 for the blanking DC. 14 bits are also dedicated to several controls (ON/OFF). 1.4 Read Mode In the read mode the second byte transmits the reply information. The reply byte contains the horizontal and vertical lock/unlock status, the XRAY activation status. A stop condition always stops all the activities of the bus decoder and switches both the data and clock line (SDA and SCL) to high impedance. See I2C subaddress and control tables. 1.5 Sync Processor The internal sync processor allows the device to receive separate horizontal & vertical TTL-compatible sync signals. 1.6 IC Status The IC informs the MCU about both the 1st horizontal PLL (locked or not) and the XRAY protection (activated or not). The XRAY internal latch is reset either directly via the I2C interface or by decreasing the VCC supply. 1.7 Sync Inputs Both HIN and VIN inputs are TTL compatible triggers with hysterisis to avoid erratic detection. Both inputs include a pull-up resistor connected to VDD. Synchro pulses must be positive. STV2000 OPERATING DESCRIPTION (continued) 1.8 Sync Processor Output The sync processor indicates whether 1st PLL is locked to an incoming horizontal sync or not. This is indicated on the D8 bit of the status register . PLL1 level is low when locked. 2. HORIZONTAL PART 2.1 Internal Input Conditions A digital signal (horizontal sync pulse) is sent by the sync processor to the horizontal input. It must be positive (see Figure 4). Synchronization occurs on the leading edge of the internal sync signal. The minimum value of Z is 0.7 µs. Vertical synchro extraction is not allowed. Figure 4. frequencies. It is followed by a ”charge pump”, composed of two current sources: sunk and sourced (typically I =1 mA when locked and I = 140 µA when unlocked). This difference between lock/unlock allows smooth catching of the horizontal frequency by PLL1. This effect is reinforced by an internal original slow down system when PLL1 is locked, preventing the horizontal frequency from changing too quickly. The dynamic behaviour of PLL1 is fixed by an external filter which integrates the current of the charge pump. A ”CRC” filter is generally used (see Figure 5). Figure 5. PLL1F Z 40 T 1.8kΩ 2.2 PLL1 The PLL1 consists of a phase comparator, an external filter and a voltage-controlled oscillator (VCO). The phase comparator is a ”phase frequency” type designed in CMOS technology. This kind of phase detector avoids locking on wrong 10nF 4.7µF Figure 6. Block Diagram Lock/Unlock Status PLL1F 40 R0 C0 42 41 FC1 43 LOCKDET High H/HVIN 44 CHARGE PUMP COMP1 VCO Low OSC 39 Filter PHASE ADJUST I 2C HPOS Adj. 19/38 6 STV2000 OPERATING DESCRIPTION (continued) Figure 7. Details of VCO I0 I0 2 6.4V PLL1F 40 (Loop Filter) RS FLIP FLOP 1.6V 4 I0 42 (1.4V<V 7<6.4V) 41 R0 6.4V C0 1.6V 0 0.875TH TH The VCO uses an external RC network. It delivers a linear sawtooth resulting from the capacitor charge and discharge . The current is proportional to the one in the resistor. Typical thresholds for the sawtooth are 1.6 V and 6.4 V. The VCO control voltage varies between 3.0 V and 3.8 V (see Figure 7). This VCO frequency range is very small. The small effective frequency is due to clamp intervention on the lowest filter value. The PLL1F filter voltage is set by a 4-bit DAC with a voltage range of 3.0 to 3.8 V. The sync frequency must always be higher than the free running frequency. For example, when using a 60 kHz synchro range, the suggested free running frequency is 56 kHz. PLL1 ensures the coincidence between the leading edge of the sync signal and a phase reference resulting from the comparison of: – the VCO sawtooth – an internal DC voltage I2C adjustable within the range of 2.9V to 4.2V (corresponding to ±10%) (see Figure 8). A Lock/Unlock identification block, also included, detects in real time whether PLL1 is locked on the incoming horizontal sync signal or not. The lock/unlock information is available through the I2C read. The FC1 Pin (Pin 43) is used for decoupling the internal 6.4 V reference by a capacitor. Figure 8. PLL1 Timing Diagram H O SC Sawtooth 7/8 TH 1/8 TH 6.4V 3.4V (Reference for H Position) Vb (2.8V<Vb<4.2V) 1.6V Phase REF1 HSynchro Phase REF1 is obtained by comparison between the sawtooth and a DC voltage adjustable between 2.9 V and 4.2 V. The PLL1 ensures the exact coincidence between the signal phase REF and HSYNC. A ±10% TH phase adjustment is possible around the 3.5V point. 20/38 6 STV2000 OPERATING DESCRIPTION (continued) 2.3 PLL2 PLL2 ensures a constant position of the shaped flyback signal in comparison with the sawtooth of the VCO, taking into account the saturation time Ts (see Figure 9). Figure 9. PLL2 Timing Diagram H Osc Sawtooth 1/8TH 7/8TH 6.4V 4.0V 1.6V Flyback Internally Shaped Flyback duction period of the horizontal scanning transistor. The maximum storage time (Ts Max.) is : 0.44TH- TFLY/2). Typically, TFLY/TH corresponds to around 20 % which means that Ts max represents approxim tively 34 % of TH. 2.4 Output Section The H-drive signal is sent to the output through a shaping stage which also controls the fixed Hdrive duty cycle (see Figure 9). In order to secure the scanning power part operation, the output is inhibited in the following cases : -when VCC is too low, -when the ABL protection is activated, -during the Horizontal flyback, -when the HDrive I2C bit control is off. The output stage consists of a NPN bipolar transistor. Only the collector is accessible (see Figure 11). Figure 11. H Drive V CC Ts Duty Cycle The phase comparator of PLL2 (phase type comparator) is followed by a charge pump (typical output current: 0.5 mA). The flyback input consists of an NPN transistor. This input must be current driven. The maximum recommended input current is 5 mA (see Figure 10). 34 Hout Figure 10. Flyback Input Electrical Diagram 400Ω HFLY Q1 36 20kΩ GND 0V The duty cycle is fixed at 48%. For a safe start-up operation, the initial duty cycle (after power-on reset) is 85% in order to avoid having too long a con- This output stage is intended for ”reverse” base control, where setting the output NPN in off-state will control the power scanning transistor in offstate. The maximum output current is 15 mA, and the corresponding voltage drop of the output VCEsat is 0.4 V Max. Obviously, the power scanning transistor cannot be directly driven by the integrated circuit. An interface either bipolar or MOS type has to be added between the circuit and the power transistor. 21/38 6 STV2000 OPERATING DESCRIPTION (continued) 2.5 X-RAY Protection X-Ray protection is activated when the ABL input (1 V on Pin 20) is at a low level. It inhibits both H-Drive, and Vout while Video goes into off-mode. This activation is internally delayed by 2 lines to avoid erratic detection (short parasitics). This protection is latched; it may be reset either by switching VCC off or by I2C (see Figure 12). Figure 12. Safety Functions Block Diagram VCC Checking HORIZONTAL OUTPUT INHIBITION VCC VSCinh +1V XRAY Protection + ABL 20 I2C Drive on/off VCC off or I C Reset 2 S R Q I2C Ramp on/off VERTICAL OUTPUT INHIBITION Horizontal Flyback 0.7V Video-off 3. VERTICAL PART 3.1 Function When the synchronization pulse is not present, an internal current source sets the free running frequency. For an external capacitor, COSC = 150nF, the typical free running frequency is 100Hz. The typical free running frequency can be calculated according to: 1 fo(Hz) = 1.5 . 10-5 . COSC A positive TTL level pulse applied on Pin 1(Vin) is used to synchronize the ramp in the range [fmin, fmax] (see Figure 13). This frequency range depends on the external capacitor connected on Pin 5. A 150nF (± 5%) capacitor is recommended for 50 Hz to 165 Hz applications. The typical maximum and minimum frequency, at 25 oC and without any correction (S correction), 22/38 6 can be calculated as follows: f(Max.) = 3.5 x fo and f(Min.) = 0.33 x fo When an S correction is applied, these values are slightly modified. With a synchronization pulse, the internal oscillator is synchonized immediately but its amplitude changes. An internal correction then adjusts it in less than half a second. The ramp top value (Pin 5) is sampled on the AGC capacitor (Pin 3) at each clock pulse. A transconductance amplifier modifies the charge current of the capacitor so as to make the amplitude constant again. We recommend using an AGC capacitor with a low leakage current. A value lower than 100nA is mandatory. A good level of stability for the internal closed loop is obtained by a 470nF ± 5% capacitor value on Pin 3 (VAGC). VRB (Pin 8) is used for decoupling the internal 2V reference voltage by a capacitor. STV2000 OPERATING DESCRIPTION (continued) 3.2 I2C Control Adjustments S correction shapes can then be added to this ramp. This frequency-independent S correction is generated internally. Its amplitudes is adjustable via the I2C. S correction can be inhibited by applying the selected bits. Finally, the amplitude of the S corrected ramp is adjustable via the vertical ramp amplitude control register.The adjusted ramp is available on Pin 6 (VOUT) to drive an external power stage. The gain of this stage can be adjusted (± 25%) depending on its register value. The mean value of this ramp is driven by its own I2C register (vertical position) with : VPOS = 7/16 x VREF-V = ± 300 mV. Usually VOUT is sent through a resistive divider to the inverting input of the booster. Since VPOS derives from VREF-V, the bias voltage sent to the noninverting input of the booster should also derive from VREF-V to optimize the accuracy (see Figure 13). Figure 13. AGC Loop Block Diagram CHARGECURRENT TRANSCONDUCTANCE AMPLIFIER REF 5 DISCH. VSYNCIN 1 SYNCHRO 3 OSC CAP SAMPLING SAMPLING CAPACITANCE OSCILLATOR S CORRECTION VS AMP SUB07/7bits Vlow 7 BREATH Sawth Disch. 6 VOUT VERT AMP SUB08/7bits VPOSITION SUB09/7bits 3.3 Basic Equations As a first approximation, the amplitude of the ramp on Pin 6 (VOUT) is calculated as follows: V OUT - VPOS = (VOSC - VDCMID) x (1 + 0.25 (VAMP)) where : VDCMID = 7/16 x VREF (middle value of the ramp on Pin 5, typically 3.6V) VOSC = V5 (ramp with fixed amplitude) VAMP = -1 as minimum vertical amplitude register value and +1 as maximum value. VPOS is calculated according to: VPOS = VDCMID + (0.4x VP ) where VP = -1 and +1 as respectively minimum and maximum vertical position register value. The current available on Pin 5 is: 3 IOSC = x VREF x COSC x f 8 where COSC = capacitor connected on Pin 5 f = synchronization frequency. 23/38 6 STV2000 OPERATING DESCRIPTION (continued) 3.4 Geometric Corrections The principle is represented in Figure 14. Starting from the vertical ramp, a parabola-shaped current is generated for E/W correction (also known as Pin Cushion correction), dynamic horizontal phase control correction. The parabola generator consists of an analog multiplier, the output current of which is equal to : ∆I = k x (VOUT - VDCMID) 2 where VOUT is the vertical output ramp (typically between 2 and 5 V) and VDCMID is 3.6 V (for VREF-V = 8.2V). The VOUT sawtooth is typically centered on 3.6 V. By changing the vertical position, the sawtooth shifts by ±0.4 V. The ”geometry tracking” feature ensures a correct screen geometry for any end user adjustment. It generates non-symmetric parabola dependent on the vertical position. Due to the large output stage voltage range (E/W Pin Cushion, Keystone), the combination of the tracking function, maximum vertical amplitude, maximum or minimum vertical position and maxi- mum gain on the DAC control may lead to output stage saturation. This must be avoided by limiting the output voltage with appropriate I2C register values. For the E/W part and the dynamic horizontal phase control part, a sawtooth-shaped differential current in the following form is generated: ∆I’ = k’ . (VOUT - VDCMID). Then ∆I and ∆I’ are added and converted into voltage for the E/W part. Each of the two E/W components or the two dynamic horizontal phase control components may be inhibited by their own I2C select bit. Internal EW correction voltage is not available directly on the output pin. The EW correction is obtained with the feedback voltage (Pin 27: EWBin) which generates a modulating current in the diode (Pin 28). In addition, the horizontal width is I2Ccontrolled. The dynamic horizontal phase control drives the H-position internally, moving the HFLY position on the horizontal sawtooth in the range of ± 2.8 %TH both for side pin balance and parallelogram. Figure 14. Geometric Corrections Principle 3.5 E/W EWOUT = EWDC + K1 (VOUT - VDCMID) +K2 (VOUT - VDCMID)2 K1 is adjustable via the keystone I2C register. K2 is adjustable via the E/W amplitude I2C register. 24/38 6 STV2000 OPERATING DESCRIPTION (continued) 3.6 Dynamic Horizontal Phase Control IOUT= K4 (VOUT - VDCMID) + K5 (VOUT - VDCMID)2 K4 is adjustable via the parallelogram I2C register. K5 is adjustable via the side pin balance I2C register. 3.7 Horizontal Breathing Horizontal breathing compensation is performed through the EW stage with the Voltage-Current Converter. This DC-controlled input provides the required horizontal width corrections to offset width changes arising from EHT variations. 3.8 Vertical Breathing Vertical breathing compensation is performed through the gain modulation of the vertical ramp. This DC-controlled input provides the vertical height corrections required to offset height changes arising from EHT variations. B PRE-AMPLIFIER PART 1. GENERAL CONSIDERATIONS 1.1 Input Stage The R, G and B signals must be supplied to the three inputs through coupling capacitors (100nF). The maximum input peak-to-peak video amplitude is 1 V. The input stage includes a clamping function. This clamp uses the input serial capacitor as ”memory capacitor” and is gated by an internally generated ”Back-Porch-Clamping-Pulse (BPCP)”. The BPCP is synchronized on the second edge of the horizontal pulse HIN inputs on Pin 44. Figure 15. . HSYNC BPCP Internal pulse width is fixed at 1µs In both cases, BPCP width is fixed. 1.2 Contrast Adjustment (7 bits) The contrast adjustment is made by simultaneously controlling the gain of three internal variable gain amplifiers through the I2C bus interface. The contrast adjustment allows covering a range higher than 40 dB. This adjustment is refreshed during the vertical retrace time. 1.3 ABL Control The STV2000 has an ABL input (automatic beam limitation) to attenuate RGB video signals according to beam intensity. The operating range is typically 2.5 V, from 5.3 V to 2.0 V. A typical 12 dB Max. attenuation is applied to the signal whatever the current gain. Refer to Figure 16 for ABL input attenuation range. In the case of software control, the ABL input must be pulled to AVCC through a resistor to limit power consumption. ABL input voltage must not exceed VAVCC . Input resistor is 10kΩ. 25/38 6 STV2000 OPERATING DESCRIPTION (continued) Figure 16. 2 large drive adjustment range (48dB) allows different standard or custom color temperatures. The drive adjustment is also used to adjust the output voltages at the optimum amplitude to drive the C.R.T drivers, keeping the whole contrast control for end-users only. The drive adjustment is made after the contrast and brightness so that the white balance remains correct when BRT is adjusted. Attenuation (dB) 0 -2 -4 -6 -8 -10 -12 -14 VIN(V) 1 2 3 4 5 6 7 8 9 1.4 Brightness Adjustment (6 bits) As with contrast adjustment, brightness is controlled by I2C. The brightness function consists of adding the same DC offset to the three R, G, B signals after contrast amplification. This DC-Offset is present only outside the blanking pulse (see Figure 18). The DC output level is forced to ”INFRA-BLACK” level (VDC) during the blanking pulse. 1.5 Drive Adjustment (3 x 8 bits) To adjust the white balance, the device offers the possibility of separately adjusting the overall gain of each complete video channel. Each channel gain is controlled by I2C (8 bits each). The very 1.6 Output Stage The three output stages (see Figure 17) incorporate three functions: • The blanking stage: when the internal generated blanking pulse is high, the three outputs are switched to a voltage which is 400 mV lower than the BLACK level. The black level is the output voltage with minimum brightness when the input signal video amplitude is equal to ”0”. • The output stage itself: a large bandwidth output amplifier which can deliver up to 5VPP on the three outputs (for 0.7 V video signal on the inputs). • The output CLAMP: the IC also incorporates three internal output clamps (sample and hold system) used for the DC to shift the three output signals. The DC output voltage is fixed at 1.5 V. The overall waveforms of the output signal according to the different adjustments are shown in Figure 18.and Figure 19. Figure 17. 10 Vout CRT Driver S/H 1.5V Cut-off DAC 8 bits 11 Cut-off STV2000 26/38 6 STV2000 OPERATING DESCRIPTION (continued) Figure 18. Waveforms VOUT, BRT, CONT HSYNC BPCP BLK Video IN VOUT1, VOUT2, VOUT3 VCONT (4) CONT VBRT (3) BRT 0.4V fixed VBLACK (2) VDC (1) Note : 1. VDC = 1.5V 2. VBLACK = VDC + 0.4V 3. VBRT = VBLACK + BRT (with BRT = 0 to 2.5V) 4. VCONT = VBRT + CONT with CONT = k x video (CONT = 5VPP max. for VIN = 0.7V PP) Figure 19. Waveforms (DRIVE adjustment) HSYNC BPCP BLK Video IN VOUT1 , V OUT2 , VOUT3 VCONT VBRT VBLACK VDC two examples of drive adjustment (1) Note : 1. Drive adjustment modifies the following voltages : VCONT, VBRT . . Drive adjustment does not modify the following voltages : VDC and VBLACK. 27/38 6 STV2000 OPERATING DESCRIPTION (continued) 1.7 Cutoff DAC Output Three Cutoff DACs (8 bits) with output buffers are incorporated to drive the external cutoff circuit. Output voltage range is from 0.5 V to 4.5 V. 1.8 Blanking Generator A vertical blanking pulse is generated (see Figure 20). The output level is a positive going pulse of 8V. The vertical blanking is started by the vertical sync pulse and the duration is determined by counting 22 horizontal periods. If there is no vertical sync pulse the vertical blanking start coincides with the beginning of the vertical capacitor discharge time. The blanking output generates a superimposed variable DC voltage. The 6-bit adjustment range is 1 V to 4.5 V. This is used to allow brightness control through G1. Additionally, this pin is used for spot killer suppression. The 0.8 V of Vcc threshold will trigger the output into a high level state resulting from the Vcc decay. Figure 20. VBDC (Pin 24) Output Voltage Waveform 22 H lines DC level controlled by 6-bit DAC 8V 4.5 V 1.0 V 1.9 DAC Output This is a 7-bit DAC with 1 output pin. An output buffer is used to enhance load capability with an Imax(source) of 2 mA. Table 1: Logic Table Conditio ns Vcc at 0 to 6.9 V (PD2 mode) Vcc at 6.9 V to 8.5 V (PD1 mode) I2C DPMS bit=1, (default=0) Hout no yes no Vout no yes no Video-off video-off video-off video-off Low Power NA (1) NA(1) yes Hlock/unlock detection = unlock yes yes video-off no no yes on/off yes yes yes yes no yes yes on/off yes yes yes video-off video-off on/off on/off on/off video-on (2) video-on (2) no no no no no NA (1) no Video ABL input pin < 1 V 5 V POR or I2C POR=1, (default=0) I2C Hout on/off, (default=1=on) I2C Vout on/off, (default=1=on) I2C Video on/off, (default=0=video-off) Vcc at >8.5 V Vcc at >8.5 V, I2C video=1=on Note 1 NA= Not applicable. Note 2 I2C video=on will be reset by I2CDPMS/Low Vcc. 28/38 6 STV2000 OPERATING DESCRIPTION (continued) C STAND-BY MODE AND PROTECTIONS 1. GENERAL CONSIDERATIONS 1.1 POR (Power On Reset) - Subadress 11- D8 POR is activated on 5 V with default values for each adjustment and in addition video off (see 1.3). It can be activated via the I2C command. 1.2 Supply Voltage Threshold. Two built-in thresholds (see figure 21) are used to enter the following modes: • PDI mode: – Activated for Vcc < 8.5V – Video off (see 1.13) • PD2 mode: – Activated for Vcc < 6.9V – Video off (see 1.13) – HOUT and VOUT disabled 1.3 Video Off (I2C control) - Subadress 00 - D8 Activates blanking of the 3 video output stages. During this time the outputs are switched to ground level, regardless of the presence of Hsync or Hflyback. Activation time is inferior to 1µs. This also activates the blanking output generating a positive going signal at pin 24 as long as “video off” is activated. 1.4 Vertical Output Off This command will switch off output VAMP. The vertical output swing is reduced to 0V. During power saver mode, the total vertical section is disabled. 1.5 Power Saver On - Subadress 11 - D7 This I2C command activates the PD1 and PD2 mode regardless of the scanning Vcc value. Internal scanning and pre-amp voltage are off. During “power saver” mode, the device power consumption will be reduced to below 20mA for all supply pins. Vdd, I2C interface and DAC data are not affected by this command. 1.6 X-Ray, Set Operation - Subadress 09 - D8 When ABL voltage is below 1 V threshold, Xray latch will be activated. This I2C command will reset the Xray latch. Activation time below 100ms. 29/38 STV2000 INTERNAL SCHEMATICS Figure 21. Figure 24. VDD 200Ω 1+ 44 200kΩ SAVCC Vgnd Figure 22. Figure 25. SAVCC SAVCC VCAP 5 Vref 2 Figure 23. Figure 26. SAVCC VAGCCAP 30/38 7 22kΩ 3 SAVCC VOUT 6 4 STV2000 INTERNAL SCHEMATICS (continued) Figure 27. Figure 30. VAVCC SAVCC V BREATH IN Pins 19 21 23 7 Agnd Agnd Figure 28. Figure 31. VAVCC Internal 5V VAVCC 9 12V BIPSWITCH 20 10k Ω AGND Agnd Figure 29. 10k Ω Figure 32. PVCC VAVCC VAVCC Pins 10, 13, 16 Agnd Pgnd Pin 11 14 17 Agnd 31/38 7 STV2000 INTERNAL SCHEMATICS (continued) Figure 33. Figure 36. VAVCC VAVCC Agnd 12 50Ω DAC 22 AGND Figure 34. Figure 37. VAVCC VBDC 24 Pgnd 15 Figure 35. Figure 38. SAVCC VAVCC 60K HBreath 26 PVCC 18 32/38 7 Vref STV2000 INTERNAL SCHEMATICS (continued) Figure 39. Figure 42. SAVCC VDD Vref 5V 10K EWFB 27 SDA 30 Figure 40. Figure 43. SAV CC VDD 5V Vref 1.5k 10k EWout 28 SCL 31 10k Figure 41. Figure 44. V DD 29 5V BIPSWITCH SAVCC 32 12V BIPSWITCH 33/38 7 STV2000 INTERNAL SCHEMATICS (continued) Figure 45. Figure 48. Href 35 SAVCC Lgnd 33 HFLY 36 Figure 46. Figure 49. SAVCC HOUT 34 Hgnd 37 Figure 47. Figure 50. SAVCC SAV cc Href PLL2C 38 Href 35 22kΩ 34/38 7 STV2000 INTERNAL SCHEMATICS (continued) Figure 51. Figure 54. Href 35 Href SAVCC SAVCC Href 42 Filter 39 Figure 52. Figure 55. SAVCC SAVCC Href 1K _ 3 PLL1F 40 FC1 43 4K _ 3 Figure 53. SAVCC Figure 56. Href 35 SAVCC Vref R1 41 VRB 8 R2 35/38 7 Vcc L3 10uH C25 100n R31 10K VOUT R31 12K R33 10K C39 1u C26 150n C27 470n CUTOFF3 OUT3 CUTOFF2 OUT2 CUTOFF1 OUT1 C31 820p R36 1K8 C0 PGND R0 CUTOFF2 C30 100n FC1 STV2000 SCL 31 VBDC 24 NC 25 HBRTH 26 EWFBIN27 EWOUT 28 VDD 29 SDA 30 Vcc L1 10uH C22 100n C21 100u IN1 R25 75 R22 47 IN2 R24 75 R21 47 R19 2K DAC 11CUTOFF1 IN3 23 DAC AGNDOUT2 12 13 14 15 16 17 18 19 20 21 22 10OUT1 9 VAVCC 8 VRB 7 VBRTHIN 6 VOUT 5 VCAP 4 VGND 3 VAGCCAP PLL1F OUT3 C29 47u C32 4u7 FILTER CUTOFF3 C28 100n PLL2C PVCC R32 1K ABLIN IN3 R23 75 R20 47 Vcc C14 100u C16 100u Vcc R18 25K C13 100n 1u 44 43 42 41 40 39 38 37 36 35 34 HIN HOUT 1 VIN LGND 33 C15 100n 2 VREF SAVCC32 HREF C17 100n Vcc 6490 R35 C35 22n 10n C34 HGND IN1 C20 100n C23 100n 47u C37 HREF IN2 C19 100n C24 100u 100n C36 HFLY C33 C3 200p +5V R4 1K R5 10K VIN R1 10K HIN R6 10K C8 33p R2 1K R3 10K 36/38 R14 10K Vcc BD677 EW Vcc R17 1K HFLY Vcc 7 NQA 8 GND C4 22p R11 100 R10 100 R9 4K7 R8 4K7 C5 22p +5V R12 560 D1 1N4148 Hout C7 33p Vcc C6 10u R13 1K QB 10 NQB 9 6 QA R15 10K 1B 12 N1B 11 5 N1A GND SCL SDA 5V C11 C10 MC14528 C12 10u 100n VCC16 1 TA1 47p R38 47K C9 2 TA2 TB1 15 47p Delay TB2 14 Vcc 3 CDA Width R16 10K CDB13 4 1A R37 47K Vcc STV2000 Figure 57. STV2000 Demonstration Board Schematics STV2000 PACKAGE MECHANICAL DATA 44-Pin Thin Quad Flat Package D 0.10m m .004 D1 D3 A A2 A1 23 33 22 34 b E3 E1 E 44 12 PIN 1 c IDENTIFICATION 1 11 e L1 L K Dimensions Millimeters Min. Typ. A Inches Max. Min. Typ. 1.60 A1 0.05 A2 1.35 1.40 b 0.30 0.37 c 0.09 0.15 0.002 1.45 0.053 0.055 0.006 0.45 0.012 0.015 0.20 0.004 12.00 0.472 D1 10.00 0.394 D3 8.00 0.315 E 12.00 0.472 E1 10.00 0.394 E3 8.00 0.315 e 0.80 0° L 0.45 L1 0.057 0.018 0.008 D K Max. 0.063 0.031 3.5° 7° 0.60 0.75 0.018 1.00 0.024 0.030 0.039 Number of Pins N 44 37/38 8 STV2000 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this public ation are subject to change witho ut notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2000 STMicroelectronics - All Rights Reserved. Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips. STMicroelectronics Group of Companies Australia - Brazil - China -Finland - France - Germany -Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www .st.com 38/38