TI THS7372IPWR

THS7372
SBOS578 – AUGUST 2011
www.ti.com
4-Channel Video Amplifier with One CVBS and Three Full-HD Filters with 6-dB Gain
Check for Samples: THS7372
FEATURES
DESCRIPTION
• One SDTV Video Amplifier for CVBS Video
• Three Fixed Full-HD 1080p60 Filters for
Y’/P’ B/P’ R, G’B’R’, or Computer RGB Outputs
• Sixth-Order Low-Pass Filters:
– SD Channel: –3 dB at 9.5 MHz
– Fixed Full-HD Channels: –3 dB at 72 MHz
• Versatile Input Biasing:
– DC-Coupled with 300-mV Output Shift
– AC-Coupled with Sync-Tip Clamp or Bias
• Built-in 6-dB Gain (2 V/V)
• +2.7-V to +5-V Single-Supply Operation
• Rail-to-Rail Output:
– Output Swings within 100 mV from the
Rails: Allows AC or DC Output Coupling
– Supports Driving Two Video Lines/Channel
• Low Total Quiescent Current: 23.4 mA at 3.3 V
• Disabled Supply Current Function: 0.1 μA
• Low Differential Gain/Phase: 0.2%/0.35°
• RoHS-Compliant TSSOP-14 Package
Fabricated using the revolutionary, complementary
Silicon-Germanium (SiGe) BiCom3X process, the
THS7372 is a low-power, single-supply, 2.7-V to 5-V,
four-channel integrated video buffer. It incorporates
one SDTV filter and three fixed Full-HD (also known
as True-HD) HDTV filters. All filters feature
sixth-order Butterworth characteristics that are useful
as digital-to-analog converter (DAC) reconstruction
filters or as analog-to-digital converter (ADC)
anti-aliasing filters.
1
2345
The THS7372 has flexible input coupling capabilities,
and can be configured for either ac- or dc-coupled
inputs. The 300-mV output level shift allows for a full
sync dynamic range at the output with 0-V input.
AC-coupled modes include a transparent sync-tip
clamp for CVBS, Y', and G'B'R' signals. AC-coupled
biasing for P'B/P'R channels can easily be achieved
by adding an external resistor to VS+.
The THS7372 is an ideal choice for a wide range of
video buffer applications. Its rail-to-rail output stage
with 6-dB gain allows for both ac and dc line driving.
The ability to drive two lines, or 75-Ω loads, allows for
maximum flexibility as a video line driver. The
23.4-mA total quiescent current at 3.3 V and 0.1 μA
(disabled mode) makes it well-suited for systems that
must meet power-sensitive Energy Star® standards.
APPLICATIONS
•
•
•
Set Top Box Output Video Buffering
PVR/DVDR Output Buffering
BluRay™ Output Video Buffering
The THS7372 is available in a TSSOP-14 package
that is lead-free and green (RoHS-compliant).
THS7372
CVBS
37.4 W
SOC/DAC/Encoder
+2.7 V to
+5 V
Y'/G'
37.4 W
P’B/B'
CVBS Out
75 W
CVBS OUT 14
1
CVBS IN
2
NC
DIS CVBS 13
3
VS+
GND 12
4
NC
5
FHD1 IN
FHD1 OUT 10
6
FHD2 IN
FHD2 OUT
9
7
FHD3 IN
FHD3 OUT
8
DIS FHD 11
Disable
CVBS
Disable
FHD
Y'/G' Out
75 W
P'B/B' Out
75 W
37.4 W
P'R/R' Out
75 W
P’R/R'
37.4 W
Single-Supply, DC-Input/DC-Output Coupled Video Line Driver
1
2
3
4
5
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
BluRay is a trademark of Blu-ray Disc Association (BDA).
Energy Star is a registered trademark of Energy Star.
Macrovision is a registered trademark of Macrovision Corporation.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
THS7372
SBOS578 – AUGUST 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION (1) (2)
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR
PACKAGE
MARKING
TSSOP-14
PW
THS7372
THS7372IPW
THS7372IPWR
(1)
(2)
TRANSPORT
MEDIA, QUANTITY
Rails, 90
Tape and Reel, 2000
ECO STATUS (2)
Pb-Free, Green
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
These packages conform to Lead (Pb)-free and green manufacturing specifications. Additional details including specific material content
can be accessed at www.ti.com/leadfree.
GREEN: TI defines Green to mean Lead (Pb)-Free and in addition, uses less package materials that do not contain halogens, including
bromine (Br), or antimony (Sb) above 0.1% of total product weight. N/A: Not yet available Lead (Pb)-Free; for estimated conversion
dates, go to www.ti.com/leadfree. Pb-FREE: TI defines Lead (Pb)-Free to mean RoHS compatible, including a lead concentration that
does not exceed 0.1% of total product weight, and, if designed to be soldered, suitable for use in specified lead-free soldering
processes.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
Supply voltage, VS+ to GND
Input voltage, VI
Output current, IO
Continuous power dissipation
THS7372
UNIT
5.5
V
–0.4 to VS+
V
±90
mA
See Thermal Information Table
Maximum junction temperature, any condition (2), TJ
+150
°C
Maximum junction temperature, continuous operation, long-term reliability (3), TJ
+125
°C
–60 to +150
°C
Human body model (HBM)
4000
V
Charge device model (CDM)
1000
V
Machine model (MM)
200
V
Storage temperature range, TSTG
ESD rating:
(1)
(2)
(3)
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
The absolute maximum junction temperature under any condition is limited by the constraints of the silicon process.
The absolute maximum junction temperature for continuous operation is limited by the package constraints. Operation above this
temperature may result in reduced reliability and/or lifetime of the device.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
Supply voltage, VS+
2.7
5
V
Ambient temperature, TA
–40
+85
°C
2
Copyright © 2011, Texas Instruments Incorporated
THS7372
SBOS578 – AUGUST 2011
www.ti.com
ELECTRICAL CHARACTERISTICS: VS+ = +3.3 V
At TA = +25°C, RL = 150 Ω to GND, and dc-coupled input/output, unless otherwise noted.
THS7372
PARAMETER
UNITS
TEST
LEVEL (1)
10
MHz
B
11
MHz
B
1.2
dB
B
TEST CONDITIONS
MIN
TYP
MAX
Passband bandwidth
–1 dB; VO = 0.2 VPP and 2 VPP
6.6
8.2
Small- and large-signal bandwidth
–3 dB; VO = 0.2 VPP and 2 VPP
8
9.5
–0.9
0.2
42
54
dB
B
78
ns
C
AC PERFORMANCE: SD (CVBS) CHANNEL
Attenuation
With respect to 500 kHz
, f = 6.75 MHz
With respect to 500 kHz (2), f = 27 MHz
Group delay
Group delay variation
(2)
f = 100 kHz
f = 5.1 MHz with respect to 100 kHz
11
ns
C
0.3
ns
C
NTSC/PAL
0.2/0.35
%
C
NTSC/PAL
0.35/0.5
Channel-to-channel delay
Differential gain
Differential phase
Degrees
C
f = 1 MHz, VO = 1.4 VPP
–69
dB
C
100 kHz to 6 MHz, non-weighted
70
dB
C
100 kHz to 6 MHz, unified weighting
78
dB
C
6.3
dB
A
6.35
dB
B
Ω
C
Total harmonic distortion
Signal-to-noise ratio
Gain
All channels, TA = +25°C
5.7
All channels, TA = –40°C to +85°C
5.65
f = 6.75 MHz
Output impedance
0.7
kΩ || pF
C
f = 6.75 MHz
Disabled
47
dB
C
f = 1 MHz, SD channel to FHD channels
–82
dB
C
Return loss
Crosstalk
6
20 || 3
AC PERFORMANCE: FULL-HD (FHD) CHANNELS
Passband bandwidth
–1 dB; VO = 0.2 VPP and 2 VPP
53
60
66
MHz
B
Small- and large-signal bandwidth
–3 dB; VO = 0.2 VPP and 2 VPP
60
72
83
MHz
B
–0.5
0.6
2
dB
B
33
Attenuation
With respect to 500 kHz (2), f = 54 MHz
With respect to 500 kHz
40
dB
B
f = 100 kHz
12
ns
C
f = 54 MHz with respect to 100 kHz
4.5
ns
C
0.3
ns
C
f = 20 MHz, VO = 1.4 VPP
–54
dB
C
100 kHz to 60 MHz, non-weighted
60
dB
C
Group delay
Group delay variation
(2)
, f = 148 MHz
Channel-to-channel delay
Total harmonic distortion
Signal-to-noise ratio
Gain
100 kHz to 60 MHz, , unified weighting
5.7
All channels, TA = –40°C to +85°C
5.65
f = 60 MHz
Output impedance
Disabled
(1)
(2)
6
4
2 || 3
dB
C
6.3
dB
A
6.35
dB
B
Ω
C
kΩ || pF
C
f = 60 MHz
32
dB
C
f = 6.75 MHz, FHD channels to SD channel
–68
dB
C
f = 25 MHz, FHD to FHD channels
–54
dB
C
Return loss
Crosstalk
70
All channels, TA = +25°C
Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization
and simulation only. (C) Typical value only for information.
3.3-V supply filter specifications are ensured by 100% testing at 5-V supply together with design and characterization.
Copyright © 2011, Texas Instruments Incorporated
3
THS7372
SBOS578 – AUGUST 2011
www.ti.com
ELECTRICAL CHARACTERISTICS: VS+ = +3.3 V (continued)
At TA = +25°C, RL = 150 Ω to GND, and dc-coupled input/output, unless otherwise noted.
THS7372
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
TEST
LEVEL (1)
VIN = 0 V, SD channel
200
305
400
mV
A
VIN = 0 V, FHD channels
200
300
400
mV
A
DC PERFORMANCE
Biased output voltage
Input voltage range
Sync-tip clamp charge current
–0.1/1.46
V
C
VIN = –0.1 V, SD channel
140
200
μA
A
VIN = –0.1 V, FHD channels
280
400
μA
A
kΩ || pF
C
3.15
V
C
3.1
V
A
3.1
V
C
DC input, limited by output
Input impedance
800 || 2
OUTPUT CHARACTERISTICS
RL = 150 Ω to +1.65 V
High output voltage swing
RL = 150 Ω to GND
2.85
RL = 75 Ω to +1.65 V
RL = 75 Ω to GND
Low output voltage swing
3
V
C
RL = 150 Ω to +1.65 V (VIN = –0.2 V)
0.06
V
C
RL = 150 Ω to GND (VIN = –0.2 V)
0.05
V
A
RL = 75 Ω to +1.65 V (VIN = –0.2 V)
0.1
V
C
RL = 75 Ω to GND (VIN = –0.2 V)
0.05
V
C
0.12
Output current (sourcing)
RL = 10 Ω to +1.65 V
80
mA
C
Output current (sinking)
RL = 10 Ω to +1.65 V
70
mA
C
POWER SUPPLY
Operating voltage
Total quiescent current, no load
Power-supply rejection ratio
(PSRR)
2.6
3.3
5.5
V
B
VIN = 0 V, all channels on
18.8
23.4
28.5
mA
A
VIN = 0 V, SD channel on, FHD channels off
5.6
6.9
9
mA
A
VIN = 0 V, SD channel off, FHD channels on
13.2
16.5
19.5
mA
A
VIN = 0 V, all channels off, VDISABLE = 3 V
0.1
10
μA
A
At dc
52
dB
C
V
A
LOGIC CHARACTERISTICS (3)
VIH
Disabled
VIL
Enabled
IIH
Applied voltage = 3.3 V
IIL
Applied voltage = 0 V
1.6
1.4
0.75
0.6
V
A
1
μA
C
1
μA
C
Disable time
200
ns
C
Enable time
250
ns
C
(3)
4
The logic input pins default to a logic '0' condition when left floating.
Copyright © 2011, Texas Instruments Incorporated
THS7372
SBOS578 – AUGUST 2011
www.ti.com
ELECTRICAL CHARACTERISTICS: VS+ = +5 V
At TA = +25°C, RL = 150 Ω to GND, and dc-coupled input/output, unless otherwise noted.
THS7372
PARAMETER
UNITS
TEST
LEVEL (1)
10
MHz
B
11
MHz
B
1.2
dB
A
TEST CONDITIONS
MIN
TYP
MAX
Passband bandwidth
–1 dB; VO = 0.2 VPP and 2 VPP
6.6
8.2
Small- and large-signal bandwidth
–3 dB; VO = 0.2 VPP and 2 VPP
8
9.5
–0.9
0.25
42
54
dB
A
78
ns
C
AC PERFORMANCE: SD (CVBS) CHANNEL
Attenuation
With respect to 500 kHz, f = 6.75 MHz
With respect to 500 kHz, f = 27 MHz
Group delay
Group delay variation
f = 100 kHz
f = 5.1 MHz with respect to 100 kHz
11
ns
C
0.3
ns
C
NTSC/PAL
0.2/0.35
%
C
NTSC/PAL
0.35/0.5
Channel-to-channel delay
Differential gain
Differential phase
Degrees
C
f = 1 MHz, VO = 1.4 VPP
–71
dB
C
100 kHz to 6 MHz, non-weighted
70
dB
C
100 kHz to 6 MHz, unified weighting
78
dB
C
6.3
dB
A
6.35
dB
B
Ω
C
Total harmonic distortion
Signal-to-noise ratio
Gain
All channels, TA = +25°C
5.7
All channels, TA = –40°C to +85°C
5.65
f = 6.75 MHz
Output impedance
0.7
kΩ || pF
C
f = 6.75 MHz
Disabled
47
dB
C
f = 1 MHz, SD channel to FHD channels
–82
dB
C
Return loss
Crosstalk
6
20 || 3
AC PERFORMANCE: FULL-HD (FHD) CHANNELS
Passband bandwidth
–1 dB; VO = 0.2 VPP and 2 VPP
53
60
66
MHz
B
Small- and large-signal bandwidth
–3 dB; VO = 0.2 VPP and 2 VPP
60
72
83
MHz
B
With respect to 500 kHz, f = 54 MHz
–0.5
0.4
2
dB
A
With respect to 500 kHz, f = 148 MHz
33
Attenuation
40
dB
A
f = 100 kHz
12
ns
C
f = 54 MHz with respect to 100 kHz
4.5
ns
C
0.3
ns
C
f = 20 MHz, VO = 1.4 VPP
–50
dB
C
100 kHz to 60 MHz, non-weighted
60
dB
C
Group delay
Group delay variation
Channel-to-channel delay
Total harmonic distortion
Signal-to-noise ratio
Gain
100 kHz to 60 MHz, unified weighting
5.7
All channels, TA = –40°C to +85°C
5.65
f = 60 MHz
Output impedance
6
dB
C
6.3
dB
A
6.35
dB
B
Ω
C
4
kΩ || pF
C
f = 60 MHz
Disabled
32
dB
C
f = 6.75 MHz, FHD channels to SD channel
–68
dB
C
f = 25 MHz, FHD channels to FHD channels
–54
dB
C
A
Return loss
Crosstalk
70
All channels, TA = +25°C
2 || 3
DC PERFORMANCE
Biased output voltage
Input voltage range
Sync-tip clamp charge current
Input impedance
(1)
VIN = 0 V, SD channel
200
VIN = 0 V, FHD channels
200
DC input, limited by output
305
400
mV
300
400
mV
A
–0.1/2.3
V
C
VIN = –0.1 V, SD channel
140
200
μA
A
VIN = –0.1 V, FHD channels
280
400
μA
A
kΩ || pF
C
800 || 2
Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization
and simulation only. (C) Typical value only for information.
Copyright © 2011, Texas Instruments Incorporated
5
THS7372
SBOS578 – AUGUST 2011
www.ti.com
ELECTRICAL CHARACTERISTICS: VS+ = +5 V (continued)
At TA = +25°C, RL = 150 Ω to GND, and dc-coupled input/output, unless otherwise noted.
THS7372
PARAMETER
UNITS
TEST
LEVEL (1)
4.85
V
C
4.75
V
A
RL = 75 Ω to +2.5V
4.7
V
C
RL = 75 Ω to GND
4.5
V
C
RL = 150 Ω to +2.5 V (VIN = –0.2 V)
0.06
V
C
TEST CONDITIONS
MIN
TYP
MAX
OUTPUT CHARACTERISTICS
RL = 150 Ω to +2.5 V
High output voltage swing
Low output voltage swing
RL = 150 Ω to GND
4.4
RL = 150 Ω to GND (VIN = –0.2 V)
0.05
V
A
RL = 75 Ω to +2.5 V (VIN = –0.2 V)
0.1
V
C
RL = 75 Ω to GND (VIN = –0.2 V)
0.05
V
C
0.12
Output current (sourcing)
RL = 10 Ω to +2.5 V
90
mA
C
Output current (sinking)
RL = 10 Ω to +2.5 V
85
mA
C
POWER SUPPLY
Operating voltage
VIN = 0 V, all channels on
Total quiescent current, no load
2.6
5
5.5
V
B
19.7
24.5
30.2
mA
A
VIN = 0 V, SD channel on, FHD channels off
6
7.2
9.5
mA
A
VIN = 0 V, SD channel off, FHD channels on
13.7
17.3
20.7
mA
A
VIN = 0 V, all channels off, VDISABLE = 3 V
1
10
μA
A
At dc
52
dB
C
V
A
Power-supply rejection ratio
(PSRR)
LOGIC CHARACTERISTICS (2)
VIH
Disabled
VIL
Enabled
IIH
Applied voltage = 3.3 V
IIL
Applied voltage = 0 V
2.1
1.9
1.2
1
V
A
1
μA
C
1
μA
C
Disable time
150
ns
C
Enable time
200
ns
C
(2)
The logic input pins default to a logic '0' condition when left floating.
THERMAL INFORMATION
THS7372
THERMAL METRIC (1)
PW
UNITS
14 PINS
θJA
Junction-to-ambient thermal resistance
134.4
θJC (top)
Junction-to-case (top) thermal resistance
52.2
θJB
Junction-to-board thermal resistance
64.3
ψJT
Junction-to-top characterization parameter
7.5
ψJB
Junction-to-board characterization parameter
63.7
θJC (bottom)
Junction-to-case (bottom) thermal resistance
n/a
(1)
6
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2011, Texas Instruments Incorporated
THS7372
SBOS578 – AUGUST 2011
www.ti.com
PIN CONFIGURATION
PW PACKAGE
TSSOP-14
(TOP VIEW)
CVBS IN
1
14 CVBS OUT
NC
2
13 DISABLE CVBS
VS+
3
12 GND
NC
4
11 DISABLE FHD
FHD1 IN
5
10 FHD1 OUT
FHD2 IN
6
9
FHD2 OUT
FHD3 IN
7
8
FHD3 OUT
NC = No connection.
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
I/O
DESCRIPTION
CVBS IN
1
I
Standard-definition video input for CVBS signal; LPF = 9.5 MHz
CVBS OUT
14
O
Standard-definition video output for CVBS signal; LPF = 9.5 MHz
Disable
CVBS
13
I
Disable standard definition channel. Logic high disables the SD channel and logic low enables the
SD channel. This pin defaults to logic low if left open.
Disable FHD
11
I
Disable full high-definition channels. Logic high disables the FHD channels and logic low enables
the FHD channels. This pin defaults to logic low if left open.
FHD1 IN
5
I
Full high-definition video input, channel 1; LPF = 72 MHz
FHD1 OUT
10
O
Full high-definition video output, channel 1; LPF = 72 MHz
FHD2 IN
6
I
Full high-definition video input, channel 2; LPF = 72 MHz
FHD2 OUT
9
O
Full high-definition video output, channel 2; LPF = 72 MHz
FHD3 IN
7
I
Full high-definition video input, channel 3; LPF = 72 MHz
FHD3 OUT
8
O
Full high-definition video output, channel 3; LPF = 72 MHz
GND
12
I
Ground pin for all internal circuitry
NC
2, 4
—
VS+
3
I
No internal connection; it is recommended to connect NC to GND
Positive power-supply pin; connect to +2.7 V up to +5 V
Copyright © 2011, Texas Instruments Incorporated
7
THS7372
SBOS578 – AUGUST 2011
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FUNCTIONAL BLOCK DIAGRAM
+VS
gm
Level
Shift
CVBS
Input
LPF
Sync-Tip Clamp
(DC Restore)
800 kW
6 dB
CVBS
Output
6 dB
FHD Channel 1
Output
6 dB
FHD Channel 2
Output
6 dB
FHD Channel 3
Output
6-Pole
9.5 MHz
+VS
gm
Level
Shift
FHD Channel 1
Input
LPF
Sync-Tip Clamp
(DC Restore)
800 kW
6-Pole
72 MHz
+VS
gm
Level
Shift
FHD Channel 2
Input
LPF
Sync-Tip Clamp
(DC Restore)
800 kW
6-Pole
72 MHz
+VS
gm
Level
Shift
FHD Channel 3
Input
800 kW
Sync-Tip Clamp
(DC Restore)
+2.7 V to +5 V
8
LPF
6-Pole
72 MHz
Disable FHD
Disable CVBS
Copyright © 2011, Texas Instruments Incorporated
THS7372
SBOS578 – AUGUST 2011
www.ti.com
TYPICAL CHARACTERISTICS
Table 1. Table of Graphs: 3.3 V, Standard-Definition (SD) Channels
TITLE
FIGURE
Figure 1, Figure 2, Figure 9,
Figure 10, Figure 11, Figure 12,
Figure 13
SD Small-Signal Gain vs Frequency
SD Phase vs Frequency
Figure 3
SD Group Delay vs Frequency
Figure 4
SD Differential Gain
Figure 5
SD Differential Phase
Figure 6
SD Large-Signal Gain vs Frequency
Figure 7, Figure 8
SD THD vs Frequency
Figure 14
SD Large-Signal Pulse Response vs Time
Figure 15
SD Small-Signal Pulse Response vs Time
Figure 16
SD Slew Rate vs Output Voltage
Figure 17
SD Enable/Disable Response vs Time
Figure 18
Table 2. Table of Graphs: 3.3 V, Full HD (FHD) Channels
TITLE
FHD Small-Signal Gain vs Frequency
FHD Phase vs Frequency
FHD Group Delay vs Frequency
FHD Large-Signal Gain vs Frequency
FIGURE
Figure 19, Figure 20, Figure 25,
Figure 26, Figure 27, Figure 28,
Figure 29
Figure 21
Figure 22
Figure 23, Figure 24
FHD THD vs Frequency
Figure 30
FHD Large-Signal Pulse Response vs Time
Figure 31
FHD Small-Signal Pulse Response vs Time
Figure 32
FHD Slew Rate vs Output Voltage
Figure 33
FHD Enable/Disable Response vs Time
Figure 34
FHD Crosstalk
Figure 35
FHD to SD Crosstalk
Figure 36
SD to FHD Crosstalk
Figure 37
Copyright © 2011, Texas Instruments Incorporated
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THS7372
SBOS578 – AUGUST 2011
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Table 3. Table of Graphs: 5 V, Standard-Definition (SD) Channels
TITLE
FIGURE
Figure 38, Figure 39, Figure 46,
Figure 47, Figure 48, Figure 49,
Figure 50
SD Small-Signal Gain vs Frequency
SD Phase vs Frequency
Figure 40
SD Group Delay vs Frequency
Figure 41
SD Differential Gain
Figure 42
SD Differential Phase
Figure 43
SD Large-Signal Gain vs Frequency
Figure 44, Figure 45
SD THD vs Frequency
Figure 51
SD Large-Signal Pulse Response vs Time
Figure 52
SD Small-Signal Pulse Response vs Time
Figure 53
SD Slew Rate vs Output Voltage
Figure 54
SD Enable/Disable Response vs Time
Figure 55
Table 4. Table of Graphs: 5 V, Full HD (FHD) Channels
TITLE
FHD Small-Signal Gain vs Frequency
FIGURE
Figure 56, Figure 57, Figure 58,
Figure 59, Figure 60, Figure 61,
Figure 62
FHD Phase vs Frequency
Figure 63
FHD Group Delay vs Frequency
Figure 64
FHD Large-Signal Gain vs Frequency
Figure 65, Figure 66
FHD Slew Rate vs Output Voltage
Figure 67
FHD THD vs Frequency
Figure 68
FHD Large-Signal Pulse Response vs Time
Figure 69
FHD Small-Signal Pulse Response vs Time
Figure 70
FHD Enable/Disable Response vs Time
Figure 71
FHD Crosstalk
Figure 72
FHD to SD Crosstalk
Figure 73
SD to FHD Crosstalk
Figure 74
10
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Table 5. Table of Graphs: General Standard-Definition (SD) Channels
TITLE
FIGURE
SD Output Impedance vs Frequency
Figure 75
SD S22 Output Return Loss vs Frequency
Figure 76
SD Disabled Output Impedance vs Frequency
Figure 77
SD PSRR vs Frequency
Figure 78
Table 6. Table of Graphs: General Full HD (FHD) Channels
TITLE
FIGURE
FHD Output Impedance vs Frequency
Figure 79
FHD S22 Output Return Loss vs Frequency
Figure 80
FHD Disabled Output Impedance vs Frequency
Figure 81
FHD PSRR vs Frequency
Figure 82
Copyright © 2011, Texas Instruments Incorporated
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TYPICAL CHARACTERISTICS: 3.3 V, Standard-Definition (SD) Channels
With load = 150 Ω || 10 pF, dc-coupled input and output, unless otherwise noted.
SD SMALL-SIGNAL GAIN vs FREQUENCY
10
SD SMALL-SIGNAL GAIN vs FREQUENCY
6.5
RL = 150 Ω
RL = 75 Ω
0
5.5
Gain (dB)
Gain (dB)
−10
−20
−30
−40
−50
RL = 150 Ω
RL = 75 Ω
6
VS+ = 3.3 V
Load = RL || 10 pF
VOUT = 200 mVPP
Input Bias = 0.65 VDC
DC−Coupled Output
−60
100k
1M
5
4.5
4
3.5
3
10M
Frequency (Hz)
100M
VS+ = 3.3 V
Load = RL || 10 pF
VOUT = 200 mVPP
Input Bias = 0.65 VDC
DC−Coupled Output
2.5
100k
1G
1M
Figure 1.
SD PHASE vs FREQUENCY
SD GROUP DELAY vs FREQUENCY
130
RL = 150 Ω
RL = 75 Ω
0
120
Group Delay (ns)
−45
Phase (°)
−90
−135
−180
−270
−315
VS+ = 3.3 V
Load = RL || 10 pF
VOUT = 200 mVPP
Input Bias = 0.65 VDC
DC−Coupled Output
−360
100k
110
90
80
70
1M
10M
60
100k
100M
1M
Frequency (Hz)
Figure 3.
Figure 4.
100M
SD DIFFERENTIAL PHASE
0.5
0
0.45
VS+ = 3.3 V
0.4
-0.05
Differential Phase (°)
Differential Gain (%)
10M
Frequency (Hz)
SD DIFFERENTIAL GAIN
12
RL = 150 Ω
RL = 75 Ω
VS+ = 3.3 V
Load = RL || 10 pF
VOUT = 200 mVPP
Input Bias = 0.65 VDC
DC−Coupled Output
100
0.05
NTSC
-0.1
-0.15
-0.2
PAL
-0.25
0.35
0.25
NTSC
0.2
0.15
0.1
-0.35
0.05
VS+ = 3.3 V
PAL
0.3
-0.3
-0.4
100M
Figure 2.
45
−225
10M
Frequency (Hz)
0
1st
2nd
4th
3rd
5th
6th
1st
2nd
4th
3rd
Steps
Steps
Figure 5.
Figure 6.
5th
6th
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TYPICAL CHARACTERISTICS: 3.3 V, Standard-Definition (SD) Channels (continued)
With load = 150 Ω || 10 pF, dc-coupled input and output, unless otherwise noted.
SD LARGE-SIGNAL GAIN vs FREQUENCY
SD LARGE-SIGNAL GAIN vs FREQUENCY
6.5
10
VOUT = 200 mVPP
VOUT = 2 VPP
0
6
5.5
Gain (dB)
Gain (dB)
−10
−20
−30
−40
−50
VS+ = 3.3 V
Load = 150 Ω || 10 pF
Input Bias = 0.65 VDC
DC−Coupled Output
−60
100k
1M
10M
Frequency (MHz)
4.5
4
3.5
3
100M
VOUT = 200 mVPP
VOUT = 2 VPP
5
VS+ = 3.3 V
Load = 150 Ω || 10 pF
Input Bias = 0.65 VDC
DC−Coupled Output
2.5
100k
1G
1M
10M
Frequency (MHz)
Figure 7.
Figure 8.
SD SMALL-SIGNAL GAIN vs FREQUENCY
SD SMALL-SIGNAL GAIN vs FREQUENCY
6.5
10
DC−Coupled Output
AC−Coupled Output
0
6
5.5
Gain (dB)
Gain (dB)
−10
−20
−30
−40
−50
VS+ = 3.3 V
Load = 150 Ω || 10 pF
VOUT = 200 mVPP
Input Bias = 0.65 VDC
−60
100k
1M
10M
Frequency (Hz)
4.5
4
3.5
3
100M
DC−Coupled Output
AC−Coupled Output
5
VS+ = 3.3 V
Load = 150 Ω || 10 pF
VOUT = 200 mVPP
Input Bias = 0.65 VDC
2.5
100k
1G
1M
SD SMALL-SIGNAL GAIN vs FREQUENCY
SD SMALL-SIGNAL GAIN vs FREQUENCY
6.5
TA = −40°C
TA = 25°C
TA = 85°C
0
6
5.5
Gain (dB)
−10
Gain (dB)
100M
Figure 10.
10
−20
−30
−50
10M
Frequency (Hz)
Figure 9.
−40
100M
VS+ = 3.3 V
Load = 150 Ω || 10 pF
VOUT = 200 mVPP
Input Bias = 0.65 VDC
DC−Coupled Output
−60
100k
1M
10M
Frequency (Hz)
Figure 11.
Copyright © 2011, Texas Instruments Incorporated
4.5
4
3.5
3
100M
1G
TA = −40°C
TA = 25°C
TA = 85°C
5
VS+ = 3.3 V
Load = 150 Ω || 10 pF
VOUT = 200 mVPP
Input Bias = 0.65 VDC
DC−Coupled Output
2.5
100k
1M
10M
100M
Frequency (Hz)
Figure 12.
13
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SBOS578 – AUGUST 2011
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TYPICAL CHARACTERISTICS: 3.3 V, Standard-Definition (SD) Channels (continued)
With load = 150 Ω || 10 pF, dc-coupled input and output, unless otherwise noted.
SD SMALL-SIGNAL GAIN vs FREQUENCY
SD THD vs FREQUENCY
−30
CL = 5 pF
CL = 10 pF
CL = 18 pF
0
Gain (dB)
−10
−20
−30
−40
VS+ = 3.3 V
Load = 150 Ω || CL
Input Bias = 0.65 VDC
DC−Coupled Output
−50
−60
100k
1M
Total Harmonic Distortion (dBc)
10
−40
−50
VOUT = 0.5 VPP
VOUT = 1 VPP
VOUT = 1.4 VPP
VOUT = 2 VPP
VOUT = 2.5 VPP
−60
−70
VS+ = 3.3 V
Input Bias = 0.65 VDC
DC−Coupled Output
−80
−90
1M
10M
Frequency (MHz)
100M
1G
8M
Frequency (Hz)
Figure 13.
Figure 14.
SD LARGE-SIGNAL PULSE RESPONSE vs TIME
SD SMALL-SIGNAL PULSE RESPONSE vs TIME
Figure 15.
Figure 16.
SD SLEW RATE vs OUTPUT VOLTAGE
SD ENABLE/DISABLE RESPONSE vs TIME
G002
60
Slew Rate (V/µs)
50
VS+ = 3.3 V
Positive and Negative Slew Rates
40
30
20
10
0
0.5
1
1.5
2
2.5
Output Voltage (VPP)
Figure 17.
14
Figure 18.
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TYPICAL CHARACTERISTICS: 3.3 V, Full HD (FHD) Channels
With load = 150 Ω || 5 pF, dc-coupled input and output, unless otherwise noted.
FHD SMALL-SIGNAL GAIN vs FREQUENCY
10
FHD SMALL-SIGNAL GAIN vs FREQUENCY
6.5
RL = 150 Ω
RL = 75 Ω
0
6
5.5
Gain (dB)
Gain (dB)
−10
−20
−30
−40
−50
−60
1M
VS+ = 3.3 V
Load = RL || 5 pF
VOUT = 200 mVPP
Input Bias = 0.65 VDC
DC−Coupled Output
10M
5
4.5
4
3.5
3
100M
Frequency (Hz)
10M
Frequency (Hz)
100M
Figure 20.
FHD PHASE vs FREQUENCY
FHD GROUP DELAY vs FREQUENCY
20
RL = 150 Ω
RL = 75 Ω
0
VS+ = 3.3 V
Load = RL || 5 pF
VOUT = 200 mVPP
Input Bias = 0.65 VDC
DC−Coupled Output
2.5
1M
1G
Figure 19.
45
RL = 150 Ω
RL = 75 Ω
RL = 150 Ω
RL = 75 Ω
18
Group Delay (ns)
−45
Phase (°)
−90
−135
−180
−225
−270
−315
−360
1M
VS+ = 3.3 V
Load = RL || 5 pF
VOUT = 200 mVPP
Input Bias = 0.65 VDC
DC−Coupled Output
10M
100M
Frequency (Hz)
16
14
12
10
8
6
1M
1G
Figure 21.
FHD LARGE-SIGNAL GAIN vs FREQUENCY
0
6
Gain (dB)
Gain (dB)
VOUT = 200 mVPP
VOUT = 2 VPP
−30
−60
1M
1G
5.5
−10
−50
100M
Frequency (Hz)
FHD LARGE-SIGNAL GAIN vs FREQUENCY
6.5
−40
10M
Figure 22.
10
−20
VS+ = 3.3 V
Load = RL || 5 pF
VOUT = 200 mVPP
Input Bias = 0.65 VDC
DC−Coupled Output
VS+ = 3.3 V
Load = 150 Ω || 5 pF
Input Bias = 0.65 VDC
DC−Coupled Output
10M
100M
Frequency (MHz)
Figure 23.
Copyright © 2011, Texas Instruments Incorporated
5
4.5
4
3.5
3
1G
VOUT = 200 mVPP
VOUT = 2 VPP
2.5
1M
VS+ = 3.3 V
Load = 150 Ω || 5 pF
Input Bias = 0.65 VDC
DC−Coupled Output
10M
Frequency (MHz)
100M
Figure 24.
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TYPICAL CHARACTERISTICS: 3.3 V, Full HD (FHD) Channels (continued)
With load = 150 Ω || 5 pF, dc-coupled input and output, unless otherwise noted.
FHD SMALL-SIGNAL GAIN vs FREQUENCY
FHD SMALL-SIGNAL GAIN vs FREQUENCY
10
6.5
0
6
5.5
−20
DC−Coupled Output
AC−Coupled Output
Gain (dB)
Gain (dB)
−10
−30
−40
−50
−60
1M
VS+ = 3.3 V
Load = 150 Ω || 5 pF
VOUT = 200 mVPP
Input Bias = 0.65 VDC
10M
4.5
4
3.5
3
100M
Frequency (Hz)
DC−Coupled Output
AC−Coupled Output
5
VS+ = 3.3 V
Load = 150 Ω || 5 pF
VOUT = 200 mVPP
Input Bias = 0.65 VDC
2.5
1M
1G
10M
Frequency (Hz)
Figure 25.
Figure 26.
FHD SMALL-SIGNAL GAIN vs FREQUENCY
FHD SMALL-SIGNAL GAIN vs FREQUENCY
6.5
10
TA = −40°C
TA = 25°C
TA = 85°C
0
6
5.5
Gain (dB)
Gain (dB)
−10
−20
−30
−40
−50
−60
1M
VS+ = 3.3 V
Load = 150 Ω || 5 pF
VOUT = 200 mVPP
Input Bias = 0.65 VDC
DC−Coupled Output
10M
4.5
4
3.5
3
100M
Frequency (Hz)
TA = −40°C
TA = 25°C
TA = 85°C
5
VS+ = 3.3 V
Load = 150 Ω || 5 pF
VOUT = 200 mVPP
Input Bias = 0.65 VDC
DC−Coupled Output
2.5
1M
1G
Figure 27.
FHD SMALL-SIGNAL GAIN vs FREQUENCY
FHD THD vs FREQUENCY
Gain (dB)
−20
−30
VS+ = 3.3 V
Load = 150 Ω || CL
Input Bias = 0.65 VDC
DC−Coupled Output
10M
100M
Frequency (MHz)
Figure 29.
16
Total Harmonic Distortion (dBc)
CL = 5 pF
CL = 10 pF
CL = 18 pF
−10
−60
1M
100M
−30
0
−50
10M
Frequency (Hz)
Figure 28.
10
−40
100M
−40
−50
−60
−70
VS+ = 3.3 V
Input Bias = 0.65 VDC
DC−Coupled Output
−80
−90
1M
1G
VOUT = 0.5 VPP
VOUT = 1 VPP
VOUT = 1.4 VPP
VOUT = 2 VPP
VOUT = 2.5 VPP
10M
Frequency (Hz)
60M
G000
Figure 30.
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SBOS578 – AUGUST 2011
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TYPICAL CHARACTERISTICS: 3.3 V, Full HD (FHD) Channels (continued)
With load = 150 Ω || 5 pF, dc-coupled input and output, unless otherwise noted.
FHD LARGE-SIGNAL PULSE RESPONSE vs TIME
FHD SMALL-SIGNAL PULSE RESPONSE vs TIME
Figure 31.
Figure 32.
FHD SLEW RATE vs OUTPUT VOLTAGE
FHD ENABLE/DISABLE RESPONSE vs TIME
350
Slew Rate (V/µs)
300
VS+ = 3.3 V
Positive and Negative Slew Rates
250
200
150
100
50
0
0.5
1
1.5
2
2.5
Output Voltage (VPP)
Figure 33.
Figure 34.
FHD CROSSTALK
FHD TO SD CROSSTALK (1)
−30
−50
VS+ = 3.3 V
−40
Crosstalk (dB)
Crosstalk (dB)
−40
−30
FHD1 into FHD2
FHD1 into FHD3
FHD2 into FHD1
FHD2 into FHD3
FHD3 into FHD1
FHD3 into FHD2
−60
−70
−80
−90
1M
−50
−60
−70
−80
10M
Frequency (Hz)
100M
−90
1M
Figure 35.
(1)
VS+ = 3.3 V
FHD1 into SD
FHD2 into SD
FHD3 into SD
10M
Frequency (Hz)
100M
Figure 36.
Measured at victim-channel output connector relative to aggressor-channel output connector.
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TYPICAL CHARACTERISTICS: 3.3 V, Full HD (FHD) Channels (continued)
With load = 150 Ω || 5 pF, dc-coupled input and output, unless otherwise noted.
SD TO FHD CROSSTALK (2)
−40
Crosstalk (dB)
−50
VS+ = 3.3 V
SD into FHD1
SD into FHD2
SD into FHD3
−60
−70
−80
−90
−100
1M
10M
Frequency (Hz)
100M
Figure 37.
(2)
18
Measured at victim-channel output connector relative to aggressor-channel output connector.
Copyright © 2011, Texas Instruments Incorporated
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TYPICAL CHARACTERISTICS: 5 V, Standard-Definition (SD) Channels
With load = 150 Ω || 10 pF, dc-coupled input and output, unless otherwise noted.
SD SMALL-SIGNAL GAIN vs FREQUENCY
10
SD SMALL-SIGNAL GAIN vs FREQUENCY
6.5
RL = 150 Ω
RL = 75 Ω
0
5.5
Gain (dB)
Gain (dB)
−10
−20
−30
−40
−50
RL = 150 Ω
RL = 75 Ω
6
VS+ = 5 V
Load = RL || 10 pF
VOUT = 200 mVPP
Input Bias = 1 VDC
DC−Coupled Output
−60
100k
1M
5
4.5
4
3.5
3
10M
Frequency (Hz)
100M
VS+ = 5 V
Load = RL || 10 pF
VOUT = 200 mVPP
Input Bias = 1 VDC
DC−Coupled Output
2.5
100k
1G
1M
Figure 38.
SD PHASE vs FREQUENCY
SD GROUP DELAY vs FREQUENCY
130
RL = 150 Ω
RL = 75 Ω
0
120
Group Delay (ns)
−45
Phase (°)
−90
−135
−180
−270
−315
VS+ = 5 V
Load = RL || 10 pF
VOUT = 200 mVPP
Input Bias = 1 VDC
DC−Coupled Output
−360
100k
110
100
90
80
1M
10M
60
100k
100M
1M
10M
Frequency (Hz)
Frequency (Hz)
Figure 40.
Figure 41.
SD DIFFERENTIAL GAIN
100M
SD DIFFERENTIAL PHASE
0.6
0
VS+ = 5 V
0.5
-0.05
Differential Phase (°)
Differential Gain (%)
RL = 150 Ω
RL = 75 Ω
VS+ = 5 V
Load = RL || 10 pF
VOUT = 200 mVPP
Input Bias = 1 VDC
DC−Coupled Output
70
0.05
NTSC
-0.1
-0.15
-0.2
PAL
-0.25
0.4
PAL
0.3
NTSC
0.2
0.1
-0.3
-0.35
100M
Figure 39.
45
−225
10M
Frequency (Hz)
VS+ = 5 V
1st
0
2nd
4th
3rd
5th
6th
1st
2nd
4th
3rd
Steps
Steps
Figure 42.
Figure 43.
Copyright © 2011, Texas Instruments Incorporated
5th
6th
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TYPICAL CHARACTERISTICS: 5 V, Standard-Definition (SD) Channels (continued)
With load = 150 Ω || 10 pF, dc-coupled input and output, unless otherwise noted.
SD LARGE-SIGNAL GAIN vs FREQUENCY
SD LARGE-SIGNAL GAIN vs FREQUENCY
6.5
10
VOUT = 200 mVPP
VOUT = 2 VPP
0
6
5.5
Gain (dB)
Gain (dB)
−10
−20
−30
−40
−50
VS+ = 5 V
Load = 150 Ω || 10 pF
Input Bias = 1 VDC
DC−Coupled Output
−60
100k
1M
10M
Frequency (MHz)
4.5
4
3.5
3
100M
VOUT = 200 mVPP
VOUT = 2 VPP
5
VS+ = 5 V
Load = 150 Ω || 10 pF
Input Bias = 1 VDC
DC−Coupled Output
2.5
100k
1G
1M
10M
Frequency (MHz)
Figure 44.
Figure 45.
SD SMALL-SIGNAL GAIN vs FREQUENCY
SD SMALL-SIGNAL GAIN vs FREQUENCY
6.5
10
DC−Coupled Output
AC−Coupled Output
0
6
5.5
Gain (dB)
Gain (dB)
−10
−20
−30
−40
−50
VS+ = 5 V
Load = 150 Ω || 10 pF
VOUT = 200 mVPP
Input Bias = 1 VDC
−60
100k
1M
10M
Frequency (Hz)
4.5
4
3.5
3
100M
DC−Coupled Output
AC−Coupled Output
5
VS+ = 5 V
Load = 150 Ω || 10 pF
VOUT = 200 mVPP
Input Bias = 1 VDC
2.5
100k
1G
1M
SD SMALL-SIGNAL GAIN vs FREQUENCY
SD SMALL-SIGNAL GAIN vs FREQUENCY
6.5
TA = −40°C
TA = 25°C
TA = 85°C
0
6
5.5
Gain (dB)
Gain (dB)
−10
−20
−30
VS+ = 5 V
Load = 150 Ω || 10 pF
VOUT = 200 mVPP
Input Bias = 1 VDC
DC−Coupled Output
−60
100k
1M
10M
Frequency (Hz)
Figure 48.
20
100M
Figure 47.
10
−50
10M
Frequency (Hz)
Figure 46.
−40
100M
4.5
4
3.5
3
100M
1G
TA = −40°C
TA = 25°C
TA = 85°C
5
VS+ = 5 V
Load = 150 Ω || 10 pF
VOUT = 200 mVPP
Input Bias = 1 VDC
DC−Coupled Output
2.5
100k
1M
10M
100M
Frequency (Hz)
Figure 49.
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TYPICAL CHARACTERISTICS: 5 V, Standard-Definition (SD) Channels (continued)
With load = 150 Ω || 10 pF, dc-coupled input and output, unless otherwise noted.
SD SMALL-SIGNAL GAIN vs FREQUENCY
SD THD vs FREQUENCY
−30
10
Total Harmonic Distortion (dBc)
CL = 5 pF
CL = 10 pF
CL = 18 pF
0
Gain (dB)
−10
−20
−30
−40
VS+ = 5 V
Load = 150 Ω || CL
Input Bias = 1 VDC
DC−Coupled Output
−50
−60
100k
1M
−40
−50
VOUT = 0.5 VPP
VOUT = 1 VPP
VOUT = 1.4 VPP
VOUT = 2 VPP
VOUT = 3 VPP
−60
−70
VS+ = 5 V
Input Bias = 1 VDC
DC−Coupled Output
−80
−90
1M
10M
Frequency (MHz)
100M
1G
8M
Frequency (Hz)
Figure 50.
Figure 51.
SD LARGE-SIGNAL PULSE RESPONSE vs TIME
SD SMALL-SIGNAL PULSE RESPONSE vs TIME
Figure 52.
Figure 53.
SD SLEW RATE vs OUTPUT VOLTAGE
SD ENABLE/DISABLE RESPONSE vs TIME
G003
80
VS+ = 5 V
Positive and Negative Slew Rates
Slew Rate (V/µs)
60
40
20
0
0.5
1
1.5
2
2.5
3
3.5
4
Output Voltage (VPP)
Figure 54.
Copyright © 2011, Texas Instruments Incorporated
Figure 55.
21
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TYPICAL CHARACTERISTICS: 5 V, Full HD (FHD) Channels
With load = 150 Ω || 5 pF, dc-coupled input and output, unless otherwise noted.
FHD SMALL-SIGNAL GAIN vs FREQUENCY
FHD SMALL-SIGNAL GAIN vs FREQUENCY
10
6.5
0
6
5.5
−20
DC−Coupled Output
AC−Coupled Output
Gain (dB)
Gain (dB)
−10
−30
−40
−50
−60
1M
VS+ = 5 V
Load = 150 Ω || 5 pF
VOUT = 200 mVPP
Input Bias = 1 VDC
10M
5
4.5
4
3.5
3
100M
Frequency (Hz)
DC−Coupled Output
AC−Coupled Output
VS+ = 5 V
Load = 150 Ω || 5 pF
VOUT = 200 mVPP
Input Bias = 1 VDC
2.5
1M
1G
10M
Frequency (Hz)
Figure 56.
Figure 57.
FHD SMALL-SIGNAL GAIN vs FREQUENCY
FHD SMALL-SIGNAL GAIN vs FREQUENCY
10
10
CL = 5 pF
CL = 10 pF
CL = 18 pF
0
Gain (dB)
Gain (dB)
−10
−20
−30
−50
−60
1M
−20
−30
−40
VS+ = 5 V
Load = 150 Ω || CL
Input Bias = 1 VDC
DC−Coupled Output
−50
10M
100M
Frequency (MHz)
−60
1M
1G
Figure 58.
FHD SMALL-SIGNAL GAIN vs FREQUENCY
6
0
Gain (dB)
Gain (dB)
4
3
2.5
1M
VS+ = 5 V
Load = RL || 5 pF
VOUT = 200 mVPP
Input Bias = 1 VDC
DC−Coupled Output
1G
TA = −40°C
TA = 25°C
TA = 85°C
−20
−30
−40
−50
10M
Frequency (Hz)
Figure 60.
22
100M
Frequency (Hz)
−10
RL = 150 Ω
RL = 75 Ω
4.5
3.5
10M
FHD SMALL-SIGNAL GAIN vs FREQUENCY
10
5
VS+ = 5 V
Load = RL || 5 pF
VOUT = 200 mVPP
Input Bias = 1 VDC
DC−Coupled Output
Figure 59.
6.5
5.5
RL = 150 Ω
RL = 75 Ω
0
−10
−40
100M
100M
−60
1M
VS+ = 5 V
Load = 150 Ω || 5 pF
VOUT = 200 mVPP
Input Bias = 1 VDC
DC−Coupled Output
10M
100M
Frequency (Hz)
1G
Figure 61.
Copyright © 2011, Texas Instruments Incorporated
THS7372
SBOS578 – AUGUST 2011
www.ti.com
TYPICAL CHARACTERISTICS: 5 V, Full HD (FHD) Channels (continued)
With load = 150 Ω || 5 pF, dc-coupled input and output, unless otherwise noted.
FHD SMALL-SIGNAL GAIN vs FREQUENCY
FHD PHASE vs FREQUENCY
6.5
45
6
0
−45
TA = −40°C
TA = 25°C
TA = 85°C
−90
Phase (°)
Gain (dB)
5.5
5
4.5
4
3.5
3
RL = 150 Ω
RL = 75 Ω
−180
−225
VS+ = 5 V
Load = 150 Ω || 5 pF
VOUT = 200 mVPP
Input Bias = 1 VDC
DC−Coupled Output
2.5
1M
−135
−270
−315
10M
Frequency (Hz)
VS+ = 5 V
Load = RL || 5 pF
VOUT = 200 mVPP
Input Bias = 1 VDC
DC−Coupled Output
−360
1M
100M
10M
Figure 62.
0
16
−10
Gain (dB)
Group Delay (ns)
FHD LARGE-SIGNAL GAIN vs FREQUENCY
10
RL = 150 Ω
RL = 75 Ω
18
14
12
10
8
6
1M
VS+ = 5 V
Load = RL || 5 pF
VOUT = 200 mVPP
Input Bias = 1 VDC
DC−Coupled Output
−20
−30
−40
−50
10M
100M
Frequency (Hz)
VOUT = 200 mVPP
VOUT = 2 VPP
VS+ = 5 V
Load = 150 Ω || 5 pF
Input Bias = 1 VDC
DC−Coupled Output
−60
1M
1G
10M
100M
Frequency (MHz)
Figure 64.
FHD LARGE-SIGNAL GAIN vs FREQUENCY
FHD SLEW RATE vs OUTPUT VOLTAGE
450
6
400
Slew Rate (V/µs)
Gain (dB)
VOUT = 200 mVPP
VOUT = 2 VPP
4.5
4
3
2.5
1M
VS+ = 5 V
Positive and Negative Slew Rates
350
5.5
3.5
1G
Figure 65.
6.5
5
1G
Figure 63.
FHD GROUP DELAY vs FREQUENCY
20
100M
Frequency (Hz)
VS+ = 5 V
Load = 150 Ω || 5 pF
Input Bias = 1 VDC
DC−Coupled Output
10M
Frequency (MHz)
Figure 66.
Copyright © 2011, Texas Instruments Incorporated
300
250
200
150
100
50
100M
0
0.5
1
1.5
2
2.5
3
3.5
4
Output Voltage (VPP)
Figure 67.
23
THS7372
SBOS578 – AUGUST 2011
www.ti.com
TYPICAL CHARACTERISTICS: 5 V, Full HD (FHD) Channels (continued)
With load = 150 Ω || 5 pF, dc-coupled input and output, unless otherwise noted.
FHD THD vs FREQUENCY
FHD LARGE-SIGNAL PULSE RESPONSE vs TIME
Total Harmonic Distortion (dBc)
−30
−40
−50
VOUT = 0.5 VPP
VOUT = 1 VPP
VOUT = 1.4 VPP
VOUT = 2 VPP
VOUT = 3 VPP
−60
−70
VS+ = 5 V
Input Bias = 1 VDC
DC−Coupled Output
−80
−90
1M
10M
Frequency (Hz)
60M
G001
Figure 68.
Figure 69.
FHD SMALL-SIGNAL PULSE RESPONSE vs TIME
FHD ENABLE/DISABLE RESPONSE vs TIME
Figure 70.
Figure 71.
FHD CROSSTALK
FHD TO SD CROSSTALK (1)
−30
−50
VS+ = 5 V
−40
Crosstalk (dB)
Crosstalk (dB)
−40
−30
FHD1 into FHD2
FHD1 into FHD3
FHD2 into FHD1
FHD2 into FHD3
FHD3 into FHD1
FHD3 into FHD2
−60
−70
−80
−90
1M
−50
−60
−70
−80
10M
Frequency (Hz)
100M
−90
1M
10M
Frequency (Hz)
Figure 72.
(1)
24
VS+ = 5 V
FHD1 into SD
FHD2 into SD
FHD3 into SD
100M
Figure 73.
Measured at victim-channel output connector relative to aggressor-channel output connector.
Copyright © 2011, Texas Instruments Incorporated
THS7372
SBOS578 – AUGUST 2011
www.ti.com
TYPICAL CHARACTERISTICS: 5 V, Full HD (FHD) Channels (continued)
With load = 150 Ω || 5 pF, dc-coupled input and output, unless otherwise noted.
SD TO FHD CROSSTALK (2)
−40
Crosstalk (dB)
−50
VS+ = 5 V
SD into FHD1
SD into FHD2
SD into FHD3
−60
−70
−80
−90
−100
1M
10M
Frequency (Hz)
100M
Figure 74.
(2)
Measured at victim-channel output connector relative to aggressor-channel output connector.
Copyright © 2011, Texas Instruments Incorporated
25
THS7372
SBOS578 – AUGUST 2011
www.ti.com
TYPICAL CHARACTERISTICS: General Standard-Definition (SD) Channels
With load = 150 Ω || 10 pF, dc-coupled input and output, unless otherwise noted.
SD OUTPUT IMPEDANCE vs FREQUENCY
SD S22 OUTPUT RETURN LOSS vs FREQUENCY
10
−20
−25
S22, Output Return Loss (dB)
Output Impedance (Ω)
VS+ = 3.3 V to 5 V
1
0.1
VS+ = 3.3 V to 5 V
−30
−35
−40
−45
−50
−55
−60
−65
0.01
100k
1M
10M
−70
100k
100M
Figure 75.
Figure 76.
SD DISABLED OUTPUT IMPEDANCE vs FREQUENCY
100M
SD PSRR vs FREQUENCY
70
VS+ = 3.3 V to 5 V
Power−Supply Rejection Ratio (dB)
VS+ = 3.3 V to 5 V
Disable Mode
Output Impedance (kΩ)
10M
Frequency (Hz)
100
10
1
0.1
100k
26
1M
Frequency (Hz)
1M
10M
100M
60
50
40
30
20
10
0
10k
Frequency (Hz)
100k
1M
Frequency (Hz)
Figure 77.
Figure 78.
10M
100M
Copyright © 2011, Texas Instruments Incorporated
THS7372
SBOS578 – AUGUST 2011
www.ti.com
TYPICAL CHARACTERISTICS: General Full HD (FHD) Channels
With load = 150 Ω || 5 pF, dc-coupled input and output, unless otherwise noted.
FHD OUTPUT IMPEDANCE vs FREQUENCY
FHD S22 OUTPUT RETURN LOSS vs FREQUENCY
10
−20
−25
S22, Output Return Loss (dB)
Output Impedance (Ω)
VS+ = 3.3 V to 5 V
1
0.1
VS+ = 3.3 V to 5 V
−30
−35
−40
−45
−50
−55
−60
−65
0.01
100k
1M
10M
−70
100k
100M
10M
Frequency (Hz)
Figure 79.
Figure 80.
FHD DISABLED OUTPUT IMPEDANCE vs FREQUENCY
100M
FHD PSRR vs FREQUENCY
10
70
VS+ = 3.3 V to 5 V
Power−Supply Rejection Ratio (dB)
VS+ = 3.3 V to 5 V
Disable Mode
Output Impedance (kΩ)
1M
Frequency (Hz)
1
0.1
100k
1M
10M
100M
60
50
40
30
20
10
0
10k
Frequency (Hz)
1M
Frequency (Hz)
Figure 81.
Figure 82.
Copyright © 2011, Texas Instruments Incorporated
100k
10M
100M
27
THS7372
SBOS578 – AUGUST 2011
www.ti.com
APPLICATION INFORMATION
The THS7372 is targeted for four-channel video output applications that require one standard-definition (SD)
video output buffer and three full-high definition (FHD) video output buffers. Although it can be used for
numerous other applications, the needs and requirements of the video signal are the most important design
parameters of the THS7372. Built on the revolutionary, complementary Silicon Germanium (SiGe) BiCom3X
process, the THS7372 incorporates many features not typically found in integrated video parts while consuming
very low power. The THS7372 includes the following features:
• Single-supply 2.7-V to 5-V operation with low total quiescent current of 23.4 mA at 3.3 V and
24.5 mA at 5 V
• Disable mode allows for shutting down individual SD/FHD blocks of amplifiers to save system power in
power-sensitive applications
• Input configuration accepting dc + level shift, ac sync-tip clamp, or ac-bias
– AC-biasing is allowed with the use of external pull-up resistors to the positive power supply
• Sixth-order, low-pass filter for DAC reconstruction or ADC image rejection:
– 9.5 MHz for NTSC, PAL, SECAM, and composite video (CVBS) signals
– 72 MHz for 1080p60 Y’/P’ B/P’R or G’B’R’ signals
• Individually-controlled Disable mode shuts down all amplifiers in each SD/FHD block to reduce quiescent
current to 0.1 μA
• Internally-fixed gain of 2-V/V (+6-dB) buffer that can drive two video lines with dc-coupling or traditional
ac-coupling
• Flow-through configuration using a TSSOP-14 package that complies with the latest lead-free
(RoHS-compatible) and green manufacturing requirements
OPERATING VOLTAGE
The THS7372 is designed to operate from 2.7 V to 5 V over the –40°C to +85°C temperature range. The impact
on performance over the entire temperature range is negligible as a result of the implementation of thin film
resistors and high-quality, low-temperature coefficient capacitors. The design of the THS7372 allows operation
down to 2.6 V, but it is recommended to use at least a 3-V supply to ensure that no issues arise with headroom
or clipping with 100% color-saturated CVBS signals. If only 75% color saturated CVBS is supported, then the
output voltage requirements are reduced to 2 VPP on the output, allowing a 2.7-V supply to be utilized without
issues.
A 0.1-μF to 0.01-μF capacitor should be placed as close as possible to the power-supply pins. Failure to do so
may result in the THS7372 outputs ringing or oscillating. Additionally, a large capacitor (such as 22 μF to 100 μF)
should be placed on the power-supply line to minimize interference with 50-/60-Hz line frequencies.
INPUT VOLTAGE
The THS7372 input range allows for an input signal range from –0.2 V to approximately (VS+ – 1.5 V). However,
because of the internal fixed gain of 2 V/V (+6 dB) and the internal input level shift of 150 mV (typical), the output
is generally the limiting factor for the allowable linear input range. For example, with a 5-V supply, the linear input
range is from –0.2 V to 3.5 V. However, because of the gain and level shift, the linear output range limits the
allowable linear input range to approximately –0.1 V to 2.3 V.
28
Copyright © 2011, Texas Instruments Incorporated
THS7372
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www.ti.com
INPUT OVERVOLTAGE PROTECTION
The THS7372 is built using a very high-speed, complementary, bipolar, and CMOS process. The internal junction
breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in
the Absolute Maximum Ratings table. All input and output device pins are protected with internal ESD protection
diodes to the power supplies, as shown in Figure 83.
+VS
External
Input/Output
Pin
Internal
Circuitry
Figure 83. Internal ESD Protection
These diodes provide moderate protection to input overdrive voltages above and below the supplies as well. The
protection diodes can typically support 30 mA of continuous current when overdriven.
TYPICAL CONFIGURATION AND VIDEO TERMINOLOGY
A typical application circuit using the THS7372 as a video buffer is shown in Figure 84. It shows a DAC or
encoder driving the input channels of the THS7372. The SD channel (CVBS IN pin) can be used for NTSC, PAL,
or SECAM signals. The other three channels are the component video Y’/P’B/P’R (sometimes labeled Y’U’V’ or
incorrectly labeled Y’/C’B/C’R) signals. These signals are typically 480i, 576i, 480p, 576p, 720p, 1080i, or up to
1080p60 signals.
Note that the Y’ term is used for the luma channels throughout this document rather than the more common
luminance (Y) term. This usage accounts for the definition of luminance as stipulated by the International
Commission on Illumination (CIE). Video departs from true luminance because a nonlinear term, gamma, is
added to the true RGB signals to form R’G’B’ signals. These R’G’B’ signals are then used to mathematically
create luma (Y’). Thus, luminance (Y) is not maintained, providing a difference in terminology.
THS7372
CVBS
37.4 W
SOC/DAC/Encoder
+2.7 V to
+5 V
Y'/G'
37.4 W
P’B/B'
37.4 W
CVBS Out
75 W
75 W
CVBS OUT 14
1
CVBS IN
2
NC
DIS CVBS 13
3
VS+
GND 12
4
NC
DIS FHD 11
5
FHD1 IN
FHD1 OUT 10
6
FHD2 IN
FHD2 OUT
9
7
FHD3 IN
FHD3 OUT
8
Disable
CVBS
Disable
FHD
Y'/G’ Out
75 W
75 W
P'B/B’ Out
75 W
75 W
P’R/R'
37.4 W
P'R/R’ Out
75 W
75 W
Figure 84. Typical Four-Channel System Inputs from DC-Coupled Encoder/DAC with
DC-Coupled Line Driving
Copyright © 2011, Texas Instruments Incorporated
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THS7372
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R’G’B’ (commonly mislabeled RGB) is also called G’B’R’ (again commonly mislabeled as GBR) in professional
video systems. The Society of Motion Picture and Television Engineers (SMPTE) component standard stipulates
that the luma information is placed on the first channel, the blue color difference is placed on the second
channel, and the red color difference signal is placed on the third channel. This practice is consistent with the
Y'/P'B/P'R nomenclature. Because the luma channel (Y') carries the sync information and the green channel (G')
also carries the sync information, it makes logical sense that G' be placed first in the system. Because the blue
color difference channel (P'B) is next and the red color difference channel (P'R) is last, then it also makes logical
sense to place the B' signal on the second channel and the R' signal on the third channel, respectfully. Thus,
hardware compatibility is better achieved when using G'B'R' rather than R'G'B'. Note that for many G'B'R'
systems, sync is embedded on all three channels, but this configuration may not always be the case in all
systems.
INPUT MODE OF OPERATION: DC
The inputs to the THS7372 allow for both ac- and dc-coupled inputs. Many DACs or video encoders can be
dc-connected to the THS7372. One of the drawbacks to dc-coupling arises when 0 V is applied to the input.
Although the input of the THS7372 allows for a 0-V input signal without issue, the output swing of a traditional
amplifier cannot yield a 0-V signal, resulting in possible clipping. This limitation is true for any single-supply
amplifier because of the characteristics of the output transistors. Neither CMOS nor bipolar transistors can
achieve 0 V while sinking current. This transistor characteristic is also the same reason why the highest output
voltage is always less than the power-supply voltage when sourcing current.
This output clipping can reduce the sync amplitudes (both horizontal and vertical sync) on the video signal. A
problem occurs if the video signal receiver uses an automatic gain control (AGC) loop to account for losses in the
transmission line. Some video AGC circuits derive gain from the horizontal sync amplitude. If clipping occurs on
the sync amplitude, then the AGC circuit can increase the gain too much—resulting in too much luma and/or
chroma amplitude gain correction. This correction may result in a picture with an overly bright display with too
much color saturation.
Other AGC circuits use the chroma burst amplitude for amplitude control; reduction in the sync signals does not
alter the proper gain setting. However, it is good engineering design practice to ensure that saturation/clipping
does not take place. Transistors always take a finite amount of time to come out of saturation. This saturation
could possibly result in timing delays or other aberrations on the signals.
To eliminate saturation or clipping problems, the THS7372 has a 150-mV input level shift feature. This feature
takes the input voltage and adds an internal +150-mV shift to the signal. Because the THS7372 also has a gain
of 6 dB (2 V/V), the resulting output with a 0-V applied input signal is approximately 300 mV. The THS7372
rail-to-rail output stage can create this output level while connected to a typical video load. This configuration
ensures that no saturation or clipping of the sync signals occur. This shift is constant, regardless of the input
signal. For example, if a 1-V input is applied, the output is 2.3 V.
Because the internal gain is fixed at +6 dB, the gain dictates what the allowable linear input voltage range can be
without clipping concerns. For example, if the power supply is set to 3 V, the maximum output is approximately
2.9 V while driving a significant amount of current. Thus, to avoid clipping, the allowable input is ([2.9 V/2] – 0.15
V) = 1.3 V. This range is valid for up to the maximum recommended 5-V power supply that allows approximately
a ([4.9 V/2] – 0.15 V) = 2.3 V input range while avoiding clipping on the output.
30
Copyright © 2011, Texas Instruments Incorporated
THS7372
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www.ti.com
The input impedance of the THS7372 in this mode of operation is dictated by the internal, 800-kΩ pull-down
resistor, as shown in Figure 85. Note that the internal voltage shift does not appear at the input pin; it only shows
at the output pin.
+VS
Internal
Circuitry
Input
Pin
800 kW
Level
Shift
Figure 85. Equivalent DC Input Mode Circuit
INPUT MODE OF OPERATION: AC SYNC TIP CLAMP
Some video DACs or encoders are not referenced to ground but rather to the positive power supply. The
resulting video signals are generally at too great a voltage for a dc-coupled video buffer to function properly. To
account for this scenario, the THS7372 incorporates a sync-tip clamp circuit. This function requires a capacitor
(nominally 0.1 μF) to be in series with the input. Although the term sync-tip-clamp is used throughout this
document, it should be noted that the THS7372 would probably be better termed as a dc restoration circuit based
on how this function is performed. This circuit is an active clamp circuit and not a passive diode clamp function.
The input to the THS7372 has an internal control loop that sets the lowest input applied voltage to clamp at
ground (0 V). By setting the reference at 0 V, the THS7372 allows a dc-coupled input to also function. Therefore,
the sync-tip-clamp (STC) is considered transparent because it does not operate unless the input signal goes
below ground. The signal then goes through the same 150-mV level shifter, resulting in an output voltage low
level of 300 mV. If the input signal tries to go below 0 V, the THS7372 internal control loop sources up to 6 mA of
current to increase the input voltage level on the THS7372 input side of the coupling capacitor. As soon as the
voltage goes above the 0-V level, the loop stops sourcing current and becomes very high impedance.
One of the concerns about the sync-tip-clamp level is how the clamp reacts to a sync edge that has
overshoot—common in VCR signals, noise, DAC overshoot, or reflections found in poor printed circuit board
(PCB) layouts. Ideally, the STC should not react to the overshoot voltage of the input signal. Otherwise, this
response could result in clipping on the rest of the video signal because it may raise the bias voltage too much.
Copyright © 2011, Texas Instruments Incorporated
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THS7372
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To help minimize this input signal overshoot problem, the control loop in the THS7372 has an internal low-pass
filter, as shown in Figure 86. This filter reduces the response time of the STC circuit. This delay is a function of
how far the voltage is below ground, but in general it is approximately a 400-ns delay for the SD channel filters
and approximately a 150-ns delay for the FHD filters. The effect of this filter is to slow down the response of the
control loop so as not to clamp on the input overshoot voltage but rather the flat portion of the sync signal.
+VS
Internal
Circuitry
STC LPF
+VS
gm
Input
0.1 mF Input
Pin
800 kW
Level
Shift
Figure 86. Equivalent AC Sync-Tip-Clamp Input Circuit
As a result of this delay, sync may have an apparent voltage shift. The amount of shift depends on the amount of
droop in the signal as dictated by the input capacitor and the STC current flow. Because sync is used primarily
for timing purposes with syncing occurring on the edge of the sync signal, this shift is transparent in most
systems.
While this feature may not fully eliminate overshoot issues on the input signal, in cases of extreme overshoot
and/or ringing, the STC system should help minimize improper clamping levels. As an additional method to help
minimize this issue, an external capacitor (for example, 10 pF to 47 pF) to ground in parallel with the external
termination resistors can help filter overshoot problems.
It should be noted that this STC system is dynamic and does not rely upon timing in any way. It only depends on
the voltage that appears at the input pin at any given point in time. The STC filtering helps minimize level shift
problems associated with switching noises or very short spikes on the signal line. This architecture helps ensure
a very robust STC system.
When the ac STC operation is used, there must also be some finite amount of discharge bias current. As
previously described, if the input signal goes below the 0-V clamp level, the internal loop of the THS7372
sources current to increase the voltage appearing at the input pin. As the difference between the signal level and
the 0-V reference level increases, the amount of source current increases proportionally—supplying up to 6 mA
of current. Thus, the time to re-establish the proper STC voltage can be very fast. If the difference is very small,
then the source current is also very small to account for minor voltage droop.
However, what happens if the input signal goes above the 0-V input level? The problem is that the video signal is
always above this level and must not be altered in any way. Thus, if the sync level of the input signal is above
this 0-V level, then the internal discharge (sink) current reduces the ac-coupled bias signal to the proper 0-V
level.
This discharge current must not be large enough to alter the video signal appreciably or picture quality issues
may arise. This effect is often seen by looking at the tilt (droop) of a constant luma signal being applied and the
resulting output level. The associated change in luma level from the beginning and end of the video line is the
amount of line tilt (droop).
If the discharge current is very small, the amount of tilt is very low, which is a generally a good thing. However,
the amount of time for the system to capture the sync signal could be too long. This effect is also termed hum
rejection. Hum arises from the ac line voltage frequency of 50 Hz or 60 Hz. The value of the discharge current
and the ac-coupling capacitor combine to dictate the hum rejection and the amount of line tilt.
32
Copyright © 2011, Texas Instruments Incorporated
THS7372
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www.ti.com
To allow for both dc- and ac-coupling in the same part, the THS7372 incorporates an 800-kΩ resistor to ground.
Although a true constant current sink is preferred over a resistor, there can be issues when the voltage is near
ground. This configuration can cause the current sink transistor to saturate and cause potential problems with the
signal. The 800-kΩ resistor is large enough to not impact a dc-coupled DAC termination. For discharging an
ac-coupled source, Ohm’s Law is used. If the video signal is 1 V, then there is 1 V/800 kΩ = 1.25-μA of
discharge current. If more hum rejection is desired or there is a loss of sync occurring, then simply decrease the
0.1-μF input coupling capacitor. A decrease from 0.1 μF to 0.047 μF increases the hum rejection by a factor of
2.1. Alternatively, an external pull-down resistor to ground may be added that decreases the overall resistance
and ultimately increases the discharge current.
To ensure proper stability of the ac STC control loop, the source impedance must be less than 1 kΩ with the
input capacitor in place. Otherwise, there is a possibility of the control loop ringing, which may appear on the
output of the THS7372. Because most DACs or encoders use resistors (typically less than 300 Ω) to establish
the voltage, meeting the less than 1-kΩ requirement is easily done. However, if the source impedance looking
from the THS7372 input perspective is very high, then simply adding a 1-kΩ resistor to GND ensures proper
operation of the THS7372.
INPUT MODE OF OPERATION: AC BIAS
Sync-tip clamps work very well for signals that have horizontal and/or vertical syncs associated with them;
however, some video signals do not have a sync embedded within the signal. If ac-coupling of these signals is
desired, then a dc bias is required to properly set the dc operating point within the THS7372. This function is
easily accomplished with the THS7372 by simply adding an external pull-up resistor to the positive power supply,
as shown in Figure 87.
+3.3 V
CIN
0.1 mF
Input
+3.3 V
Internal
Circuitry
RPU
Input
Pin
800 kW
Level
Shift
Figure 87. AC-Bias Input Mode Circuit Configuration
The dc voltage appearing at the input pin is equal to Equation 1:
VDC = VS
800 kW
800 kW + RPU
(1)
The THS7372 allowable input range is approximately 0 V to (VS+ – 1.5 V), allowing for a very wide input voltage
range. As such, the input dc bias point is very flexible, with the output dc bias point being the primary factor. For
example, if the output dc bias point is desired to be 1.6 V on a 3.3-V supply, then the input dc bias point should
be (1.6 V – 300 mV)/2 = 0.65 V. Thus, the pull-up resistor calculates to approximately 3.3 MΩ, resulting in
0.644 V. If the output dc-bias point is desired to be 1.6 V with a 5-V power supply, then the pull-up resistor
calculates to approximately 5.36 MΩ.
Keep in mind that the internal 800-kΩ resistor has approximately a ±20% variance. As such, the calculations
should take this variance into account. For the 0.644-V example above, using an ideal 3.3-MΩ resistor, the input
dc bias voltage is approximately 0.644 V ±0.1 V.
The value of the output bias voltage is very flexible and is left to each individual design. It is important to ensure
that the signal does not clip or saturate the video signal. Thus, it is recommended to ensure the output bias
voltage is between 0.9 V and (VS+ – 1 V). For 100% color saturated CVBS or signals with Macrovision®, the
CVBS signal can reach up to 1.23 VPP at the input, or 2.46 VPP at the output of the THS7372. In contrast, other
signals are typically 1 VPP or 0.7 VPP at the input which translate to an output voltage of 2 VPP or 1.4 VPP. The
output bias voltage must account for a worst-case situation, depending on the signals involved.
Copyright © 2011, Texas Instruments Incorporated
33
THS7372
SBOS578 – AUGUST 2011
www.ti.com
One other issue that must be taken into account is the dc-bias point is a function of the power supply. As such,
there is an impact on system PSRR. To help reduce this impact, the input capacitor combines with the pull-up
resistance to function as a low-pass filter. Additionally, the time to charge the capacitor to the final dc bias point
is a function of the pull-up resistor and the input capacitor size. Lastly, the input capacitor forms a high-pass filter
with the parallel impedance of the pull-up resistor and the 800-kΩ resistor. In general, it is good to have this
high-pass filter at approximately 3 Hz to minimize any potential droop on a P’B or P’R signal. A 0.1-μF input
capacitor with a 3.3-MΩ pull-up resistor equates to approximately a 2.5-Hz high-pass corner frequency.
This mode of operation is recommended for use with chroma (C’), P’B, P’R, U’, and V’ signals. This method can
also be used with sync signals if desired. The benefit of using the STC function over the ac-bias configuration on
embedded sync signals is that the STC maintains a constant back-porch voltage as opposed to a back-porch
voltage that fluctuates depending on the video content. Because the high-pass corner frequency is a very low
2.5 Hz, the impact on the video signal is negligible relative to the STC configuration.
One question may arise over the P’B and P’R channels. For 480i, 576i, 480p, and 576p signals, a sync may or
may not be present. If no sync exists within the signal, then it is obvious that ac-bias is the preferred method of
ac-coupling the signal.
For 720p, 1080i, and 1080p signals, or for the the 480i, 576i, 480p, and 576p signals with sync present on the
P’B and P’R channels, the lowest voltage of the sync is –300 mV below the midpoint reference voltage of 0 V.
The P’B and P’R signals allow a signal to be as low as –350 mV below the midpoint reference voltage of 0 V. This
allowance corresponds to 100% yellow for P’B signal or 100% cyan for P’R signal . Because the P’B and P’R
signal voltage can be lower than the sync voltage, there exists a potential for clipping of the signal for a short
period of time if the signals drop below the sync voltage.
The THS7372 does include a 150-mV input level shift, or 300 mV at the output, that should mitigate any clipping
issues. For example, if a STC is used, then the bottom of the sync is 300 mV at the output. If the signal does go
the lowest level, or 50 mV lower than the sync at the input, then the instantaneous output is (–50 mV + 150 mV)
× 2 = 200 mV at the output.
Another potential risk is that if this signal (100% yellow for P’B or 100% cyan for P’R) exists for several pixels,
then the STC circuit engages to raise the voltage back to 0 V at the input. This function can cause a 50-mV level
shift at the input midway through the active video signal. This effect is undesirable and can cause errors in the
decoding of the signal. It is therefore recommended to use ac bias mode for component P’B and P’R signals
when ac-coupling is desired.
34
Copyright © 2011, Texas Instruments Incorporated
THS7372
SBOS578 – AUGUST 2011
www.ti.com
OUTPUT MODE OF OPERATION: DC-COUPLED
The THS7372 incorporates a rail-to-rail output stage that can be used to drive the line directly without the need
for large ac-coupling capacitors. This design offers the best line tilt and field tilt (droop) performance because no
ac-coupling occurs. Keep in mind that if the input is ac-coupled, then the resulting tilt as a result of the input
ac-coupling continues to be seen on the output, regardless of the output coupling. The 80-mA output current
drive capability of the THS7372 is designed to drive two video lines simultaneously—essentially, a 75-Ω
load—while keeping the output dynamic range as wide as possible. Figure 88 shows the THS7372 driving two
video lines while keeping the output dc-coupled.
THS7372
CVBS
37.4 W
SOC/DAC/Encoder
+2.7 V to
+5 V
Y'/G'
37.4 W
P’B/B'
CVBS 1 Out
75 W
CVBS 2 Out
75 W
75 W
75 W
75 W
Y'/G’ 2 Out
75 W
75 W
P'B/B’ 1 Out
75 W
75 W
P'B/B’ 2 Out
75 W
75 W
75 W
P'R/R’ 2 Out
75 W
75 W
CVBS OUT 14
1
CVBS IN
2
NC
3
VS+
GND 12
4
NC
DIS FHD 11
DIS CVBS 13
5
FHD1 IN
FHD1 OUT 10
6
FHD2 IN
FHD2 OUT
9
7
FHD3 IN
FHD3 OUT
8
37.4 W
75 W
Disable
CVBS
Disable
FHD
Y'/G’ 1 Out
P’R/R'
37.4 W
P'R/R’ 1 Out
75 W
Figure 88. Typical Four-Channel System with DC-Coupled Line Driving and Two Outputs Per Channel
One concern of dc-coupling, however, arises if the line is terminated to ground. If the ac-bias input configuration
is used, the output of the THS7372 has a dc bias on the output, such as 1.6 V. With two lines terminated to
ground, this configuration allows a dc current path to flow, such as 1.6 V/75-Ω = 21.3 mA. The result of this
configuration is a slightly decreased high output voltage swing and an increase in power dissipation of the
THS7372. While the THS7372 was designed to operate with a junction temperature of up to +125°C, care must
be taken to ensure that the junction temperature does not exceed this level or else long-term reliability could
suffer. Using a 5-V supply, this configuration can result in an additional dc power dissipation of (5 V – 1.6 V) ×
21.3 mA = 72.5 mW per channel. With a 3.3-V supply, this dissipation reduces to 36.2 mW per channel. The
overall low quiescent current of the THS7372 design minimizes potential thermal issues even when using the
TSSOP package at high ambient temperatures, but power and thermal analysis should always be examined in
any system to ensure that no issues arise. Be sure to use RMS power and not instantaneous power when
evaluating the thermal performance.
Note that the THS7372 can drive the line with dc-coupling regardless of the input mode of operation. The only
requirement is to make sure the video line has proper termination in series with the output (typically 75 Ω). This
requirement helps isolate capacitive loading effects from the THS7372 output. Failure to isolate capacitive loads
may result in instabilities with the output buffer, potentially causing ringing or oscillations to appear. The stray
capacitance appearing directly at the THS7372 output pins should be kept below 20 pF for the fixed SD filter
channels and below 15 pF for the FHD filter channels. One way to help ensure this condition is satisfied is to
make sure the 75-Ω source resistor is placed within 0.5 inches, or 12.7 mm, of the THS7372 output pin. If a large
ac-coupling capacitor is used, the capacitor should be placed after this resistor.
There are many reasons dc-coupling is desirable, including reduced costs, printed circuit board (PCB) area, and
no line tilt. A common question is whether or not there are any drawbacks to using dc-coupling. There are some
potential issues that must be examined, such as the dc current bias as discussed above. Another potential risk is
whether this configuration meets industry standards. EIA/CEA-770 stipulates that the back-porch shall be 0 V ± 1
V as measured at the receiver. With a double-terminated load system, this requirement implies a 0-V ± 2-V level
Copyright © 2011, Texas Instruments Incorporated
35
THS7372
SBOS578 – AUGUST 2011
www.ti.com
at the video amplifier output. The THS7372 can easily meet this requirement without issue. However, in Japan,
the EIAJ CP-1203 specification stipulates a 0-V ± 0.1-V level with no signal. This requirement can be met with
the THS7372 in shutdown mode, but while active it cannot meet this specification without output ac-coupling.
AC-coupling the output essentially ensures that the video signal works with any system and any specification.
For many modern systems, however, dc-coupling can satisfy most needs.
OUTPUT MODE OF OPERATION: AC-COUPLED
A very common method of coupling the video signal to the line is with a large capacitor. This capacitor is typically
between 220 μF and 1000 μF, although 470 μF is very typical. The value of this capacitor must be large enough
to minimize the line tilt (droop) and/or field tilt associated with ac-coupling as described previously in this
document. AC-coupling is performed for several reasons, but the most common is to ensure full interoperability
with the receiving video system. This approach ensures that regardless of the reference dc voltage used on the
transmitting side, the receiving side re-establishes the dc reference voltage to its own requirements.
In the same way as the dc output mode of operation discussed previously, each line should have a 75-Ω source
termination resistor in series with the ac-coupling capacitor. This 75-Ω resistor should be placed next to the
THS7372 output to minimize capacitive loading effects. If two lines are to be driven, it is best to have each line
use its own capacitor and resistor rather than sharing these components. This configuration helps ensure
line-to-line dc isolation and eliminates the potential problems as described previously. Using a single, 1000-μF
capacitor for two lines is permissible, but there is a chance for interference between the two receivers.
Lastly, because of the edge rates and frequencies of operation, it is recommended (but not required) to place a
0.1-μF to 0.01-μF capacitor in parallel with the large 220-μF to 1000-μF capacitor. These large value capacitors
are most commonly aluminum electrolytic. It is well-known that these capacitors have significantly large
equivalent series resistance (ESR), and the impedance at high frequencies is rather large as a result of the
associated inductances involved with the leads and construction. The small 0.1-μF to 0.01-μF capacitors help
pass these high-frequency signals (greater than 1 MHz) with much lower impedance than the large capacitors.
Although it is common to use the same capacitor values for all the video lines, the frequency bandwidth of the
chroma signal in a S-Video system is not required to go as low (or as high of a frequency) as the luma channels.
Thus, the capacitor values of the chroma line(s) can be smaller, such as 0.1 μF.
Figure 89 shows a typical configuration where the input is ac-coupled and the output is also ac-coupled.
AC-coupled inputs are generally required when current-sink DACs are used or the input is connected to an
unknown source, such as when the THS7372 is used as an input device.
THS7372
+V
CVBS Out
(1)
0.1 mF
CVBS
37.4 W
+V
SOC/DAC/Encoder
(1)
0.1 mF
+2.7 V to
+5 V
Y'/G'
37.4 W
(2)
75 W
330 mF
75 W
330 mF
75 W
330 mF
75 W
330 mF
75 W
CVBS OUT 14
1
CVBS IN
2
NC
DIS CVBS 13
3
VS+
GND 12
4
NC
DIS FHD 11
5
FHD1 IN
FHD1 OUT 10
6
FHD2 IN
FHD2 OUT
9
7
FHD3 IN
FHD3 OUT
8
Disable
CVBS
Disable
FHD
Y'/G’ Out
(2)
75 W
+V
(1)
0.1 mF
P’B/B'
37.4 W
+V
(2)
P'B/B’ Out
75 W
(1)
0.1 mF
P’R/R'
37.4 W
RPU
RPU
(2)
P'R/R’ Out
75 W
+2.7 V to +5 V
(1) AC-coupled input is shown in this example. DC-coupling is also allowed as long as the DAC output voltage is within the allowable linear
input and output voltage range of the THS7372. To apply dc-coupling, remove the 0.1-μF input capacitors and the RPU pull-up resistors.
(2) This example shows an ac-coupled output. DC-coupling is also allowed by simply removing these capacitors.
Figure 89. Typical AC Input System Driving AC-Coupled Video Lines
36
Copyright © 2011, Texas Instruments Incorporated
THS7372
www.ti.com
SBOS578 – AUGUST 2011
LOW-PASS FILTER
Each channel of the THS7372 incorporates a sixth-order, low-pass filter. These video reconstruction filters
minimize DAC images from being passed onto the video receiver. Depending on the receiver design, failure to
eliminate these DAC images can cause picture quality problems because of aliasing of the ADC in the receiver.
Another benefit of the filter is to smooth out aberrations in the signal that some DACs can have if the internal
filtering is not very good. This benefit helps with picture quality and ensures that the signal meets video
bandwidth requirements.
Each filter has an associated Butterworth characteristic. The benefit of the Butterworth response is that the
frequency response is flat with a relatively steep initial attenuation at the corner frequency. The problem with this
characteristic is that the group delay rises near the corner frequency. Group delay is defined as the change in
phase (radians/second) divided by a change in frequency. An increase in group delay corresponds to a time
domain pulse response that has overshoot and some possible ringing associated with the overshoot.
The use of other type of filters, such as elliptic or chebyshev, are not recommended for video applications
because of the very large group delay variations near the corner frequency resulting in significant overshoot and
ringing. While these filters may help meet the video standard specifications with respect to amplitude attenuation,
the group delay is well beyond the standard specifications. Considering this delay with the fact that video can go
from a white pixel to a black pixel over and over again, it is easy to see that ringing can occur. Ringing typically
causes a display to have ghosting or fuzziness appear on the edges of a sharp transition. On the other hand, a
Bessel filter has ideal group delay response, but the rate of attenuation is typically too low for acceptable image
rejection. Thus, the Butterworth filter is an acceptable compromise for both attenuation and group delay.
The THS7372 SD filter has a nominal corner (–3-dB) frequency at 9.5 MHz and a –1-dB passband typically at
8.2 MHz. This 9.5-MHz filter is ideal for SD NTSC, PAL, and SECAM composite video (CVBS) signals. The
9.5-MHz, –3-dB corner frequency was designed to achieve 54 dB of attenuation at 27 MHz—a common sampling
frequency between the DAC/ADC second and third Nyquist zones found in many video systems. This
consideration is important because any signal that appears around this frequency can also appear in the
baseband as a result of aliasing effects of an ADC found in a receiver.
The THS7372 FHD filters have a nominal corner (–3-dB) frequency at 72 MHz and a –1-dB passband typically at
60 MHz. This 72-MHz filter is ideal for 1080p50 or 1080p60 component video. It is also ideal for oversampling
systems where the video DAC upsamples the video signal such as 720p or 1080i upsampled to 148.5 MHz. The
benefit is an extremely flat passband response along with almost no group delay within the HD video passband.
Keep in mind that images do not stop at the DAC sampling frequency, fS (for example, 27 MHz for traditional SD
DACs); they continue around the sampling frequencies of 2x fS, 3x fS, 4x fS, and so on (that is, 54 MHz, 81 MHz,
108 MHz, etc.). Because of these multiple images, an ADC can fold down into the baseband signal, meaning that
the low-pass filter must also eliminate these higher-order images. The THS7372 filters are Butterworth filters and,
as such, do not bounce at higher frequencies, thus maintaining good attenuation performance.
The filter frequencies were chosen to account for process variations in the THS7372. To ensure the required
video frequencies are effectively passed, the filter corner frequency must be high enough to allow component
variations. The other consideration is that the attenuation must be large enough to ensure the
anti-aliasing/reconstruction filtering is sufficient to meet the system demands. Thus, the selection of the filter
frequencies was not arbitrarily selected and is a good compromise that should meet the demands of most
systems.
BENEFITS OVER PASSIVE FILTERING
Two key benefits of using an integrated filter system, such as the THS7372, over a passive system are PCB area
and filter variations. The small TSSOP-14 package for four video channels is much smaller over a passive RLC
network, especially a six-pole passive network. Additionally, consider that inductors have at best ±10%
tolerances (normally, ±15% to ±20% is common) and capacitors typically have ±10% tolerances. Using a Monte
Carlo analysis shows that the filter corner frequency (–3 dB), flatness (–1 dB), Q factor (or peaking), and
channel-to-channel delay have wide variations. These variances can lead to potential performance and quality
issues in mass-production environments. The THS7372 solves most of these problems with the corner frequency
being essentially the only variable.
Copyright © 2011, Texas Instruments Incorporated
37
THS7372
SBOS578 – AUGUST 2011
www.ti.com
Another concern about passive filters is the use of inductors. Inductors are magnetic components, and are
therefore susceptible to electromagnetic coupling/interference (EMC/EMI). Some common coupling can occur
because of other video channels nearby using inductors for filtering, or it can come from nearby switched-mode
power supplies. Some other forms of coupling could be from outside sources with strong EMI radiation and can
cause failure in EMC testing such as required for CE compliance.
One concern about an active filter in an integrated circuit is the variation of the filter characteristics when the
ambient temperature and the subsequent die temperature changes. To minimize temperature effects, the
THS7372 uses low-temperature coefficient resistors and high-quality, low-temperature coefficient capacitors
found in the BiCom3X process. These filters have been specified by design to account for process variations and
temperature variations to maintain proper filter characteristics. This approach maintains a low channel-to-channel
time delay that is required for proper video signal performance.
Another benefit of the THS7372 over a passive RLC filter is the input and output impedance. The input
impedance presented to the DAC varies significantly, from 35 Ω to over 1.5 kΩ with a passive network, and may
cause voltage variations over frequency. The THS7372 input impedance is 800 kΩ, and only the 2-pF input
capacitance plus the PCB trace capacitance impact the input impedance. As such, the voltage variation
appearing at the DAC output is better controlled with a fixed termination resistor and the high input impedance
buffer of the THS7372.
On the output side of the filter, a passive filter again has a large impedance variation over frequency. The
EIA/CEA-770 specifications require the return loss to be at least 25 dB over the video frequency range of usage.
For a video system, this requirement implies the source impedance (which includes the source, series resistor,
and the filter) must be better than 75 Ω, ±9 Ω. The THS7372 is an operational amplifier that approximates an
ideal voltage source, which is desirable because the output impedance is very low and can source and sink
current. To properly match the transmission line characteristic impedance of a video line, a 75-Ω series resistor is
placed on the output. To minimize reflections and to maintain a good return loss meeting EIA/CEA specifications,
this output impedance must maintain a 75-Ω impedance. A wide impedance variation of a passive filter cannot
ensure this level of performance. On the other hand, the THS7372 has approximately 0.7 Ω of output impedance,
or a return loss of 47 dB, at 6.75 MHz for the SD filter and approximately 4 Ω of output impedance, or a return
loss of 32 dB, at 60 MHz for the FHD filters. Thus, the system is matched significantly better with a THS7372
compared to a passive filter.
One final benefit of the THS7372 over a passive filter is power dissipation. A DAC driving a video line must be
able to drive a 37.5-Ω load: the receiver 75-Ω resistor and the 75-Ω impedance matching resistor next to the
DAC to maintain the source impedance requirement. This requirement forces the DAC to drive at least 1.25 VP
(100% saturation CVBS)/37.5 Ω = 33.3 mA. A DAC is a current-steering element, and this amount of current
flows internally to the DAC even if the output is 0 V. Thus, power dissipation in the DAC may be very high,
especially when four channels are being driven. Using the THS7372 with a high input impedance and the
capability to drive up to two video lines per channel can reduce DAC power dissipation significantly. This
outcome is possible because the resistance that the DAC drives can be substantially increased. It is common to
set this resistance in a DAC by a current-setting resistor on the DAC itself. Thus, the resistance can be 300 Ω or
more, substantially reducing the current drive demands from the DAC and saving significant amounts of power.
For example, a 3.3-V, four-channel DAC dissipates 440 mW alone for the steering current capability (four
channels × 33.3 mA × 3.3 V) if it must drive a 37.5-Ω load. With a 300-Ω load, the DAC power dissipation as a
result of current steering current would only be 55 mW (four channels × 4.16 mA × 3.3 V).
38
Copyright © 2011, Texas Instruments Incorporated
THS7372
SBOS578 – AUGUST 2011
www.ti.com
EVALUATION MODULE
To evaluate the THS7372, an evaluation module (EVM) is available. The THS7372EVM allows for testing the
THS7372 in many different configurations. Inputs and outputs include BNC connectors and RCA connectors
commonly found in video systems, along with 75-Ω input termination resistors, 75-Ω series source termination
resistors, and 75-Ω characteristic impedance traces. Several unpopulated component pads are found on the
EVM to allow for different input and output configurations as dictated by the user. This EVM is designed to be
used with a single supply from 2.6 V up to 5 V.
The EVM default input configuration sets all channels for dc input coupling. The input signal must be within 0 V
to approximately 1.4 V for proper operation. Failure to be within this range saturates and/or clips the output
signal. If the input range is beyond this, if the signal voltage is unknown, or if coming from a current sink DAC,
then ac input configuration is desired. This option is easily accomplished with the EVM by simply replacing the Z1
through Z4 0-Ω resistors with 0.1-μF capacitors.
For an ac-coupled input and sync-tip clamp (STC) functionality commonly used for CVBS, component Y' signals,
and R'G'B' signals, no other changes are needed. However, if a bias voltage is needed after the input capacitor
which is commonly needed for component P'B, and P'R, then a pull-up resistor should be added to the signal on
the EVM. This configuration is easily achieved by simply adding a resistor to any of the following resistor pads;
RX4 to RX6 for the FHD channels and RX8 for the CVBS channel. A common value to use is 3.3 MΩ. Note that
even signals with embedded sync can also use bias mode if desired.
The EVM default output configuration sets all channels for ac output coupling. The 470-μF and 0.1-μF capacitors
work well for most ac-coupled systems. However, if dc-coupled output is desired, then replacing the 0.1-μF
capacitors (C24, C26, C28, and/or C30) with 0-Ω resistors works well. Removing the 470-μF capacitors is
optional, but removing them from the EVM eliminates a few picofarads of stray capacitance on each signal path
which may be desirable.
The THS7372 incorporates an easy method to configure the disable modes. The use of JP1 controls the SD
channel disable feature; JP3 controls the FHD channels disable feature.
Connection of JP1 and JP3 to GND applies 0 V to the disable pins and the THS7372 operates normally. Moving
JP1 to +VS causes the THS7372 SD channel to be in disable mode, while moving JP3 to +VS causes the
THS7372 FHD channels to be in disable mode.
Figure 90 shows the THS7372EVM schematic. Figure 92 and Figure 93 illustrate the two layers of the EVM PCB,
incorporating standard high-speed layout practices. Table 7 lists the bill of materials as the board comes supplied
from Texas Instruments.
Copyright © 2011, Texas Instruments Incorporated
39
THS7372
SBOS578 – AUGUST 2011
www.ti.com
+
+
Figure 90. THS7372EVM Schematic 1
40
Copyright © 2011, Texas Instruments Incorporated
THS7372
SBOS578 – AUGUST 2011
www.ti.com
Figure 91. THS7372EVM Schematic 2
Copyright © 2011, Texas Instruments Incorporated
41
THS7372
SBOS578 – AUGUST 2011
www.ti.com
Figure 92. THS7372EVM PCB Top Layer
Figure 93. THS7372EVM PCB Bottom Layer
42
Copyright © 2011, Texas Instruments Incorporated
THS7372
SBOS578 – AUGUST 2011
www.ti.com
THS7372EVM Bill of Materials
Table 7. THS7372EVM Parts List
ITEM
REF DES
QTY
DESCRIPTION
1
FB1, FB2
2
Bead, ferrite, 2.5 A, 330 Ω
2
C17
1
Capacitor, 100 µF, tantalum, 10 V, 10%, low
ESR
3
C18
1
Capacitor, 22 µF, tantalum, 16 V, 10%, low
ESR
4
C5-C8,
C19-C22,
C31-C34
12
Open
5
C15
1
6
C1-C4, C10,
C12-C14, C16,
C24, C26, C28,
C30, C35-C38
7
MANUFACTURER
PART NUMBER
SMD SIZE
DISTRIBUTOR
PART NUMBER
(TDK) MPZ2012S331A
(DIGI-KEY)
445-1569-1-ND
C
(AVX) TPSC107K010R0100
(DIGI-KEY)
478-1765-1-ND
C
(AVX) TPSC226K016R0375
(DIGI-KEY)
478-1767-1-ND
0805
—
—
Capacitor, 0.01 µF, ceramic, 100 V, X7R
0805
(AVX) 08051C103KAT2A
(DIGI-KEY)
478-1358-1-ND
17
Capacitor, 0.1 µF, ceramic, 50 V, X7R
0805
(AVX) 08055C104KAT2A
(DIGI-KEY)
478-1395-1-ND
C9, C11
2
Capacitor, 0.1 µF, ceramic, 50 V, X7R
1206
(AVX) 12065C104KAT2A
(DIGI-KEY)
478-1556-1-ND
8
C23, C25, C27,
C29
4
Capacitor, aluminum, 470 µF, 10 V, 20%
(PANASONIC)
EEE-FP1A471AP
(DIGI-KEY)
PCE4526CT-ND
9
RX1-RX12, R7,
R10, R12, R14
16
Open
0603
—
—
10
Z1-Z4, R1,
R16-R21, R26
12
Resistor, 0 Ω
0805
(ROHM) MCR10EZHJ000
(DIGI-KEY)
RHM0.0ACT-ND
11
R2-R5,
R22-R25
8
Resistor, 75 Ω, 1/8 W, 1%
0805
(ROHM) MCR10EZHF75.0
(DIGI-KEY)
RHM75.0CCT-ND
12
R8
1
Resistor, 100 Ω, 1/8 W, 1%
0805
(ROHM) MCR10EZHF1000
(DIGI-KEY)
RHM100CCT-ND
13
R6, R13
2
Resistor, 1 kΩ, 1/8 W, 1%
0805
(ROHM) MCR10EZHF1001
(DIGI-KEY)
RHM1.00KCCT-ND
14
R9, R11
2
Resistor, 100 kΩ, 1/8 W, 1%
0805
(ROHM) MCR10EZHF1003
(DIGI-KEY)
RHM100KCCT-ND
15
R15
1
Resistor, 1 kΩ, 1/4 W, 1%
1206
(ROHM) MCR18EZHF1001
(DIGI-KEY)
RHM1.00KFCT-ND
16
D1-D8
8
Diode, ultrafast
(FAIRCHILD) BAV99
(DIGI-KEY)
BAV99FSCT-ND
17
J6, J7
2
Jack, banana receptance, 0.25" diameter
hole
(SPC) 813
(NEWARK) 39N867
18
J1-J3, J5,
J11-J14
8
Connector, BNC, jack, 75 Ω
(AMPHENOL)
31-5329-72RFX
(NEWARK) 93F7554
19
J8
1
Connector, SMA, jack, 50 Ω
(AMPHENOL) 901-144-8RFX
(DIGI-KEY) ARFX1231-ND
20
J4, J15
2
Connector, RCA jack, yellow
(CUI) RCJ-044
(DIGI-KEY) CP-1421-ND
21
J9, J10
2
Connector, RCA, jack, R/A
(CUI) RCJ-32265
(DIGI-KEY) CP-1446-ND
22
TP1, TP2
2
Test point, black
(KEYSTONE) 5001
(DIGI-KEY) 5001K-ND
23
JP1-JP4
4
Header, 0.1" CTRS, 0.025" square pins
(SULLINS) PBC36SAAN
(DIGI-KEY) S1011E-36-ND
24
JP1-JP4
4
Shunts
(SULLINS) SSC02SYAN
(DIGI-KEY) S9002-ND
25
U1
1
IC, THS7372
(TI) THS7372IPW
—
26
4
Standoff, 4-40 hex, 0.625" length
(KEYSTONE) 1808
(DIGI-KEY) 1808K-ND
27
4
Screw, Phillips, 4-40, .250"
(BF) PMS 440 0031 PH
(DIGI-KEY) H343-ND
28
1
Board, printed circuit
EDGE # 6526621 REV.A
—
Copyright © 2011, Texas Instruments Incorporated
805
F
3 pos.
PW
43
PACKAGE OPTION ADDENDUM
www.ti.com
27-Aug-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
THS7372IPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
THS7372IPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Aug-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
THS7372IPWR
Package Package Pins
Type Drawing
TSSOP
PW
14
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
12.4
Pack Materials-Page 1
6.9
B0
(mm)
K0
(mm)
P1
(mm)
5.6
1.6
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Aug-2011
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
THS7372IPWR
TSSOP
PW
14
2000
346.0
346.0
29.0
Pack Materials-Page 2
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