TI TLV2262IP

 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
D
D
D
D
D
D
Output Swing Includes Both Supply Rails
Low Noise . . . 12 nV/√Hz Typ at f = 1 kHz
Low Input Bias Current . . . 1 pA Typ
Fully Specified for Both Single-Supply and
Split-Supply Operation
Low Power . . . 500 µA Max
Common-Mode Input Voltage Range
Includes Negative Rail
D Low Input Offset Voltage
D
D
D
950 µV Max at TA = 25°C (TLV226xA)
Wide Supply Voltage Range
2.7 V to 8 V
Macromodel Included
Available in Q-Temp Automotive
HighRel Automotive Applications
Configuration Control / Print Support
Qualification to Automotive Standards
description
4
VDD = 3 V
3.5
VOH − High-Level Output Voltage − V
The TLV2262 and TLV2264 are dual and quad low
voltage operational amplifiers from Texas Instruments. Both devices exhibit rail-to-rail output
performance for increased dynamic range in
single or split supply applications. The TLV226x
family offers a compromise between the micropower TLV225x and the ac performance of the
TLC227x. It has low supply current for batterypowered applications, while still having adequate
ac performance for applications that demand it.
This family is fully characterized at 3 V and 5 V and
is optimized for low-voltage applications. The
noise performance has been dramatically improved over previous generations of CMOS
amplifiers. Figure 1 depicts the low level of noise
voltage for this CMOS amplifier, which has only
200 µA (typ) of supply current per amplifier.
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
3
TA = − 55°C
2.5
TA = 125°C
2
TA = 25°C
1.5
ÁÁ
ÁÁ
1
0.5
TA = 85°C
TA = − 40°C
0
The TLV226x, exhibiting high input impedance
0
500
1000
1500
2000
and low noise, are excellent for small-signal
| IOH | − High-Level Output Current − µ A
conditioning for high-impedance sources, such as
Figure 1
piezoelectric transducers. Because of the micropower dissipation levels combined with 3-V
operation, these devices work well in hand-held monitoring and remote-sensing applications. In addition, the
rail-to-rail output feature with single or split supplies makes this family a great choice when interfacing with
analog-to-digital converters (ADCs). For precision applications, the TLV226xA family is available and has a
maximum input offset voltage of 950 µV.
The TLV2262/4 also makes great upgrades to the TLV2332/4 in standard designs. They offer increased output
dynamic range, lower noise voltage and lower input offset voltage. This enhanced feature set allows them to
be used in a wider range of applications. For applications that require higher output drive and wider input voltage
range, see the TLV2432 and TLV2442 devices. If your design requires single amplifiers, please see the
TLV2211/21/31 family. These devices are single rail-to-rail operational amplifiers in the SOT-23 package. Their
small size and low power consumption make them ideal for high density, battery-powered equipment.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Advanced LinCMOS is a trademark of Texas Instruments.
Copyright  1997−2006, Texas Instruments Incorporated
!"# $ %!!# $ &%'(# #)
!%#$ !" # $&#$ &! #* #!"$ $ $#!%"#$
$#! +!!#,) !%# &!$$- $ # $$!(, (%
#$#- (( &!"#!$)
&!%#$ "&(# # ./0.0 (( &!"#!$ ! #$#
%($$ #*!+$ #) (( #*! &!%#$ &!%#
&!$$- $ # $$!(, (% #$#- (( &!"#!$)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
TLV2262 AVAILABLE OPTIONS
PACKAGED DEVICES
VIOmax
AT 25°C
TA
SMALL
OUTLINE
(D)
CHIP
CARRIER
(FK)
CERAMIC
DIP
(JG)
PLASTIC
DIP
(P)
TSSOP
(PW)
CERAMIC
FLATPACK
(U)
0°C to 70°C
2.5 mV
TLV2262CD
—
—
TLV2262CP
TLV2262CPWLE
—
−40°C to 125°C
950 µV
2.5 mV
TLV2262AID
TLV2262ID
—
—
—
—
TLV2262AIP
TLV2262IP
TLV2262AIPWLE
—
—
—
−40°C to 125°C
950 µV
2.5 mV
TLV2262AQD
TLV2262QD
—
—
—
—
—
—
—
—
—
—
−55°C to 125°C
950 µV
2.5 mV
—
—
TLV2262AMFK
TLV2262MFK
TLV2262AMJG
TLV2262MJG
—
—
—
—
TLV2262AMU
TLV2262MU
† The D packages are available taped and reeled. Add R suffix to device type (e.g., TLV2262CDR).
‡ The PW package is available only left-end taped and reeled.
§ Chips are tested at 25°C.
¶ For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site
at www.ti.com.
TLV2264 AVAILABLE OPTIONS
PACKAGED DEVICES
TA
VIOmax
AT 25°C
SMALL
OUTLINE
(D)
CHIP
CARRIER
(FK)
CERAMIC
DIP
(J)
PLASTIC
DIP
(N)
TSSOP
(PW)
CERAMIC
FLATPACK
(W)
−40 C to
−40°C
125°C
950 µV
2.5 mV
TLV2264AID
TLV2264ID
—
—
—
—
TLV2264AIN
TLV2264IN
TLV2264AIPWLE
—
—
—
−40 C to
−40°C
125°C
950 µV
2.5 mV
TLV2264AQD
TLV2264QD
—
—
—
—
—
—
—
—
—
—
−55°C to
125°C
950 µV
2.5 mV
—
—
TLV2264AMFK
TLV2264MFK
TLV2264AMJ
TLV2264MJ
—
—
—
—
TLV2264AMW
TLV2264MW
† The D packages are available taped and reeled. Add R suffix to device type (e.g., TLV2262IDR).
‡ The PW package is available only left-end taped and reeled.
§ Chips are tested at 25°C.
¶ For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site
at www.ti.com.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
TLV2262C, TLV2262AC
TLV2262I, TLV2262AI
TLV2262Q, TLV2262AQ
D, P, OR PW PACKAGE
(TOP VIEW)
1OUT
1IN −
1IN +
VDD − /GND
1
8
2
7
3
6
4
5
TLV2264I, TLV2264AI
TLV2264Q, TLV2264AQ
D, N, OR PW PACKAGE
(TOP VIEW)
1OUT
1IN −
1IN +
VDD +
2IN +
2IN −
2OUT
VDD +
2OUT
2IN −
2IN +
TLV2262M, TLV2262AM
JG PACKAGE
(TOP VIEW)
1OUT
1IN −
1IN +
VDD − /GND
1
8
2
7
3
6
4
5
1OUT
1IN −
1IN +
VDD +
2IN +
2IN −
2OUT
NC
VCC +
2OUT
2IN −
2IN +
10
2
9
3
8
4
7
5
6
1IN +
NC
VCC +
NC
2IN +
NC
1OUT
NC
VDD+
NC
17
6
16
7
15
8
14
9 10 11 12 13
11
5
10
6
9
7
8
1
14
2
13
3
12
4
11
5
10
6
9
7
8
4OUT
4IN −
4IN +
VDD − / GND
3IN +
3IN −
3OUT
NC
2OUT
NC
2IN −
NC
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
4IN +
NC
VCC − /GND
NC
3IN +
2IN −
2OUT
NC
3OUT
3IN −
5
12
4
NC
VDD− /GND
NC
2IN+
NC
NC
1IN −
NC
1IN +
NC
3
4OUT
4IN −
4IN +
VDD − / GND
3IN +
3IN −
3OUT
TLV2264M, TLV2264AM
FK PACKAGE
(TOP VIEW)
TLV2262M, TLV2262AM
FK PACKAGE
(TOP VIEW)
3 2 1 20 19
18
4
13
1IN −
1OUT
NC
4OUT
4IN −
1
14
2
TLV2264M, TLV2264AM
J OR W PACKAGE
(TOP VIEW)
VDD +
2OUT
2IN −
2IN +
TLV2662M, TLV2262AM
U PACKAGE
(TOP VIEW)
NC
1OUT
1IN −
1IN +
VCC − /GND
1
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
4
IN −
IN +
Q1
Q5
R4
Q2
R3
Q3
Q4
equivalent schematic (each amplifier)
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Q8
Q10
R6
Q9
3
Capacitors
6
18
54
76
TLV2254
† Includes both amplifiers and all ESD, bias, and trim circuitry
9
28
Diodes
Resistors
TLV2252
38
COMPONENT
Transistors
R1
Q13
C1
Q12
VDD −/ GND
Q11
R5
ACTUAL DEVICE COMPONENT COUNT†
Q7
Q6
VDD +
R2
Q15
Q14
D1
Q17
Q16
OUT
Template Release Date: 7−11−94
1
1 1
SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 V
Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VDD
Input voltage range, VI (any input, see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD − −0.3 V to VDD+
Input current, II (each input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 5 mA
Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Total current into VDD + . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Total current out of VDD − . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Duration of short-circuit current (at or below) 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA: I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
Q suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
M suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to VDD − .
2. Differential voltages are at the noninverting input with respect to the inverting input. Excessive current flows when input is brought
below VDD − − 0.3 V.
3. The output may be shorted to either supply. Temperature and /or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
25 C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
85°C
TA = 85
C
POWER RATING
125°C
TA = 125
C
POWER RATING
D−8
725 mW
5.8 mW/°C
377 mW
145 mW
D−14
950 mW
7.6 mW/°C
494 mW
190 mW
FK
1375 mW
11.0 mW/°C
715 mW
275 mW
J
1375 mW
11.0 mW/°C
715 mW
275 mW
JG
1050 mW
8.4 mW/°C
—
210 mW
N
1150 mW
9.2 mW/°C
598 mW
—
P
1000 mW
8.0 mW/°C
520 mW
200 mW
PW−8
525 mW
4.2 mW/°C
273 mW
105 mW
PW−14
700 mW
5.6 mW/°C
364 mW
—
U
700 mW
5.5 mW/°C
—
150 mW
W
700 mW
5.5 mW/°C
370 mW
150 mW
recommended operating conditions
I SUFFIX
Supply voltage, VDD ± Input voltage range, VI
Common-mode input voltage, VIC
Q SUFFIX
M SUFFIX
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
2.7
8
2.7
8
2.7
8
V
VDD + − 1.3
VDD + − 1.3
V
VDD −
VDD −
VDD + − 1.3 VDD −
VDD + − 1.3 VDD −
125
−40
Operating free-air temperature, TA
−40
NOTE 1: All voltage values, except differential voltages, are with respect to VDD − .
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
VDD + − 1.3 VDD −
VDD + − 1.3 VDD −
125
−55
125
V
°C
5
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
TLV2262I electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise
noted)
PARAMETER
VIO
Input offset voltage
αVIO
Temperature coefficient
of input offset voltage
Input offset voltage
long-term drift
(see Note 4)
IIO
TEST CONDITIONS
TA†
TLV2262I
MIN
25°C
MAX
300
2500
Full range
Input offset current
Common-mode input
voltage range
RS = 50 Ω
Ω,
VOH
High-level output
voltage
0.003
0.003
µV/mo
25°C
0.5
IOH = − 400 µA
VIC = 1.5 V,
VOL
Low-level output
voltage
VIC = 1.5 V,
VIC = 1.5 V,
AVD
Large-signal differential
voltage amplification
IOL = 50 µA
IOL = 500 µA
IOL = 1 A
RL = 50 kΩ‡
VIC = 1.5 V,
VO = 1 V to 2 V
RL = 1 MΩ‡
60
0.5
150
60
150
800
1
1
60
150
150
Full range
800
800
25°C
0
to
2
Full range
0
to
1.7
−0.3
to
2.2
0
to
2
−0.3
to
2.2
2.99
2.99
2.85
2.85
Full range
2.825
2.825
25°C
2.7
2.7
Full range
2.65
V
2.65
25°C
10
10
25°C
100
100
Full range
150
150
200
Full range
25°C
60
30
100
mV
200
300
Full range
pA
V
0
to
1.7
25°C
25°C
pA
800
60
85°C
25°C
IOH = − 100 µA
µV
25°C
|VIO | ≤ 5 mV
IOH = − 20 µA
950
1500
UNIT
µV/°C
25°C
VICR
300
MAX
2
85°C
Input bias current
TYP
2
Full range
IIB
MIN
3000
25°C
to 85°C
VDD ± = ± 1.5 V, VIC = 0,
VO = 0,
RS = 50 Ω
TLV2262AI
TYP
300
60
100
30
V/mV
25°C
100
100
ri(d)
Differential input
resistance
25°C
1012
1012
Ω
ri(c)
Common-mode input
resistance
25°C
1012
1012
Ω
ci(c)
Common-mode input
capacitance
f = 10 kHz,
P package
25°C
8
8
pF
zo
Closed-loop output
impedance
f = 100 kHz,
AV = 10
25°C
270
270
Ω
CMRR
Common-mode
rejection ratio
VIC = 0 to 1.7 V,
VO = 1.5 V,
RS = 50 Ω
kSVR
Supply voltage rejection
ratio (∆VDD/∆VIO)
VDD = 2.7 V to 8 V,
VIC = VDD /2,
No load
25°C
65
Full range
60
25°C
80
Full range
80
75
65
77
60
95
80
80
100
dB
dB
† Full range is − 40°C to 125°C.
‡ Referenced to 1.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
TLV2262I electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise
noted) (continued)
PARAMETER
IDD
Supply current
TA†
TEST CONDITIONS
VO = 1.5 V,
No load
TLV2262I
MIN
25°C
TLV2262AI
TYP
MAX
400
500
Full range
MIN
TYP
MAX
400
500
500
500
UNIT
µA
† Full range is − 40°C to 125°C.
TLV2262I operating characteristics at specified free-air temperature, VDD = 3 V
PARAMETER
SR
Slew rate at unity gain
TEST CONDITIONS
VO = 1.1 V to 1.9 V,
CL = 100 pF‡
RL = 50 kΩ‡,
TLV2262I
TA†
MIN
TYP
25°C
0.35
0.55
Full
range
0.3
TLV2262AI
MAX
MIN
TYP
0.35
0.55
MAX
UNIT
V/µs
0.3
Equivalent input noise
voltage
f = 10 Hz
25°C
43
43
Vn
f = 1 kHz
25°C
12
12
Peak-to-peak
equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
25°C
0.6
0.6
VN(PP)
f = 0.1 Hz to 10 Hz
25°C
1
1
In
Equivalent input noise
current
25°C
0.6
0.6
Total harmonic
distortion plus noise
VO = 0.5 V to 2.5 V,
f = 20 kHz,
RL = 50 kΩ‡
AV = 1
0.03%
0.03%
THD + N
0.05%
0.05%
Gain-bandwidth
product
f = 1 kHz,
CL = 100 pF‡
RL = 50 kΩ‡,
25°C
0.67
0.67
MHz
Maximum
output-swing
bandwidth
VO(PP) = 1 V,
RL = 50 kΩ‡,
AV = 1,
CL = 100 pF‡
25°C
395
395
kHz
5.6
5.6
Settling time
AV = − 1,
Step = 1 V to 2 V,
RL = 50 kΩ‡,
CL = 100 pF‡
12.5
12.5
25°C
55°
55°
25°C
11
11
BOM
ts
φm
Phase margin at
unity gain
RL = 50 kΩ‡,
nV/√Hz
µV
V
fA /√Hz
25°C
AV = 10
To 0.1%
µss
25°C
To 0.01%
CL = 100 pF‡
Gain margin
† Full range is − 40°C to 125°C.
‡ Referenced to 1.5 V
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
dB
7
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
TLV2262I electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise
noted)
PARAMETER
VIO
Input offset voltage
αVIO
Temperature coefficient
of input offset voltage
Input offset voltage
long-term drift
(see Note 4)
IIO
TEST CONDITIONS
TA†
TLV2262I
MIN
25°C
25°C
25
C
to 85°C
Input offset current
Input bias current
Common-mode input
voltage range
|VIO | ≤ 5 mV,
High-level output voltage
IOH = − 400 µA
VIC = 2.5 V,
VOL
Low-level output voltage
VIC = 2.5 V,
VIC = 2.5 V,
IOL = 50 µA
IOL = 500 µA
IOL = 1 A
RL = 50 kΩ‡
VIC = 2.5 V,
VO = 1 V to 4 V
RL = 1 MΩ‡
µV
25°C
0.003
0.003
µV/mo
25°C
0.5
60
0.5
60
85°C
150
150
Full range
800
800
1
60
1
150
150
Full range
800
800
0
to
4
0
to
3.5
−0.3
to
4.2
0
to
4
0
to
3.5
4.99
25°C
4.85
Full range
4.82
25°C
4.7
Full range
4.6
−0.3
to
4.2
4.85
4.85
4.94
4.7
V
4.85
4.6
0.01
0.09
Full range
0.01
0.15
0.09
0.15
0.2
Full range
Full range
55
170
0.15
0.15
0.3
0.2
0.3
80
V
4.82
25°C
25°C
pA
4.99
4.94
25°C
25°C
pA
60
85°C
25°C
IOH = − 100 µA
950
1500
UNIT
µV/°C
RS = 50 Ω
IOH = − 20 µA
300
MAX
2
Full range
VOH
2500
TYP
2
25°C
25
C
VICR
300
MIN
3000
25°C
IIB
MAX
Full range
VDD ± = ± 2.5 V, VIC = 0,
VO = 0,
RS = 50 Ω
TLV2262AI
TYP
V
0.3
0.3
80
170
AVD
Large-signal differential
voltage amplification
25°C
550
550
ri(d)
Differential input
resistance
25°C
1012
1012
Ω
ri(c)
Common-mode input
resistance
25°C
1012
1012
Ω
ci(c)
Common-mode input
capacitance
f = 10 kHz,
P package
25°C
8
8
pF
zo
Closed-loop output
impedance
f = 100 kHz,
AV = 10
25°C
240
240
Ω
CMRR
Common-mode rejection
ratio
VIC = 0 to 2.7 V,
VO = 2.5 V,
RS = 50 Ω
25°C
70
Full range
70
Supply voltage rejection
ratio (∆VDD /∆VIO)
VDD = 4.4 V to 8 V,
VIC = VDD /2,
No load
25°C
80
kSVR
Full range
80
55
83
70
V/mV
83
70
95
80
80
dB
95
dB
† Full range is − 40°C to 125°C.
‡ Referenced to 2.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
TLV2262I electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise
noted) (continued)
PARAMETER
TEST CONDITIONS
TA†
TLV2262I
MIN
25°C
IDD
Supply current
VO = 2.5 V,
No load
TLV2262AI
TYP
MAX
400
500
Full range
MIN
TYP
MAX
400
500
500
500
UNIT
µA
A
† Full range is − 40°C to 125°C.
TLV2262I operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER
TEST CONDITIONS
RL = 50 kΩ‡,
TLV2262I
TA†
MIN
TYP
25°C
0.35
0.55
Full
range
0.3
TLV2262AI
MAX
MIN
TYP
0.35
0.55
Slew rate at unity
gain
VO = 1.5 V to 3.5 V,
CL = 100 pF‡
Equivalent input
noise voltage
f = 10 Hz
25°C
40
40
Vn
f = 1 kHz
25°C
12
12
Peak-to-peak
equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
25°C
0.7
0.7
VN(PP)
f = 0.1 Hz to 10 Hz
25°C
1.3
1.3
In
Equivalent input
noise current
25°C
0.6
0.6
Total harmonic
distortion plus
noise
VO = 0.5 V to 2.5 V,
f = 20 kHz,
RL = 50 kΩ‡
AV = 1
THD + N
Gain-bandwidth
product
f = 50 kHz,
CL = 100 pF‡
RL = 50 kΩ‡,
Maximum outputswing bandwidth
VO(PP) = 2 V,
RL = 50 kΩ‡,
AV = 1,
CL = 100 pF‡
Settling time
AV = − 1,
Step = 0.5 V to 2.5 V,
RL = 50 kΩ‡,
CL = 100 pF‡
SR
BOM
ts
φm
Phase margin at
unity gain
RL = 50 kΩ‡,
MAX
UNIT
V/µs
0.3
nV/√Hz
µV
V
fA /√Hz
0.017%
0.017%
0.03%
0.03%
25°C
0.71
0.71
MHz
25°C
185
185
kHz
6.4
6.4
14.1
14.1
25°C
56°
56°
25°C
11
11
25°C
AV = 10
To 0.1%
µss
25°C
To 0.01%
CL = 100 pF‡
Gain margin
† Full range is − 40°C to 125°C.
‡ Referenced to 2.5 V
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
dB
9
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
TLV2264I electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise
noted)
PARAMETER
VIO
Input offset voltage
αVIO
Temperature coefficient
of input offset voltage
Input offset voltage
long-term drift
(see Note 4)
IIO
Input offset current
TEST CONDITIONS
TA†
TLV2264I
MIN
25°C
25°C
25
C
to 85°C
Input bias current
Common-mode input
voltage range
RS = 50 Ω
Ω,
High-level output
voltage
IOH = − 400 µA
VOL
Low-level output voltage
0.003
0.003
µV/mo
25°C
0.5
AVD
Large-signal differential
voltage amplification
60
150
Full range
800
800
1
60
1
150
150
Full range
800
800
0
to
2
0
to
1.7
−0.3
to
2.2
0
to
2
0
to
1.7
2.99
−0.3
to
2.2
pA
V
2.99
25°C
2.85
2.85
Full range
2.825
2.825
25°C
2.7
2.7
Full range
2.65
V
2.65
10
VIC = 1.5 V,
IOL = 500 µA
25°C
100
Full range
10
100
150
25°C
pA
60
85°C
25°C
VIC = 1.5 V,
VO = 1 to 2 V
0.5
150
IOL = 50 µA
IOL = 1 A
60
85°C
VIC = 1.5 V,
VIC = 1.5 V,
µV
25°C
25°C
IOH = − 100 µA
950
1500
UNIT
µV/°C
|VIO | ≤ 5 mV
IOH = − 20 µA
300
MAX
2
Full range
VOH
2500
TYP
2
25°C
25
C
VICR
300
MIN
3000
25°C
IIB
MAX
Full range
VDD ± = ± 1.5 V,
VIC = 0,
VO = 0,
RS= 50 Ω
TLV2264AI
TYP
150
200
Full range
300
100
mV
200
300
RL = 50 kΩ‡
25°C
60
60
100
Full range
30
RL = 1 MΩ‡
25°C
100
100
30
V/mV
ri(d)
Differential input
resistance
25°C
1012
1012
Ω
ri(c)
Common-mode input
resistance
25°C
1012
1012
Ω
ci(c)
Common-mode input
capacitance
f = 10 kHz,
N package
25°C
8
8
pF
zo
Closed-loop output
impedance
f = 100 kHz,
AV = 10
25°C
270
270
Ω
CMRR
Common-mode
rejection ratio
kSVR
Supply voltage rejection
ratio ((∆V
VDD /∆V
/ VIO)
VIC = 0 to 1.7 V,
RS = 50 Ω
VO = 1.5 V,
VDD = 2.7 V to 8 V,
25°C
65
Full range
60
25°C
80
VIC = VDD /2,
Full range
80
No load
75
65
77
60
95
80
80
100
dB
dB
† Full range is − 40°C to 125°C.
‡ Referenced to 1.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
TLV2264I electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise
noted) (continued)
PARAMETER
Supply current
(four amplifiers)
IDD
TA†
TEST CONDITIONS
VO = 1.5 V,
No load
TLV2264I
MIN
25°C
TLV2264AI
TYP
MAX
0.8
1
Full range
MIN
TYP
MAX
0.8
1
1
1
UNIT
mA
† Full range is − 40°C to 125°C.
TLV2264I operating characteristics at specified free-air temperature, VDD = 3 V
PARAMETER
TEST CONDITIONS
RL = 50 kΩ‡,
TA†
TLV2264I
MIN
TYP
25°C
0.35
0.55
Full
range
0.3
TLV2264AI
MAX
MIN
TYP
0.35
0.55
MAX
UNIT
SR
Slew rate at unity
gain
VO = 0.7 V to 1.7 V,
CL = 100 pF‡
Equivalent input
noise voltage
f = 10 Hz
25°C
43
43
Vn
f = 1 kHz
25°C
12
12
Peak-to-peak
equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
25°C
0.6
0.6
VN(PP)
f = 0.1 Hz to 10 Hz
25°C
1
1
In
Equivalent input
noise current
25°C
0.6
0.6
Total harmonic
distortion plus
noise
VO = 0.5 V to 2.5 V,
f = 20 kHz,
RL = 50 kΩ ‡
AV = 1
0.03%
0.03%
THD + N
0.05%
0.05%
Gain-bandwidth
product
f = 1 kHz,
CL = 100 pF ‡
RL = 50 kΩ ‡,
25°C
0.67
0.67
MHz
Maximum
output-swing
bandwidth
VO(PP) = 1 V,
RL = 50 kΩ ‡,
AV = 1,
CL = 100 pF ‡
25°C
395
395
kHz
5.6
5.6
Settling time
AV = −1,
Step = 1 V to 2 V,
RL = 50 kΩ ‡,
CL = 100 pF ‡
12.5
12.5
25°C
55°
55°
25°C
11
11
BOM
ts
φm
Phase margin at
unity gain
RL = 50 kΩ‡,
V/µs
0.3
nV/√Hz
µV
V
fA /√Hz
25°C
AV = 10
To 0.1%
µss
25°C
To 0.01%
CL = 100 pF ‡
Gain margin
† Full range is − 40°C to 125°C.
‡ Referenced to 1.5 V
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
dB
11
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
TLV2264I electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise
noted)
PARAMETER
VIO
Input offset voltage
αVIO
Temperature coefficient
of input offset voltage
Input offset voltage
long-term drift
(see Note 4)
IIO
Input offset current
TEST CONDITIONS
TA†
TLV2264I
MIN
25°C
VICR
25°C
25
C
to 85°C
Input bias current
Common-mode input
voltage range
|VIO | ≤ 5 mV,
High-level output
voltage
IOH = − 100 µA
VIC = 2.5 V,
VOL
VIC = 2.5 V,
VIC = 2.5 V,
AVD
Large-signal differential
voltage amplification
IOL = 50 µA
IOL = 500 µA
IOL = 1 A
RL = 50 kΩ‡
VIC = 2.5 V,
VO = 1 V to 4 V
RL = 1 MΩ‡
300
MAX
950
1500
UNIT
µV
2
µV/°C
25°C
0.003
0.003
µV/mo
25°C
0.5
60
0.5
60
85°C
150
150
Full range
800
800
1
60
1
150
150
Full range
800
800
25°C
25
C
0
to
4
Full range
0
to
3.5
−0.3
to
4.2
0
to
4
4.85
Full range
4.82
25°C
4.7
Full range
4.6
−0.3
to
4.2
4.99
4.94
4.85
4.94
4.82
4.85
4.7
V
4.85
4.6
25°C
0.01
25°C
0.09
Full range
0.01
0.15
0.09
0.15
25°C
0.2
Full range
80
Full range
55
170
0.15
0.15
0.3
0.2
0.3
25°C
pA
V
0
to
3.5
4.99
25°C
pA
60
85°C
25°C
IOH = − 400 µA
Low-level output
voltage
2500
TYP
2
RS = 50 Ω
IOH = − 20 µA
VOH
300
MIN
3000
25°C
IIB
MAX
Full range
VDD ± = ± 2.5 V,
VIC = 0,
VO = 0,
RS = 50 Ω
TLV2264AI
TYP
V
0.3
0.3
80
170
55
V/mV
25°C
550
550
ri(d)
Differential input
resistance
25°C
1012
1012
Ω
ri(c)
Common-mode input
resistance
25°C
1012
1012
Ω
ci(c)
Common-mode input
capacitance
f = 10 kHz,
N package
25°C
8
8
pF
zo
Closed-loop output
impedance
f = 100 kHz,
AV = 10
25°C
240
240
Ω
CMRR
Common-mode rejection
ratio
VIC = 0 to 2.7 V, VO = 2.5 V,
RS = 50 Ω
25°C
70
Full range
70
kSVR
Supply voltage rejection
ratio (∆VDD /∆VIO)
VDD = 4.4 V to 8 V,
VIC = VDD /2, No load
25°C
80
Full range
80
83
70
83
70
95
80
80
95
dB
dB
† Full range is − 40°C to 125°C.
‡ Referenced to 2.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
TLV2264I electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise
noted) (continued)
PARAMETER
Supply current
(four amplifiers)
IDD
TEST CONDITIONS
VO = 2.5 V,
No load
TA†
TLV2264I
MIN
25°C
TLV2264AI
TYP
MAX
0.8
1
Full range
MIN
TYP
MAX
0.8
1
1
1
UNIT
mA
† Full range is − 40°C to 125°C.
TLV2264I operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER
TEST CONDITIONS
RL = 50 kΩ ‡,
TA†
TLV2264I
MIN
TYP
25°C
0.35
0.55
Full
range
0.3
TLV2264AI
MAX
MIN
TYP
0.35
0.55
MAX
UNIT
SR
Slew rate at unity
gain
VO = 1.4 V to 2.6 V,
CL = 100 pF ‡
Equivalent input
noise voltage
f = 10 Hz
25°C
40
40
Vn
f = 1 kHz
25°C
12
12
Peak-to-peak
equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
25°C
0.7
0.7
VN(PP)
f = 0.1 Hz to 10 Hz
25°C
1.3
1.3
In
Equivalent input
noise current
25°C
0.6
0.6
Total harmonic
distortion plus
noise
VO = 0.5 V to 2.5 V,
f = 20 kHz,
RL = 50 kΩ ‡
AV = 1
0.017%
0.017%
THD + N
0.03%
0.03%
Gain-bandwidth
product
f = 50 kHz,
CL = 100 pF ‡
RL = 50 kΩ ‡,
25°C
0.71
0.71
MHz
Maximum outputswing bandwidth
VO(PP) = 2 V,
RL = 50 kΩ ‡,
AV = 1,
CL = 100 pF ‡
25°C
185
185
kHz
6.4
6.4
Settling time
AV = − 1,
Step = 0.5 V to 2.5 V,
RL = 50 kΩ ‡,
CL = 100 pF ‡
14.1
14.1
25°C
56°
56°
25°C
11
11
BOM
ts
φm
Phase margin at
unity gain
RL = 50 kΩ ‡,
V/µs
0.3
nV/√Hz
µV
V
fA /√Hz
25°C
AV = 10
To 0.1%
µss
25°C
To 0.01%
CL = 100 pF ‡
Gain margin
† Full range is − 40°C to 125°C.
‡ Referenced to 2.5 V
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
dB
13
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
TLV2262Q and TLV2262M electrical characteristics at specified free-air temperature, VDD = 3 V
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLV2262Q,
TLV2262M
MIN
VIO
Input offset voltage
αVIO
Temperature coefficient
of input offset voltage
Input offset voltage
long-term drift
(see Note 4)
IIO
Input offset current
IIB
Input bias current
25°C
Common-mode input
voltage range
VIC = 1.5 V,
Low-level output
voltage
VIC = 1.5 V,
VIC = 1.5 V,
AVD
Large-signal differential
voltage amplification
IOL = 500 µA
IOL = 1 A
RL = 50 kΩ‡
VIC = 1.5 V,
VO = 1 V to 2 V
RL = 1 MΩ‡
µV
0.003
0.003
µV/mo
25°C
0.5
60
0.5
800
1
0
to
2
0
to
1.7
60
−0.3
to
2.2
1
0
to
2
0
to
1.7
2.99
−0.3
to
2.2
2.85
Full range
2.82
2.82
25°C
2.7
2.7
Full range
2.55
10
25°C
100
Full range
200
Full range
10
150
100
100
150
165
300
200
300
25
V
V
165
Full range
pA
2.55
25°C
60
pA
2.99
2.85
25°C
60
800
25°C
25°C
60
800
800
25°C
IOL = 50 µA
950
1500
25°C
|VIO | ≤ 5 mV
IOH = − 100 µA
300
UNIT
MAX
µV/°C
25°C
RS = 50 Ω
Ω,
TYP
2
125°C
IOH = − 400 µA
VOL
2500
125°C
IOH = − 20 µA
High-level output
voltage
300
MIN
2
Full range
VOH
MAX
3000
25°C
25
C
to 125°C
25°C
25
C
VICR
TYP
Full range
VDD ± = ± 1.5 V, VIC = 0,
VO = 0,
RS = 50 Ω
TLV2262AQ,
TLV2262AM
mV
300
300
60
100
25
V/mV
25°C
100
100
ri(d)
Differential input
resistance
25°C
1012
1012
Ω
ri(c)
Common-mode input
resistance
25°C
1012
1012
Ω
ci(c)
Common-mode input
capacitance
f = 10 kHz,
P package
25°C
8
8
pF
zo
Closed-loop output
impedance
f = 100 kHz,
AV = 10
25°C
270
270
Ω
CMRR
Common-mode
rejection ratio
VIC = 0 to 1.7 V,
VO = 1.5 V,
RS = 50 Ω
25°C
65
Full range
60
kSVR
Supply voltage rejection
ratio ((∆V
VDD /∆V
/ VIO)
VDD = 2.7 V to 8 V,
VIC = VDD /2,
No load
25°C
80
Full range
80
75
65
77
60
95
80
80
100
dB
dB
† Full range is − 40°C to 125°C for Q level part, − 55°C to 125°C for M level part.
‡ Referenced to 1.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
TLV2262Q and TLV2262M electrical characteristics at specified free-air temperature, VDD = 3 V
(unless otherwise noted) (continued)
PARAMETER
TA†
TEST CONDITIONS
TLV2262Q,
TLV2262M
MIN
IDD
Supply current
VO = 1.5 V,
No load
25°C
TLV2262AQ,
TLV2262AM
TYP
MAX
400
500
Full range
MIN
UNIT
TYP
MAX
400
500
500
500
µA
† Full range is − 40°C to 125°C for Q level part, − 55°C to 125°C for M level part.
TLV2262Q and TLV2262M operating characteristics at specified free-air temperature, VDD = 3 V
PARAMETER
SR
Slew rate at unity gain
VO = 0.5 V to 1.7 V,
CL = 100 pF‡
TLV2262Q,
TLV2262M
TA†
TEST CONDITIONS
RL = 50 kΩ‡,
MIN
TYP
25°C
0.35
0.55
Full
range
0.25
MAX
TLV2262AQ,
TLV2262AM
MIN
TYP
0.35
0.55
UNIT
MAX
V/µs
0.25
Equivalent input noise
voltage
f = 10 Hz
25°C
43
43
Vn
f = 1 kHz
25°C
12
12
Peak-to-peak
equivalent input noise
voltage
f = 0.1 Hz to 1 Hz
25°C
0.6
0.6
VN(PP)
f = 0.1 Hz to 10 Hz
25°C
1
1
In
Equivalent input noise
current
25°C
0.6
0.6
Total harmonic
distortion plus noise
0.03%
0.03%
THD + N
0.05%
0.05%
25°C
0.67
0.67
MHz
25°C
395
395
kHz
5.6
5.6
12.5
12.5
25°C
55°
55°
Gain margin
25°C
† Full range is − 40°C to 125°C for Q level part, − 55°C to 125°C for M level part.
‡ Referenced to 1.5 V
11
11
BOM
ts
φm
VO = 0.5 V to 2.5 V,
f = 20 kHz,
RL = 50 kΩ‡
AV = 1
Gain-bandwidth
product
f = 1 kHz,
CL = 100 pF‡
RL = 50 kΩ‡,
Maximum
output-swing
bandwidth
VO(PP) = 1 V,
RL = 50 kΩ‡,
AV = 1,
CL = 100 pF‡
Settling time
AV = − 1,
Step = 1 V to 2 V,
RL = 50 kΩ‡,
CL = 100 pF‡
Phase margin at unity
gain
RL = 50 kΩ‡,
nV/√Hz
µV
V
fA /√Hz
25°C
AV = 10
To 0.1%
µss
25°C
To 0.01%
CL = 100 pF‡
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
dB
15
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
TLV2262Q and TLV2262M electrical characteristics at specified free-air temperature, VDD = 5 V
(unless otherwise noted)
PARAMETER
TLV2262Q,
TLV2262M
TA†
TEST CONDITIONS
MIN
VIO
Input offset voltage
αVIO
Temperature coefficient of
input offset voltage
Input offset voltage
long-term drift (see Note 4)
IIO
Input offset current
IIB
Input bias current
VICR
Common-mode input
voltage range
25°C
High-level output voltage
2500
VIC = 2.5 V,
VIC = 2.5 V,
IOL = 500 µA
IOL = 1 A
RL = 50 kΩ‡
VIC = 2.5 V,
VO = 1 V to 4 V
RL = 1 MΩ‡
950
1500
µV
25°C
0.003
0.003
µV/mo
25°C
0.5
60
0.5
800
1
25°C
25
C
0
to
4
60
Full range
0
to
3.5
−0.3
to
4.2
1
25°C
4.85
4.82
25°C
4.7
Full range
4.5
0
to
4
−0.3
to
4.2
4.85
4.85
4.94
4.7
V
4.85
4.5
0.09
Full range
0.01
0.15
0.09
0.15
0.2
Full range
50
170
0.15
0.15
0.3
0.2
0.3
80
V
4.82
25°C
25°C
pA
4.99
4.94
0.01
Full range
pA
0
to
3.5
25°C
25°C
60
800
4.99
Full range
60
800
800
25°C
IOL = 50 µA
300
UNIT
MAX
µV/°C
RS = 50 Ω
IOH = − 100 µA
TYP
2
125°C
|VIO | ≤ 5 mV,
MIN
2
25°C
VIC = 2.5 V,
Low-level output voltage
300
125°C
IOH = − 400 µA
VOL
MAX
3000
25°C
25
C
to 125°C
IOH = − 20 µA
VOH
TYP
Full range
VDD ± = ± 2.5 V, VIC = 0,
VO = 0,
RS = 50 Ω
TLV2262AQ,
TLV2262AM
V
0.3
0.3
80
170
AVD
Large-signal differential
voltage amplification
ri(d)
Differential input resistance
25°C
550
1012
550
1012
Ω
ri(c)
Common-mode input
resistance
25°C
1012
1012
Ω
ci(c)
Common-mode input
capacitance
f = 10 kHz,
P package
25°C
8
8
pF
zo
Closed-loop output
impedance
f = 100 kHz,
AV = 10
25°C
240
240
Ω
CMRR
Common-mode rejection
ratio
VIC = 0 to 2.7 V,
VO = 2.5 V,
RS = 50 Ω
25°C
70
Full range
70
kSVR
Supply voltage rejection
ratio (∆VDD /∆VIO)
VDD = 4.4 V to 8 V,
VIC = VDD /2,
No load
25°C
80
Full range
80
25°C
50
83
70
V/mV
83
70
95
80
80
95
dB
dB
† Full range is − 40°C to 125°C for Q level part, − 55°C to 125°C for M level part.
‡ Referenced to 2.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
TLV2262Q and TLV2262M electrical characteristics at specified free-air temperature, VDD = 5 V
(unless otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
TLV2262Q,
TLV2262M
TA†
MIN
IDD
Supply current
VO = 2.5 V,
No load
25°C
TLV2262AQ,
TLV2262AM
TYP
MAX
400
500
Full range
MIN
UNIT
TYP
MAX
400
500
500
500
µA
† Full range is − 40°C to 125°C for Q level part, − 55°C to 125°C for M level part.
TLV2262Q and TLV2262M operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER
TEST CONDITIONS
RL = 50 kΩ‡
TLV2262Q,
TLV2262M
TA†
MIN
TYP
25°C
0.35
0.55
Full
range
0.25
TLV2262AQ,
TLV2262AM
MAX
MIN
TYP
0.35
0.55
Slew rate at unity
gain
VO = 0.5 V to 3.5 V,
CL = 100 pF‡
Equivalent input
noise voltage
f = 10 Hz
25°C
40
40
Vn
f = 1 kHz
25°C
12
12
Peak-to-peak
equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
25°C
0.7
0.7
VN(PP)
f = 0.1 Hz to 10 Hz
25°C
1.3
1.3
In
Equivalent input
noise current
25°C
0.6
0.6
Total harmonic
distortion plus
noise
VO = 0.5 V to 2.5 V,
f = 20 kHz,
RL = 50 kΩ‡
AV = 1
THD + N
Gain-bandwidth
product
f = 50 kHz,
CL = 100 pF‡
RL = 50 kΩ‡,
Maximum
output-swing
bandwidth
VO(PP) = 2 V,
RL = 50 kΩ‡,
AV = 1,
CL = 100 pF‡
Settling time
AV = − 1,
Step = 0.5 V to 2.5 V,
RL = 50 kΩ‡,
CL = 100 pF‡
SR
UNIT
MAX
V/µs
0.25
nV/√Hz
µV
V
fA /√Hz
0.017%
0.017%
0.03%
0.03%
25°C
0.71
0.71
MHz
25°C
185
185
kHz
6.4
6.4
14.1
14.1
25°C
56°
56°
Gain margin
25°C
† Full range is − 40°C to 125°C for Q level part, − 55°C to 125°C for M level part.
‡ Referenced to 2.5 V
11
11
BOM
ts
φm
Phase margin at
unity gain
RL = 50 kΩ‡,
25°C
AV = 10
To 0.1%
µss
25°C
To 0.01%
CL = 100 pF‡
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
dB
17
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
TLV2264Q and TLV2264M electrical characteristics at specified free-air temperature, VDD = 3 V
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLV2264Q,
TLV2264M
MIN
VIO
Input offset voltage
αVIO
Temperature coefficient
of input offset voltage
Input offset voltage
long-term drift
(see Note 4)
IIO
Input offset current
IIB
Input bias current
25°C
Common-mode input
voltage range
VIC = 1.5 V,
Low-level output
voltage
VIC = 1.5 V,
VIC = 1.5 V,
AVD
Large-signal differential
voltage amplification
IOL = 500 µA
IOL = 1 A
RL = 50 kΩ‡
VIC = 1.5 V,
VO = 1 V to 2 V
RL = 1 MΩ‡
µV
0.003
0.003
µV/mo
25°C
0.5
60
0.5
800
1
0
to
2
0
to
1.7
60
−0.3
to
2.2
1
0
to
2
0
to
1.7
2.99
−0.3
to
2.2
2.85
Full range
2.82
2.82
25°C
2.7
2.7
Full range
2.6
10
25°C
100
Full range
200
Full range
10
150
100
100
150
150
300
200
300
25
V
V
150
60
pA
2.6
25°C
25°C
pA
2.99
2.85
Full range
60
800
25°C
25°C
60
800
800
25°C
IOL = 50 µA
950
1500
25°C
|VIO | ≤ 5 mV
IOH = − 100 µA
300
UNIT
MAX
µV/°C
25°C
RS = 50 Ω
Ω,
TYP
2
125°C
IOH = − 400 µA
VOL
2500
125°C
IOH = − 20 µA
High-level output
voltage
300
MIN
2
Full range
VOH
MAX
3000
25°C
25
C
to 125°C
25°C
25
C
VICR
TYP
Full range
VDD ± = ± 1.5 V,
VIC = 0,
VO = 0,
RS = 50 Ω
TLV2264AQ,
TLV2264AM
mV
300
300
60
100
25
V/mV
25°C
100
100
ri(d)
Differential input
resistance
25°C
1012
1012
Ω
ri(c)
Common-mode input
resistance
25°C
1012
1012
Ω
ci(c)
Common-mode input
capacitance
f = 10 kHz,
N package
25°C
8
8
pF
zo
Closed-loop output
impedance
f = 100 kHz,
AV = 10
25°C
270
270
Ω
CMRR
Common-mode rejection
ratio
VIC = 0 to 1.7 V, VO = 1.5 V,
RS = 50 Ω
VDD = 2.7 V to 8 V,
25°C
65
Full range
60
75
65
60
77
dB
25°C
80
95
80
100
dB
VIC = VDD /2,
No load
Full range
80
80
† Full range is − 40°C to 125°C for Q level part, − 55°C to 125°C for M level part.
‡ Referenced to 1.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
kSVR
18
Supply voltage rejection
VDD /∆V
/ VIO)
ratio ((∆V
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
TLV2264Q and TLV2264M electrical characteristics at specified free-air temperature, VDD = 3 V
(unless otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
TLV2264Q,
TLV2264M
TA†
MIN
Supply current (four
amplifiers)
IDD
VO = 1.5 V,
No load
25°C
TLV2264AQ,
TLV2264AM
TYP
MAX
0.8
1
Full range
MIN
UNIT
TYP
MAX
0.8
1
1
1
mA
† Full range is − 40°C to 125°C for Q level part, − 55°C to 125°C for M level part.
TLV2264Q and TLV2264M operating characteristics at specified free-air temperature, VDD = 3 V
PARAMETER
TEST CONDITIONS
RL = 50 kΩ‡,
TLV2264Q,
TLV2264M
TA†
MIN
TYP
25°C
0.35
0.55
Full
range
0.25
TLV2264AQ,
TLV2264AM
MAX
MIN
TYP
0.35
0.55
UNIT
MAX
SR
Slew rate at unity
gain
VO = 0.5 V to 1.7 V,
CL = 100 pF‡
Equivalent input
noise voltage
f = 10 Hz
25°C
43
43
Vn
f = 1 kHz
25°C
12
12
Peak-to-peak
equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
25°C
0.6
0.6
VN(PP)
f = 0.1 Hz to 10 Hz
25°C
1
1
In
Equivalent input
noise current
25°C
0.6
0.6
Total harmonic
distortion plus
noise
VO = 0.5 V to 2.5 V,
f = 20 kHz,
RL = 50 kΩ ‡
AV = 1
0.03%
0.03%
THD + N
0.05%
0.05%
Gain-bandwidth
product
f = 1 kHz,
CL = 100 pF ‡
RL = 50 kΩ ‡,
25°C
0.67
0.67
MHz
Maximum outputswing bandwidth
VO(PP) = 1 V,
RL = 50 kΩ‡,
AV = 1,
CL = 100 pF ‡
25°C
395
395
kHz
5.6
5.6
Settling time
AV = − 1,
Step = 1 V to 2 V,
RL = 50 kΩ ‡,
CL = 100 pF ‡
12.5
12.5
25°C
55°
55°
Gain margin
25°C
† Full range is − 40°C to 125°C for Q level part, − 55°C to 125°C for M level part.
‡ Referenced to 1.5 V
11
11
BOM
ts
φm
Phase margin at
unity gain
RL = 50 kΩ‡,
V/µs
0.25
nV/√Hz
µV
V
fA /√Hz
25°C
AV = 10
To 0.1%
µss
25°C
To 0.01%
CL = 100 pF ‡
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
dB
19
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
TLV2264Q and TLV2264M electrical characteristics at specified free-air temperature, VDD = 5 V
(unless otherwise noted)
PARAMETER
TLV2264Q,
TLV2264M
TA†
TEST CONDITIONS
MIN
VIO
Input offset voltage
αVIO
Temperature coefficient of
input offset voltage
Input offset voltage
long-term drift
(see Note 4)
IIO
Input offset current
IIB
Input bias current
VICR
Common-mode input
voltage range
25°C
High-level output voltage
|VIO | ≤ 5 mV,
VIC = 2.5 V,
Large-signal differential
voltage amplification
IOL = 500 µA
IOL = 1 A
RL = 50 kΩ‡
VIC = 2.5 V,
VO = 1 V to 4 V
RL = 1 MΩ‡
950
1500
µV
25°C
0.003
0.003
µV/mo
25°C
0.5
60
0.5
800
1
25°C
25
C
0
to
4
60
Full range
0
to
3.5
−0.3
to
4.2
1
4.85
Full range
4.82
25°C
4.7
Full range
4.5
0
to
4
−0.3
to
4.2
4.85
4.94
4.82
4.85
4.7
V
4.85
4.5
0.01
0.09
Full range
0.01
0.15
0.09
0.15
0.2
Full range
Full range
50
170
0.15
0.15
0.3
0.2
0.3
80
pA
4.99
4.94
25°C
25°C
pA
V
0
to
3.5
25°C
25°C
60
800
4.99
25°C
60
800
800
25°C
IOL = 50 µA
300
UNIT
MAX
µV/°C
RS = 50 Ω
IOH = − 100 µA
TYP
2
125°C
VIC = 2.5 V,
AVD
2500
MIN
2
25°C
VIC = 2.5 V,
Low-level output voltage
300
125°C
IOH = − 400 µA
VOL
MAX
3000
25°C
25
C
to 125°C
IOH = − 20 µA
VOH
TYP
Full range
VDD ± = ± 2.5 V,
VIC = 0,
VO = 0,
RS = 50 Ω
TLV2264AQ,
TLV2264AM
V
0.3
0.3
80
170
50
V/mV
25°C
550
550
ri(d)
Differential input
resistance
25°C
1012
1012
Ω
ri(c)
Common-mode input
resistance
25°C
1012
1012
Ω
ci(c)
Common-mode input
capacitance
f = 10 kHz,
N package
25°C
8
8
pF
zo
Closed-loop output
impedance
f = 100 kHz,
AV = 10
25°C
240
240
Ω
CMRR
Common-mode rejection
ratio
VIC = 0 to 2.7 V, VO = 2.5 V,
RS = 50 Ω
25°C
70
Full range
70
kSVR
Supply voltage rejection
ratio (∆VDD /∆VIO)
VDD = 4.4 V to 8 V,
VIC = VDD /2,
No load
25°C
80
Full range
80
83
70
83
70
95
80
80
95
dB
dB
† Full range is − 40°C to 125°C for Q level part, − 55°C to 125°C for M level part.
‡ Referenced to 2.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
20
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
TLV2264Q and TLV2264M electrical characteristics at specified free-air temperature, VDD = 5 V
(unless otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
TLV2264Q,
TLV2264M
TA†
MIN
Supply current (four
amplifiers)
IDD
VO = 2.5 V,
No load
25°C
TLV2264AQ,
TLV2264AM
TYP
MAX
0.8
1
Full range
MIN
UNIT
TYP
MAX
0.8
1
1
1
mA
† Full range is − 40°C to 125°C for Q level part, − 55°C to 125°C for M level part.
TLV2264Q and TLV2264M operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER
TEST CONDITIONS
RL = 50 kΩ ‡,
TLV2264Q,
TLV2264M
TA†
MIN
TYP
25°C
0.35
0.55
Full
range
0.25
TLV2264AQ,
TLV2264AM
MAX
MIN
TYP
0.35
0.55
UNIT
MAX
SR
Slew rate at unity
gain
VO = 0.5 V to 3.5 V,
CL = 100 pF ‡
Equivalent input
noise voltage
f = 10 Hz
25°C
40
40
Vn
f = 1 kHz
25°C
12
12
Peak-to-peak
equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
25°C
0.7
0.7
VN(PP)
f = 0.1 Hz to 10 Hz
25°C
1.3
1.3
In
Equivalent input
noise current
25°C
0.6
0.6
Total harmonic
distortion plus
noise
0.017%
0.017%
THD + N
0.03%
0.03%
25°C
0.71
0.71
MHz
25°C
185
185
kHz
6.4
6.4
14.1
14.1
25°C
56°
56°
Gain margin
25°C
† Full range is − 40°C to 125°C for Q level part, − 55°C to 125°C for M level part.
‡ Referenced to 2.5 V
11
11
BOM
ts
φm
VO = 0.5 V to 2.5 V,
f = 20 kHz,
RL = 50 kΩ ‡
AV = 1
Gain-bandwidth
product
f = 50 kHz,
CL = 100 pF ‡
RL = 50 kΩ ‡,
Maximum
output-swing
bandwidth
VO(PP) = 2 V,
RL = 50 kΩ ‡,
AV = 1,
CL = 100 pF ‡
Settling time
AV = − 1,
Step = 0.5 V to 2.5 V,
RL = 50 kΩ ‡,
CL = 100 pF ‡
Phase margin at
unity gain
RL = 50 kΩ ‡,
V/µs
0.25
nV/√Hz
µV
V
fA /√Hz
25°C
AV = 10
To 0.1%
µss
25°C
To 0.01%
CL = 100 pF ‡
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
dB
21
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO
Input offset voltage
Distribution
vs Common-mode voltage
2−5
6, 7
αVIO
IIB/IIO
Input offset voltage temperature coefficient
Distribution
8 − 11
Input bias and input offset currents
vs Free-air temperature
12
VI
Input voltage
vs Supply voltage
vs Free-air temperature
13
14
VOH
VOL
High-level output voltage
vs High-level output current
15, 18
Low-level output voltage
vs Low-level output current
16, 17, 19
VO(PP)
Maximum peak-to-peak output voltage
vs Frequency
20
IOS
Short-circuit output current
vs Supply voltage
vs Free-air temperature
21
22
VID
AVD
Differential input voltage
vs Output voltage
Differential voltage amplification
vs Load resistance
AVD
Large-signal differential voltage amplification
vs Frequency
vs Free-air temperature
26, 27
28, 29
zo
Output impedance
vs Frequency
30, 31
CMRR
Common-mode rejection ratio
vs Frequency
vs Free-air temperature
32
33
kSVR
Supply-voltage rejection ratio
vs Frequency
vs Free-air temperature
34, 35
36, 37
IDD
Supply current
vs Free-air temperature
38, 39
SR
Slew rate
vs Load capacitance
vs Free-air temperature
40
41
VO
VO
Inverting large-signal pulse response
42, 43
Voltage-follower large-signal pulse response
44, 45
VO
VO
Inverting small-signal pulse response
46, 47
Voltage-follower small-signal pulse response
48, 49
Vn
Equivalent input noise voltage
vs Frequency
Input noise voltage
Over a 10-second period
52
Integrated noise voltage
vs Frequency
53
Total harmonic distortion plus noise
vs Frequency
54
Gain-bandwidth product
vs Supply voltage
vs Free-air temperature
55
56
Phase margin
vs Frequency
vs Load capacitance
26, 27
57
Gain margin
vs Load capacitance
58
Unity-gain bandwidth
vs Load capacitance
59
Overestimation of phase margin
vs Load capacitance
60
THD + N
φm
B1
22
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
23, 24
25
50, 51
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
TYPICAL CHARACTERISTICS
DISTRIBUTION OF TLV2262
INPUT OFFSET VOLTAGE
DISTRIBUTION OF TLV2262
INPUT OFFSET VOLTAGE
15
12
841 Amplifiers From 2 Wafer Lots
VDD± = ± 1.5 V
TA = 25°C
Precentage of Amplifiers − %
Precentage of Amplifiers − %
15
9
6
3
0
−1.6
−0.8
0
0.8
VIO − Input Offset Voltage − mV
12
841 Amplifiers From 2 Wafer Lots
VDD± = ± 2.5 V
TA = 25°C
9
6
3
0
−1.6
1.6
Figure 2
20
16
Percentage of Amplifiers − %
Percentage of Amplifiers − %
DISTRIBUTION OF TLV2264
INPUT OFFSET VOLTAGE
2272 Amplifiers From 2 Wafer Lots
VDD ± = ± 1.5 V
TA = 25°C
12
8
4
0
−1.6
1.6
Figure 3
DISTRIBUTION OF TLV2264
INPUT OFFSET VOLTAGE
20
−0.8
0
0.8
VIO − Input Offset Voltage − mV
−0.8
0
0.8
VIO − Input Offset Voltage − mV
1.6
2272 Amplifiers From 2 Wafer Lots
VDD ± = ± 2.5 V
TA = 25°C
16
12
8
4
0
−1.6
Figure 4
−0.8
0
0.8
VIO − Input Offset Voltage − mV
1.6
Figure 5
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
23
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
TYPICAL CHARACTERISTICS
INPUT OFFSET VOLTAGE†
vs
COMMON-MODE INPUT VOLTAGE
INPUT OFFSET VOLTAGE†
vs
COMMON-MODE INPUT VOLTAGE
1
1
VIO − Input Offset Voltage − mV
VIO − Input Offset Voltage − mV
VDD = 3 V
RS = 50 Ω
TA = 25°C
0.5
0
ÁÁ
ÁÁ
ÁÁ
ÁÁ
−0.5
−1
−1
−0.5
0
0.5
1
1.5
2
2.5
VDD = 5 V
RS = 50 Ω
TA = 25°C
0.5
0
−0.5
−1
−1
3
VIC − Common-Mode Input Voltage − V
0
Figure 6
3
4
30
Percentage of Amplifiers − %
128 Amplifiers From 2 Wafer Lots
VDD± = ± 1.5 V
25 P Package
TA = 25°C to 85°C
20
15
10
128 Amplifiers From 2 Wafer Lots
VDD± = ± 2.5 V
25 P Package
TA = 25°C to 85°C
20
15
10
5
5
−4 −3 −2 −1 0
1
2
3
4
α VIO − Temperature Coefficient − µ V / °C
5
0
−5
−4 −3 −2 −1 0
1
2
3
4
α VIO − Temperature Coefficient − µ V / °C
Figure 8
Figure 9
† For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
24
5
DISTRIBUTION OF TLV2262 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT
30
Percentage of Amplifiers − %
2
Figure 7
DISTRIBUTION OF TLV2262 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT
0
−5
1
VIC − Common-Mode Input Voltage − V
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
TYPICAL CHARACTERISTICS
DISTRIBUTION OF TLV2264 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT
DISTRIBUTION OF TLV2264 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT
35
128 Amplifiers From
2 Wafer Lots
30 VDD± = ± 1.5 V
N Package
TA = 25°C to 125°C
25
128 Amplifiers From
2 Wafer Lots
VDD ± = ± 2.5 V
N Package
TA = 25°C to 125°C
30
Percentage of Amplifiers − %
Percentage of Amplifiers − %
35
20
15
10
5
25
20
15
10
5
0
−5
−4
−3
−2
−1
0
1
2
3
4
0
5
−5
−4
−3 −2 −1 0
1
2
3
αVIO − Temperature Coefficient
of Input Offset Voltage − µV / °C
αVIO − Temperature Coefficient
of Input Offset Voltage − µV / °C
ÁÁ
ÁÁ
INPUT BIAS AND INPUT OFFSET CURRENTS†
vs
FREE-AIR TEMPERATURE
INPUT VOLTAGE
vs
SUPPLY VOLTAGE
35
30
5
Figure 11
2.5
VDD ± = ± 2.5 V
VIC = 0
VO = 0
RS = 50 Ω
2
RS = 50 Ω
TA = 25°C
1.5
25
IIB
20
15
IIO
10
VI − Input Voltage − V
IIO − Input Bias and Input Offset Currents − pA
IIIB
IB and IIO
Figure 10
4
1
0.5
0
| VIO | ≤ 5 mV
ÁÁ
ÁÁ
−0.5
−1
−1.5
5
−2
0
25
45
65
85
105
TA − Free-Air Temperature − °C
125
−2.5
1
1.5
Figure 12
2
2.5
3
3.5
| VDD± | − Supply Voltage − V
4
Figure 13
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
25
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
TYPICAL CHARACTERISTICS
INPUT VOLTAGE†‡
vs
FREE-AIR TEMPERATURE
HIGH-LEVEL OUTPUT VOLTAGE†‡
vs
HIGH-LEVEL OUTPUT CURRENT
5
4
VDD = 5 V
VDD = 3 V
3.5
VOH − High-Level Output Voltage − V
4
VI − Input Voltage − V
3
| VIO | ≤ 5 mV
2
ÁÁ
1
0
−1
−55 −35 −15
5
25
45
65 85 105 125
TA − Free-Air Temperature − °C
ÁÁ
ÁÁ
ÁÁ
3
TA = − 55°C
2.5
TA = 125°C
2
TA = 25°C
1.5
TA = 85°C
1
TA = − 40°C
0.5
0
0
500
1.4
1
VOL − Low-Level Output Voltage − V
VOL − Low-Level Output Voltage − V
LOW-LEVEL OUTPUT VOLTAGE†‡
vs
LOW-LEVEL OUTPUT CURRENT
VDD = 3 V
TA = 25°C
VIC = 0
0.8
VIC = 0.75 V
0.6
VIC = 1.5 V
0.4
ÁÁ
ÁÁ
ÁÁ
0.2
0
0
1
2
3
4
5
VDD = 3 V
VIC = 1.5 V
1.2
TA = 125°C
1
TA = 85°C
0.8
TA = 25°C
0.6
TA = − 55°C
0.4
TA = − 40°C
0.2
0
0
IOL − Low-Level Output Current − mA
Figure 16
1
2
3
4
IOL − Low-Level Output Current − mA
Figure 17
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
‡ For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
26
2000
Figure 15
LOW-LEVEL OUTPUT VOLTAGE‡
vs
LOW-LEVEL OUTPUT CURRENT
ÁÁ
ÁÁ
1500
| IOH | − High-Level Output Current − µ A
Figure 14
1.2
1000
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE†‡
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE†‡
vs
LOW-LEVEL OUTPUT CURRENT
6
1.4
VDD = 5 V
VIC = 2.5 V
ÁÁ
ÁÁ
1.2
5
VOL − Low-Level Output Voltage − V
VOH − High-Level Output Voltage − V
VDD = 5 V
TA = − 55°C
4
TA = − 40°C
3
TA = 25°C
TA = 125°C
2
TA = 85°C
0
500
TA = 85°C
0.8
TA = 25°C
0.6
TA = 125°C
1000
1500
2000
2500
3000
TA = − 40°C
0.2
0
0
| IOH | − High-Level Output Current − µA
4
5
1
2
3
IOL − Low-Level Output Current − mA
Figure 18
SHORT-CIRCUIT OUTPUT CURRENT
vs
SUPPLY VOLTAGE
5
12
RI = 10 kΩ
TA = 25°C
VDD = 5 V
I OS − Short-Circuit Output Current − mA
VO(PP) − Maximum Peak-to-Peak Output Voltage − V
6
Figure 19
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE‡
vs
FREQUENCY
ÁÁ
ÁÁ
ÁÁ
TA = − 55°C
0.4
ÁÁ
ÁÁ
1
0
1
4
3
VDD = 3 V
2
1
0
10 3
10 4
10 5
f − Frequency − Hz
10 6
10
VIC = VDD/2
TA = 25°C
VID = − 100 mV
8
6
4
2
0
VID = 100 mV
−2
2
Figure 20
3
4
5
6
VDD − Supply Voltage − V
7
8
Figure 21
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
‡ For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
27
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
TYPICAL CHARACTERISTICS
SHORT-CIRCUIT OUTPUT CURRENT †
vs
FREE-AIR TEMPERATURE
DIFFERENTIAL INPUT VOLTAGE‡
vs
OUTPUT VOLTAGE
1000
VO = 2.5 V
VDD = 5 V
10
VID = − 100 mV
8
6
4
2
0
VID = 100 mV
−2
−4
−75
−50
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
VDD = 3 V
RI = 50 kΩ
VIC = 1.5 V
TA = 25°C
800
V ID − Differential Input Voltage − µ V
I OS − Short-Circuit Output Current − mA
12
600
400
200
0
−200
−400
−600
−800
−1000
125
0
0.5
1
1.5
2
VO − Output Voltage − V
Figure 22
DIFFERENTIAL VOLTAGE AMPLIFICATION‡
vs
LOAD RESISTANCE
V ID − Differential Input Voltage − µ V
AVD − Differential Voltage Amplification − V/mV
1000
VDD = 5 V
VIC = 2.5 V
RL = 50 kΩ
TA = 25°C
600
400
200
0
−200
−400
−600
−800
−1000
0
1
2
4
3
VO − Output Voltage − V
5
1000
ÁÁ
ÁÁ
VO(PP) = 2 V
TA = 25°C
VDD = 5 V
100
VDD = 3 V
10
1
10 3
10 4
10 5
RL − Load Resistance − kΩ
Figure 24
Figure 25
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
‡ For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
28
3
Figure 23
DIFFERENTIAL INPUT VOLTAGE‡
vs
OUTPUT VOLTAGE
800
2.5
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
10 6
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
TYPICAL CHARACTERISTICS
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE MARGIN†
vs
FREQUENCY
60
AVD
A
VD − Large-Signal Differential
Voltage Amplification − dB
180°
VDD = 5 V
CL= 100 pF
TA = 25°C
135°
40
Phase Margin
20
ÁÁ
ÁÁ
ÁÁ
90°
45°
Gain
0
0°
−20
φom
m − Phase Margin
80
−45°
−40
103
104
105
−90°
107
106
f − Frequency − Hz
Figure 26
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE MARGIN†
vs
FREQUENCY
60
180°
VDD = 3 V
CL = 100 pF
TA = 25°C
135°
40
Phase Margin
20
ÁÁ
ÁÁ
ÁÁ
90°
45°
Gain
0
0°
−20
φom
m − Phase Margin
AVD
A
VD − Large-Signal Differential
Voltage Amplification − dB
80
−45°
−40
103
104
105
106
−90°
107
f − Frequency − Hz
Figure 27
† For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
29
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
TYPICAL CHARACTERISTICS
LARGE-SIGNAL DIFFERENTIAL
VOLTAGE AMPLIFICATION†‡
vs
FREE-AIR TEMPERATURE
LARGE-SIGNAL DIFFERENTIAL
VOLTAGE AMPLIFICATION†‡
vs
FREE-AIR TEMPERATURE
1000
10000
VDD = 5 V
VIC = 2.5 V
VO = 1 V to 4 V
AVD − Large-Signal Differential Voltage
Amplification − V/mV
AVD − Large-Signal Differential Voltage
Amplification − V/mV
RL = 1 MΩ
RL = 50 kΩ
100
RL = 10 kΩ
VDD = 3 V
VIC = 1.5 V
VO = 0.5 V to 2.5 V
10
−75
−50
−25
0
25
50
75 100
TA − Free-Air Temperature − °C
RL = 1 MΩ
1000
RL = 50 kΩ
100
RL = 10 kΩ
10
−75
125
−50
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
Figure 28
Figure 29
OUTPUT IMPEDANCE‡
vs
FREQUENCY
100
10
OUTPUT IMPEDANCE‡
vs
FREQUENCY
1000
VDD = 3 V
TA = 25°C
VDD = 5 V
TA = 25°C
A V = 100
z o − Output Impedance − Ω
z o − Output Impedance − Ω
1000
A V = 10
AV = 1
1
0.1
10 2
10 3
10 4
f− Frequency − Hz
10 5
100
A V = 100
10
A V = 10
1
AV = 1
0.1
10 2
Figure 30
10 3
10 4
f− Frequency − Hz
Figure 31
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
‡ For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
30
125
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
10 5
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
TYPICAL CHARACTERISTICS
COMMON-MODE REJECTION RATIO†
vs
FREQUENCY
COMMON-MODE REJECTION RATIO†‡
vs
FREE-AIR TEMPERATURE
90
VDD = 5 V
VIC = 2.5 V
CMMR − Common-Mode Rejection Ratio − dB
CMRR − Common-Mode Rejection Ratio − dB
100
TA = 25°C
80
VDD = 5 V
VIC = 1.5 V
60
40
20
0
10 1
10 2
10 4
10 3
f − Frequency − Hz
10 5
88
86
84
VDD = 5 V
82
80
78
VDD = 3 V
76
74
72
70
− 75 − 50 − 25
0
25 50
75 100
TA − Free-Air Temperature − °C
10 6
Figure 32
Figure 33
SUPPLY-VOLTAGE REJECTION RATIO†
vs
FREQUENCY
SUPPLY-VOLTAGE REJECTION RATIO†
vs
FREQUENCY
100
VDD = 3 V
TA = 25°C
k SVR − Supply-Voltage Rejection Ratio − dB
k SVR − Supply-Voltage Rejection Ratio − dB
100
80
60
kSVR +
40
kSVR −
20
ÁÁ
ÁÁ
0
−20
10 1
125
10 2
10 3
10 4
f − Frequency − Hz
10 5
10 6
VDD = 5 V
TA = 25°C
80
60
kSVR +
40
kSVR −
20
ÁÁ
ÁÁ
ÁÁ
0
−20
10 1
Figure 34
10 2
10 3
10 4
f − Frequency − Hz
10 5
10 6
Figure 35
† For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
‡ Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
31
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
TYPICAL CHARACTERISTICS
TLV2262
SUPPLY-VOLTAGE REJECTION RATIO†
vs
FREE-AIR TEMPERATURE
110
VDD = 2.7 V to 8 V
VIC = VO = VDD / 2
k SVR − Supply-Voltage Rejection Ratio − dB
k SVR − Supply-Voltage Rejection Ratio − dB
110
TLV2264
SUPPLY-VOLTAGE REJECTION RATIO†
vs
FREE-AIR TEMPERATURE
105
100
ÁÁ
ÁÁ
95
90
−75 −50
−25
0
25
50
75 100
TA − Free-Air Temperature − °C
VDD = 2.7 V to 8 V
VIC = VO = VDD / 2
105
100
ÁÁ
ÁÁ
ÁÁ
95
90
−75
125
−50
TLV2264
SUPPLY CURRENT†‡
vs
FREE-AIR TEMPERATURE
600
1200
500
1000
I DD − Supply Current − µ A
I DD − Supply Current − µ A
TLV2262
SUPPLY CURRENT †‡
vs
FREE-AIR TEMPERATURE
VDD = 5 V
VO = 2.5 V
400
ÁÁ
ÁÁ
ÁÁ
VDD = 3 V
VO = 1.5 V
300
200
−75 −50
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
125
VDD = 5 V
VO = 2.5 V
800
VDD = 3 V
VO = 1.5 V
600
400
−75
−50
Figure 38
−25
0
25
50
75 100
TA − Free-Air Temperature − °C
Figure 39
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
‡ For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
32
125
Figure 37
Figure 36
ÁÁ
ÁÁ
−25
0
25
50
75 100
TA − Free-Air Temperature − °C
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
125
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
TYPICAL CHARACTERISTICS
SLEW RATE†‡
vs
FREE-AIR TEMPERATURE
SLEW RATE†
vs
LOAD CAPACITANCE
1
1.2
SR −
1
SR −
SR − Slew Rate − V/ µ s
SR − Slew Rate − V/ µ s
0.8
0.6
SR +
0.4
0.2
SR +
0.6
0.4
0.2
VDD = 5 V
AV = −1
TA = 25°C
0
10 1
0.8
10 2
10 3
CL − Load Capacitance − pF
0
−75
10 4
VDD = 5 V
RL = 50 kΩ
CL = 100 pF
AV = 1
−50
−25
0
25
50
75 100
TA − Free-Air Temperature − °C
Figure 40
Figure 41
INVERTING LARGE-SIGNAL PULSE
RESPONSE†
INVERTING LARGE-SIGNAL PULSE
RESPONSE†
3
2
1.5
1
3
2
1
0.5
0
VDD = 5 V
RL = 50 kΩ
CL = 100 pF
AV = −1
TA = 25°C
4
VO − Output Voltage − V
VO − Output Voltage − V
5
VDD = 3 V
RL = 50 kΩ
CL = 100 pF
AV = −1
TA = 25°C
2.5
125
0
2
4
6
8
10 12 14
t − Time − µs
16
18
20
0
0
2
Figure 42
4
6
8
10 12
t − Time − µs
14
16
18
20
Figure 43
† For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
‡ Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
33
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
TYPICAL CHARACTERISTICS
VOLTAGE-FOLLOWER LARGE-SIGNAL
PULSE RESPONSE†
VOLTAGE-FOLLOWER LARGE-SIGNAL
PULSE RESPONSE†
3
5
VDD = 3 V
RL = 50 kΩ
CL = 100 pF
AV = −1
TA = 25°C
4
VO − Output Voltage − V
VO − Output Voltage − V
2.5
2
1.5
1
3
2
1
0.5
0
VDD = 5 V
RL = 50 kΩ
CL = 100 pF
AV = −1
TA = 25°C
0
2
4
6
8
10
12
14
16
18
0
20
0
2
4
6
t − Time − µs
Figure 44
18
0.8
0.75
0.7
VDD = 5 V
RL = 50 kΩ
CL = 100 pF
2.6 A = − 1
V
TA = 25°C
2.55
2.5
2.45
0.65
0.6
0
2
4
6
8
10
12
14
16
18
20
2.4
0
2
t − Time − µs
4
6
8
10
12
14
16
18
t − Time − µs
Figure 46
Figure 47
† For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
34
20
2.65
VO
VO − Output Voltage − V
VO − Output Voltage − V
0.85
16
INVERTING SMALL-SIGNAL
PULSE RESPONSE†
VDD = 3 V
RL = 50 kΩ
CL = 100 pF
AV = − 1
TA = 25°C
0.9
14
Figure 45
INVERTING SMALL-SIGNAL
PULSE RESPONSE†
0.95
8
10 12
t − Time − µs
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
20
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
TYPICAL CHARACTERISTICS
VOLTAGE-FOLLOWER SMALL-SIGNAL
PULSE RESPONSE†
VOLTAGE-FOLLOWER SMALL-SIGNAL
PULSE RESPONSE†
0.95
VDD = 5 V
RL = 50 kΩ
CL = 100 pF
AV = 1
TA = 25°C
2.6
VO
VO − Output Voltage − V
0.9
VO
VO − Output Voltage − V
2.65
VDD = 3 V
RL = 50 kΩ
CL = 100 pF
AV = 1
TA = 25°C
0.85
0.8
0.75
2.55
2.5
2.45
0.7
0
2
4
6
8
10 12
t − Time − µs
14
16
18
2.4
20
0
2
4
Figure 48
14
16
18
20
EQUIVALENT INPUT NOISE VOLTAGE†
vs
FREQUENCY
60
60
VDD = 3 V
RS = 20 Ω
TA = 25°C
V n − Equivalent Input Noise Voltage − nV/ Hz
V n − Equivalent Input Noise Voltage − nV/ Hz
8
10 12
t − Time − µs
Figure 49
EQUIVALENT INPUT NOISE VOLTAGE†
vs
FREQUENCY
50
6
40
30
20
10
0
10 1
10 2
10 3
f − Frequency − Hz
10 4
50
VDD = 5 V
RS = 20 Ω
TA = 25°C
40
30
20
10
0
10 1
Figure 50
10 2
10 3
f − Frequency − Hz
10 4
Figure 51
† For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
35
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
TYPICAL CHARACTERISTICS
INTEGRATED NOISE VOLTAGE
vs
FREQUENCY
INPUT NOISE VOLTAGE OVER
A 10-SECOND PERIOD†
100
1000
Calculated Using Ideal Pass-Band Filter
Lower Frequency = 1 Hz
TA = 25°C
Integrated Noise Voltage − µ V
Input Noise Voltage − nV
750
500
250
0
−250
−500
−750
−1000
0
VDD = 5 V
f = 0.1 Hz
to 10 Hz
TA = 25°C
2
10
1
0.1
4
6
8
10
10 1
1
t − Time − s
Figure 52
10 4
10 5
Figure 53
TOTAL HARMONIC DISTORTION PLUS NOISE†
vs
FREQUENCY
GAIN-BANDWIDTH PRODUCT
vs
SUPPLY VOLTAGE
10 −1
900
A V = 100
10 −2
Gain-Bandwidth Product − kHz
THD + N − Total Harmonic Distortion Plus Noise − %
10 2
10 3
f − Frequency − Hz
A V = 10
AV = 1
10 −3
10 1
VDD = 5 V
RL = 50 kΩ
TA = 25°C
10 2
10 3
10 4
10 4
860
820
780
740
700
0
1
f − Frequency − Hz
Figure 54
2
3
5
4
6
VDD − Supply Voltage − V
7
Figure 55
† For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
36
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
8
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
TYPICAL CHARACTERISTICS
PHASE MARGIN
vs
LOAD CAPACITANCE
GAIN-BANDWIDTH PRODUCT †‡
vs
FREE-AIR TEMPERATURE
75°
1200
TA = 25°C
60°
Rnull = 100 Ω
1000
φom
m − Phase Margin
Gain-Bandwidth Product − kHz
VDD = 5 V
f = 10 kHz
CL = 100 pF
800
Rnull = 50 Ω
45°
Rnull = 20 Ω
30°
Rnull = 10 Ω
50 kΩ
600
15°
50 kΩ
VI
400
−75
0
25
50
75
100
TA − Free-Air Temperature − °C
Figure 56
Rnull = 0
10 4
UNITY-GAIN BANDWIDTH
vs
LOAD CAPACITANCE
20
1000
RL = 50 kΩ
AV = 1
TA = 25°C
B1 − Unity-Gain Bandwidth − kHz
TA = 25°C
Rnull = 100 Ω
15
Gain Margin − dB
CL
Figure 57
GAIN MARGIN
vs
LOAD CAPACITANCE
10
Rnull = 50 Ω
Rnull = 20 Ω
Rnull = 10 Ω
Rnull = 0
10 2
10 3
CL − Load Capacitance − pF
800
600
ÁÁ
ÁÁ
5
0
10
Rnull
10 2
10 3
CL − Load Capacitance − pF
10
125
−
+
VDD −/GND
0°
−50 −25
VDD +
10 4
400
200
10
Figure 58
10 2
10 3
CL − Load Capacitance − pF
10 4
Figure 59
† For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.
‡ Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
37
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
TYPICAL CHARACTERISTICS
OVERESTIMATION OF PHASE MARGIN†
vs
LOAD CAPACITANCE
14°
TA = 25°C
Overestimation of Phase Margin
12°
Rnull = 100 Ω
10°
8°
Rnull = 50 Ω
6°
4°
Rnull = 10 Ω
Rnull = 20 Ω
2°
0
10
10 2
10 3
CL − Load Capacitance − pF
† See application information
Figure 60
38
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
10 4
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
APPLICATION INFORMATION
driving large capacitive loads
The TLV226x is designed to drive larger capacitive loads than most CMOS operational amplifiers. Figure 51
and Figure 52 illustrate its ability to drive loads greater than 400 pF while maintaining good gain and phase
margins (Rnull = 0).
A smaller series resistor (Rnull) at the output of the device (see Figure 61) improves the gain and phase margins
when driving large capacitive loads. Figure 51 and Figure 52 show the effects of adding series resistances of
10 Ω, 20 Ω, 50 Ω, and 100 Ω. The addition of this series resistor has two effects: the first is that it adds a zero
to the transfer function and the second is that it reduces the frequency of the pole associated with the output
load in the transfer function.
The zero introduced to the transfer function is equal to the series resistance times the load capacitance. To
calculate the improvement in phase margin, equation (1) can be used.
ǒ
∆θ m1 + tan –1 2 × π × UGBW × R
null
×C
Ǔ
(1)
L
Where :
∆θ m1 + improvement in phase margin
UGBW + unity-gain bandwidth frequency
R null + output series resistance
C L + load capacitance
The unity-gain bandwidth (UGBW) frequency decreases as the capacitive load increases (see Figure 53). To
use equation 1, UGBW must be approximated from Figure 53.
Using equation 1 alone overestimates the improvement in phase margin as illustrated in Figure 59. The
overestimation is caused by the decrease in the frequency of the pole associated with the load, providing
additional phase shift and reducing the overall improvement in phase margin. The pole associated with the load
is reduced by the factor calculated in equation 2.
F +
1
1 ) g m × R null
(2)
Where :
F + factor reducing frequency of pole
g m + small-signal output transconductance (typically 4.83 × 10 – 3 mhos)
R null + output series resistance
For the TLV226x, the pole associated with the load is typically 7 MHz with 100-pF load capacitance. This value
varies inversely with CL: at CL = 10 pF, use 70 MHz, at CL = 1000 pF, use 700 kHz, and so on.
Reducing the pole associated with the load introduces phase shift, thereby reducing phase margin. This results
in an error in the increase in phase margin expected by considering the zero alone (equation 1). Equation 3
approximates the reduction in phase margin due to the movement of the pole associated with the load. The
result of this equation can be subtracted from the result of the equation 1 to better approximate the improvement
in phase margin.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
39
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
APPLICATION INFORMATION
driving large capacitive loads (continued)
ȱ
ȧ
Ȳ
ǒ
ȳ
ȧ
ȴ
Ǔ
∆θ m2 + tan –1 UGBW – tan –1 UGBW
P2
ǒF × P2Ǔ
Where :
∆θ m2 + reduction in phase margin
(3)
UGBW + unity-gain bandwidth frequency
F + factor from equation (2)
P 2 + unadjusted pole (70 MHz @ 10 pF, 7 MHz @ 100 pF, etc.)
Using these equations with Figure 60 and Figure 61 enables the designer to choose the appropriate output
series resistance to optimize the design of circuits driving large capacitive loads.
50 kΩ
VDD +
50 kΩ
VI
−
Rnull
+
CL
VDD − / GND
Figure 61. Series-Resistance Circuit
40
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
 SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts, the model generation software used
with Microsim PSpice. The Boyle macromodel (see Note 5) and subcircuit in Figure 62 are generated using
the TLV226x typical electrical and operating characteristics at TA = 25°C. Using this information, output
simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):
D
D
D
D
D
D
D
D
D
D
D
D
Maximum positive output voltage swing
Maximum negative output voltage swing
Slew rate
Quiescent power dissipation
Input bias current
Open-loop voltage amplification
Unity-gain frequency
Common-mode rejection ratio
Phase margin
DC output resistance
AC output resistance
Short-circuit output current limit
NOTE 5: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Intergrated Circuit Operational Amplifiers,” IEEE
Journal of Solid-State Circuits, SC-9, 353 (1974).
99
3
VCC +
9
RSS
92
FB
+
10
J1
DP
VC
J2
IN +
11
RD1
VAD
DC
12
C1
R2
−
53
HLIM
−
C2
6
−
−
+
VLN
+
GCM
GA
VLIM
8
−
RD2
54
4
−
7
60
+
−
+ DLP
91
+
VLP
90
RO2
VB
IN −
VCC −
−
+
ISS
RP
2
1
DLN
EGND +
−
RO1
DE
5
+
VE
OUT
.SUBCKT TLV226x 1 2 3 4 5
C1
11
12
5.5E−12
C2
6
7
20.00E−12
DC
5
53
DX
DE
54
5
DX
DLP
90
91
DX
DLN
92
90
DX
DP
4
3
DX
EGND
99
0
POLY (2) (3,0) (4,0) 0 .5 .5
FB
7
99
POLY (5) VB VC VE VLP
+ VLN 0 8.84E6 −10E6 10E6 10E6 −10E6
GA
6
0
11
12 62.83E−6
GCM
0
6
10
99 12.34E−9
ISS
3
10
DC 11.05E−6
HLIM
90
0
VLIM 1K
J1
11
2
10 JX
J2
12
1
10 JX
R2
6
9
100.0E3
RD1
60
11
15.92E3
RD2
60
12
15.92E3
R01
8
5
135
R02
7
99
135
RP
3
4
15.87E3
RSS
10
99
18.18E6
VAD
60
4
−.5
VB
9
0
DC 0
VC
3
53
DC .615
VE
54
4
DC .615
VLIM
7
8
DC 0
VLP
91
0
DC 1
VLN
0
92
DC 5.1
.MODEL DX D (IS=800.0E−18)
.MODEL JX PJF (IS=500.0E−15 BETA=325E−6
+ VTO=−.08)
.ENDS
Figure 62. Boyle Macromodel and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
41
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
5962-9550401Q2A
ACTIVE
LCCC
FK
20
1
TBD
5962-9550401QHA
ACTIVE
CFP
U
10
1
TBD
5962-9550401QPA
ACTIVE
CDIP
JG
8
1
TBD
5962-9550402Q2A
ACTIVE
LCCC
FK
20
1
TBD
5962-9550402QCA
ACTIVE
CDIP
J
14
1
TBD
5962-9550402QDA
ACTIVE
CFP
W
14
1
TBD
5962-9550403Q2A
ACTIVE
LCCC
FK
20
1
TBD
5962-9550403QHA
ACTIVE
CFP
U
10
1
TBD
5962-9550403QPA
ACTIVE
CDIP
JG
8
1
TBD
5962-9550404Q2A
ACTIVE
LCCC
FK
20
1
TBD
5962-9550404QCA
ACTIVE
CDIP
J
14
1
TBD
5962-9550404QDA
ACTIVE
CFP
W
14
1
TLV2262AID
ACTIVE
SOIC
D
8
75
TLV2262AIDG4
ACTIVE
SOIC
D
8
75
TLV2262AIDR
ACTIVE
SOIC
D
TLV2262AIDRG4
ACTIVE
SOIC
TLV2262AIP
ACTIVE
TLV2262AIPE4
Lead/Ball Finish
MSL Peak Temp (3)
POST-PLATE N / A for Pkg Type
A42 SNPB
N / A for Pkg Type
A42 SNPB
N / A for Pkg Type
POST-PLATE N / A for Pkg Type
A42 SNPB
N / A for Pkg Type
A42 SNPB
N / A for Pkg Type
POST-PLATE N / A for Pkg Type
A42 SNPB
N / A for Pkg Type
A42 SNPB
N / A for Pkg Type
POST-PLATE N / A for Pkg Type
A42 SNPB
N / A for Pkg Type
TBD
A42 SNPB
N / A for Pkg Type
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TLV2262AIPW
ACTIVE
TSSOP
PW
8
150
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV2262AIPWG4
ACTIVE
TSSOP
PW
8
150
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV2262AIPWLE
OBSOLETE
TSSOP
PW
8
TLV2262AIPWR
ACTIVE
TSSOP
PW
8
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV2262AIPWRG4
ACTIVE
TSSOP
PW
8
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV2262AMFKB
ACTIVE
LCCC
FK
20
1
TBD
TLV2262AMJGB
ACTIVE
CDIP
JG
8
1
TBD
TLV2262AMUB
ACTIVE
CFP
U
10
1
TLV2262AQD
NRND
SOIC
D
8
75
TLV2262AQDG4
ACTIVE
SOIC
D
8
TBD
Call TI
Call TI
POST-PLATE N / A for Pkg Type
A42 SNPB
N / A for Pkg Type
TBD
A42 SNPB
N / A for Pkg Type
TBD
CU NIPDAU
Level-1-220C-UNLIM
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TBD
CU NIPDAU
Level-1-220C-UNLIM
CU NIPDAU
Level-1-260C-UNLIM
TLV2262AQDR
NRND
SOIC
D
8
2500
TLV2262AQDRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
TLV2262ID
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV2262IDG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TLV2262IDR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV2262IDRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV2262IP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TLV2262IPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TLV2262IPW
ACTIVE
TSSOP
PW
8
150
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV2262IPWG4
ACTIVE
TSSOP
PW
8
150
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV2262IPWR
ACTIVE
TSSOP
PW
8
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV2262IPWRG4
ACTIVE
TSSOP
PW
8
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV2262MFKB
ACTIVE
LCCC
FK
20
1
TBD
TLV2262MJGB
ACTIVE
CDIP
JG
8
1
TBD
A42 SNPB
N / A for Pkg Type
TLV2262MUB
ACTIVE
CFP
U
10
1
TBD
A42 SNPB
N / A for Pkg Type
TLV2262QD
NRND
SOIC
D
8
75
TBD
CU NIPDAU
Level-1-220C-UNLIM
TLV2262QDG4
ACTIVE
SOIC
D
8
1500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV2262QDR
NRND
SOIC
D
8
2500
CU NIPDAU
Level-1-220C-UNLIM
TLV2262QDRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV2264AID
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV2264AIDG4
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV2264AIDR
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV2264AIDRG4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV2264AIN
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TLV2264AINE4
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TLV2264AIPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV2264AIPWG4
ACTIVE
TSSOP
PW
14
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV2264AIPWLE
OBSOLETE
TSSOP
PW
14
TLV2264AIPWR
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV2264AIPWRG4
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV2264AMFKB
ACTIVE
LCCC
FK
20
1
TBD
TBD
TBD
Lead/Ball Finish
MSL Peak Temp (3)
POST-PLATE N / A for Pkg Type
Call TI
Call TI
POST-PLATE N / A for Pkg Type
TLV2264AMJB
ACTIVE
CDIP
J
14
1
TBD
A42 SNPB
N / A for Pkg Type
TLV2264AMWB
ACTIVE
CFP
W
14
1
TBD
A42 SNPB
N / A for Pkg Type
TLV2264AQD
ACTIVE
SOIC
D
14
50
TBD
CU NIPDAU
Addendum-Page 2
Level-1-220C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TLV2264AQDG4
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TBD
CU NIPDAU
Level-1-220C-UNLIM
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
TLV2264AQDR
ACTIVE
SOIC
D
14
2500
TLV2264AQDRG4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
TLV2264ID
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV2264IDG4
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV2264IDR
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV2264IDRG4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV2264IN
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TLV2264INE4
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TLV2264IPWR
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV2264IPWRG4
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV2264MFKB
ACTIVE
LCCC
FK
20
1
TBD
TLV2264MJ
ACTIVE
CDIP
J
14
1
TBD
A42 SNPB
N / A for Pkg Type
POST-PLATE N / A for Pkg Type
TLV2264MJB
ACTIVE
CDIP
J
14
1
TBD
A42 SNPB
N / A for Pkg Type
TLV2264MWB
ACTIVE
CFP
W
14
1
TBD
A42 SNPB
N / A for Pkg Type
TLV2264QD
ACTIVE
SOIC
D
14
50
TBD
CU NIPDAU
Level-1-220C-UNLIM
TLV2264QDG4
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLV2264QDR
ACTIVE
SOIC
D
14
2500
TBD
CU NIPDAU
Level-1-220C-UNLIM
TLV2264QDRG4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Nov-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TLV2262AIDR
D
8
SITE 27
330
12
6.4
5.2
2.1
8
12
Q1
TLV2262AIDR
D
8
SITE 60
330
12
6.4
5.2
2.1
8
12
Q1
TLV2262AIPWR
PW
8
SITE 41
330
12
7.0
3.6
1.6
8
12
Q1
TLV2262IDR
D
8
SITE 27
330
12
6.4
5.2
2.1
8
12
Q1
TLV2262IDR
D
8
SITE 60
330
12
6.4
5.2
2.1
8
12
Q1
TLV2262IPWR
PW
8
SITE 41
330
12
7.0
3.6
1.6
8
12
Q1
TLV2264AIDR
D
14
SITE 60
330
16
6.5
9.0
2.1
8
16
Q1
TLV2264AIPWR
PW
14
SITE 41
330
12
7.0
5.6
1.6
8
12
Q1
TLV2264IDR
D
14
SITE 60
330
16
6.5
9.0
2.1
8
16
Q1
TLV2264IPWR
PW
14
SITE 41
330
12
7.0
5.6
1.6
8
12
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Nov-2007
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
TLV2262AIDR
D
8
SITE 27
342.9
336.6
20.64
TLV2262AIDR
D
8
SITE 60
346.0
346.0
29.0
TLV2262AIPWR
PW
8
SITE 41
346.0
346.0
29.0
TLV2262IDR
D
8
SITE 27
342.9
336.6
20.64
TLV2262IDR
D
8
SITE 60
346.0
346.0
29.0
TLV2262IPWR
PW
8
SITE 41
346.0
346.0
29.0
TLV2264AIDR
D
14
SITE 60
346.0
346.0
33.0
TLV2264AIPWR
PW
14
SITE 41
346.0
346.0
29.0
TLV2264IDR
D
14
SITE 60
346.0
346.0
33.0
TLV2264IPWR
PW
14
SITE 41
346.0
346.0
29.0
Pack Materials-Page 2
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
0.063 (1,60)
0.015 (0,38)
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification.
Falls within MIL STD 1835 GDIP1-T8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
A
B
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
9
22
8
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
7
52
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
25
5
26
27
28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
Falls within JEDEC MS-004
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.430 (10,92)
MAX
0.010 (0,25) M
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,
improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.
Customers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s
standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this
warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily
performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should
provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask
work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services
are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such
products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under
the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an
unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties
may be subject to additional restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service
voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business
practice. TI is not responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would
reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement
specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications
of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related
requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any
applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its
representatives against any damages arising out of the use of TI products in such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is
solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in
connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products
are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any
non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
RFID
www.ti-rfid.com
Telephony
www.ti.com/telephony
Low Power
Wireless
www.ti.com/lpw
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2007, Texas Instruments Incorporated

Open as PDF

Similar pages: TI TLV2252ID; TI TLV2252IDR; TI TLC2272CP; TI TLC2272CDR; TI TLC2264CDR; TI TLC2262IDR; TI LT1013DIDR; TI TLV2252AIDRG4; TI TLC2252CDR; TI TLE2022AID; TI TLC27M2BIDG4; TI TLV2252-Q1; TI TLC2254AIPWR; TI TLC27L7IDRG4; TI TLC2254AIN; TI TLC274CDG4; TI 5962-9089501MPA; TI TLV2211IDBVR; TI TLC2254AQDRQ1; TI 5962-8967701CA; TI 5962-9080801MHA; TI TLC2274AQDRQ1