TLV5618A 2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS230H – JULY 1999 – REVISED JULY 2002 features applications D Dual 12-Bit Voltage Output DAC D Programmable Settling Time DIN SCLK CS OUTA 1 8 2 7 3 6 4 5 VDD OUTB REF AGND VDD NC 3 2 1 20 19 NC 4 18 NC SCLK 5 17 OUTB NC 6 16 NC CS 7 15 REF NC 8 14 NC 10 11 12 13 NC 9 AGND The resistor string output voltage is buffered by an x2 gain rail-to-rail output buffer. The buffer features a Class-AB output stage to improve stability and reduce settling time. The programmable settling time of the DAC allows the designer to optimize speed versus power dissipation. NC The TLV5618A is a dual 12-bit voltage output DAC with a flexible 3-wire serial interface. The serial interface is compatible with TMS320, SPI, QSPI, and Microwire serial ports. It is programmed with a 16-bit serial string containing 4 control and 12 data bits. NC description DIN FK PACKAGE (TOP VIEW) OUTA D P, D OR JG PACKAGE (TOP VIEW) NC D D D – 3 µs in Fast Mode – 10 µs in Slow Mode Compatible With TMS320 and SPI Serial Ports Differential Nonlinearity <0.5 LSB Typ Monotonic Over Temperature Direct Replacement for TLC5618A (C and I Suffixes) Available in Q-Temp Automotive HighRel Automotive Applications Configuration Control/Print Support Qualification to Automotive Standards Digital Servo Control Loops Digital Offset and Gain Adjustment Industrial Process Control Machine and Motion Control Devices Mass Storage Devices NC D D D D D D Implemented with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It is available in an 8-pin SOIC package in standard commercial and industrial temperature ranges. The TLV5618AC is characterized for operation from 0°C to 70°C. The TLV5618AI is characterized for operation from – 40°C to 85°C. The TLV5618AQ is characterized for operation from – 40°C to 125°C. The TLV5618AM is characterized for operation from – 55°C to 125°C. AVAILABLE OPTIONS PACKAGE TA PLASTIC DIP (P) SOIC (D) CERAMIC DIP (JG) 20 PAD LCCC (FK) 0°C to 70°C TLV5618ACP TLV5618ACD — — – 40°C to 85°C TLV5618AIP TLV5618AID — — – 40°C to 125°C — TLV5618AQD TLV5618AQDR — — – 55°C to 125°C — — TLV5618AMJG TLV5618AMFK Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation. Copyright 2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TLV5618A 2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS230H – JULY 1999 – REVISED JULY 2002 functional block diagram REF AGND VDD Power and Speed Control Power-On Reset 2 x2 OUTA x2 OUTB DIN 12 SCLK Serial Interface and Control CS 12-Bit DAC A Latch 12 12 Buffer 12 12-Bit DAC B Latch 12 Terminal Functions TERMINAL NAME NO. I/O/P DESCRIPTION AGND 5 P Ground CS 3 I Chip select. Digital input active low, used to enable/disable inputs. DIN 1 I Digital serial data input OUTA 4 O DAC A analog voltage output OUTB 7 O DAC B analog voltage output REF 6 I Analog reference voltage input SCLK 2 I Digital serial clock input VDD 8 P Positive power supply 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5618A 2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS230H – JULY 1999 – REVISED JULY 2002 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage (VDD to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD + 0.3 V Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD + 0.3 V Operating free-air temperature range, TA: TLV5618AC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C TLV5618AI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C TLV5618AQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 125°C TLV5618AM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATING TABLE PACKAGE 25°C TA ≤ 25 C POWER RATING DERATING FACTOR ABOVE TA = 25°C‡ 70°C TA = 70 C POWER RATING 85°C TA = 85 C POWER RATING 125°C TA = 125 C POWER RATING D 635 mW 5.08 mW/°C 407 mW 330 mW 127 mW FK 1375 mW 11.00 mW/°C 880 mW 715 mW 275 mW JG 1050 mW 8.40 mW/°C 672 mW 546 mW 210 mW ‡ This is the inverse of the traditional junction-to-ambient thermal resistance (RΘJA). Thermal resistances are not production tested and are for informational purposes only. recommended operating conditions Supply voltage voltage, VDD MIN NOM MAX 4.5 5 5.5 2.7 3 3.3 VDD = 5 V VDD = 3 V Power on reset 0.55 High level digital input voltage, voltage VIH High-level VDD = 2.7 V VDD = 5.5 V Low level digital input voltage, Low-level voltage VIL VDD = 2.7 V VDD = 5.5 V Reference voltage, voltage Vref to REF terminal VDD = 5 V (see Note 1) VDD = 3 V (see Note 1) 2 V V 2 V 2.4 0.6 1 Load resistance, RL AGND 2.048 AGND 1.024 VDD –1.5 VDD – 1.5 2 Load capacitance, CL Clock frequency, f(CLK) TLV5618AC Operating free free-air air temperature temperature, TA UNIT 0 V V kΩ 100 pF 20 MHz 70 TLV5618AI – 40 85 TLV5618AQ – 40 125 TLV5618AM – 55 125 °C NOTE 1: Due to the x2 output buffer, a reference input voltage ≥ (VDD–0.4 V)/2 causes clipping of the transfer function. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TLV5618A 2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS230H – JULY 1999 – REVISED JULY 2002 electrical characteristics over recommended operating conditions (unless otherwise noted) power supply PARAMETER TEST CONDITIONS MIN VDD = 4.5 V to 5.5 55V IDD Power su ly current supply No load, All inputs in uts = AGND or VDD, DAC latch = All ones VDD = 2.7 V to 3.3 33V VDD = 2.7 V to 5.5 V TYP MAX Fast 1.8 2.5 Slow 08 0.8 1 Fast 1.6 2.2 Slow 06 0.6 0.9 09 Fast 18 1.8 2.3 23 Slow 0.8 1 mA C&I suffixes mA M&Q suffixes Power down supply current PSRR Zero scale, See Note 2 –65 Full scale, –65 See Note 3 mA µA 1 Power supply rejection ratio UNIT dB NOTES: 2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by: PSRR = 20 log [(EZS(VDDmax) – EZS(VDDmin)/VDDmax] 3. Power supply rejection ratio at full scale is measured by varying VDD and is given by: PSRR = 20 log [(EG(VDDmax) – EG(VDDmin)/VDDmax] static DAC specifications PARAMETER TEST CONDITIONS MIN Resolution TYP MAX UNIT 12 bits INL Integral nonlinearity See Note 4 ±2 ±4 LSB DNL Differential nonlinearity See Note 5 ± 0.5 ±1 LSB EZS Zero-scale error (offset error at zero scale) See Note 6 ± 12 mV EZS (TC) Zero-scale-error temperature coefficient See Note 7 EG Gain error See Note 8 EG (TC) Gain-error temperature coefficient See Note 9 3 C & I suffixes VDD = 4.5 V – 5.5 V VDD = 2.7 V – 3.3 V M & Q suffixes VDD = 2.7 V – 5.5 V ppm/°C ± 0.29 ± 0.6 ± 0.6 1 % full f ll scale V ppm/°C NOTES: 4. The relative accuracy of integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale, excluding the effects of zero-code and full-scale errors. 5. The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1-LSB amplitude change of any two adjacent codes. 6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero. 7. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) – EZS (Tmin)]/2Vref × 106/(Tmax – Tmin). 8. Gain error is the deviation from the ideal output (2Vref – 1 LSB) with an output load of 10 kΩ. 9. Gain temperature coefficient is given by: EG TC = [EG (Tmax) – Eg (Tmin)]/2Vref × 106/(Tmax – Tmin). output specifications PARAMETER VO 4 TEST CONDITIONS Output voltage range RL = 10 kΩ Output load regulation accuracy VO = 4.096 V, 2.048 V, RL = 2 kΩ to 10 kΩ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MIN 0 TYP MAX VDD–0.4 ± 0.29 UNIT V % FS TLV5618A 2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS230H – JULY 1999 – REVISED JULY 2002 electrical characteristics over recommended operating conditions (unless otherwise noted) (continued) reference input PARAMETER VI RI Input voltage range CI Input capacitance TEST CONDITIONS MIN TYP 0 MAX VDD–1.5 Input resistance UNIT V 10 MΩ 5 pF Fast 1.3 MHz Slow 525 kHz – 80 dB Reference input bandwidth REF = 0 2 Vpp + 1.024 1 024 V dc 0.2 Reference feedthrough REF = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10) NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000. digital inputs PARAMETER IIH IIL High-level digital input current Ci Input capacitance TEST CONDITIONS VI = VDD VI = 0 V Low-level digital input current MIN TYP MAX 1 UNIT µA µA –1 8 pF analog output dynamic performance PARAMETER TEST CONDITIONS ts(FS) Output settling time, time full scale RL = 10 kΩ, kΩ CL = 100 pF pF, See Note 11 ts(CC) time code to code Output settling time, RL = 10 kΩ, kΩ CL = 100 pF pF, See Note 12 SR Slew rate RL = 10 kΩ, kΩ CL = 100 pF pF, See Note 13 Glitch energy DIN = 0 to 1, FCLK = 100 kHz, CS = VDD SNR Signal-to-noise ratio SINAD Signal-to-noise + distortion THD Total harmonic distortion SFDR Spurious free dynamic range TYP MAX Fast MIN 1 3 Slow 3 10 Fast 1 Slow 2 Fast 3 Slow 0.5 5 UNIT µss µss V/ s V/µs nV–s 76 fs = 102 kSPS, fout = 1 kHz, CL = 100 pF RL = 10 kΩ, 68 –68 dB 72 NOTES: 11. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of 0x020 to 0xFDF and 0xFDF to 0x020 respectively. Not tested, assured by design. 12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of one count. Not tested, assured by design. 13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% of full-scale voltage. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TLV5618A 2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS230H – JULY 1999 – REVISED JULY 2002 digital input timing requirements MIN tsu(CS-CK) Setup time, CS low before first negative SCLK edge Setu C and I suffixes VDD = 5 V VDD = 3 V NOM MAX UNIT 5 ns 10 Q and M suffixes th Setup time, 16 negative SCLK edge before CS rising edge 10 ns 10 ns SCLK pulse width high 25 ns tw(L) SCLK pulse width low 25 ns tsu(D) Setup time, data ready before SCLK falling edge Setu tsu(C16-CS) tw(H) C and I suffixes VDD = 5 V VDD = 3 V Q and M suffixes th(D) C and I suffixes Hold time, data held valid after SCLK falling g edge g Hold time, time CS high between cycles ns 8 VDD = 5 V 5 VDD = 3 V 10 Q and M suffixes th(CSH) 5 10 ns 10 VDD = 5 V 25 VDD = 3 V 50 ns timing requirements tw(L) SCLK X 1 2 tsu(D) DIN X tw(H) 3 4 5 15 X 16 th(D) D15 D14 D13 D12 D1 D0 X tsu(C16-CS) tsu(CS-CK) CS Figure 1. Timing Diagram 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5618A 2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS230H – JULY 1999 – REVISED JULY 2002 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE vs LOAD CURRENT 2.050 OUTPUT VOLTAGE vs LOAD CURRENT 4.105 3 V Slow Mode, SOURCE 5 V Slow Mode, SOURCE 4.100 3 V Fast Mode, SOURCE 2.046 VO – Output Voltage – V VO – Output Voltage – V 2.048 2.044 2.042 2.040 VDD = 3 V VREF = 1 V Full Scale 2.038 4.095 5 V Fast Mode, SOURCE 4.090 4.085 4.080 4.075 2.036 4.070 0 –0.01 –0.02 –0.5 –0.1 –0.2 –0.5 –0.8 –1 Load Current – mA –2 0 –0.02 –0.04 –0.1 –0.2 –0.4 –0.8 Load Current – mA Figure 2 –1 –2 –4 Figure 3 OUTPUT VOLTAGE vs LOAD CURRENT OUTPUT VOLTAGE vs LOAD CURRENT 0.20 0.35 VDD = 3 V VREF = 1 V Zero Scale 0.18 VDD = 5 V VREF = 2 V Zero Scale 0.30 0.16 3 V Slow Mode, SINK VO – Output Voltage – V VO– Output Voltage – V VDD = 5 V VREF = 2 V Full Scale 0.14 0.12 0.10 0.08 0.06 3 V Fast Mode, SINK 5 V Slow Mode, SINK 0.25 0.20 0.15 5 V Fast Mode, SINK 0.10 0.04 0.05 0.02 0.00 0 0.01 0.02 0.05 0.1 0.2 0.5 Load Current – mA 0.8 1 2 0.00 0 0.02 0.04 0.1 0.2 0.4 0.8 Load Current – mA Figure 4 1 2 4 Figure 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TLV5618A 2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS230H – JULY 1999 – REVISED JULY 2002 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREE-AIR TEMPERATURE SUPPLY CURRENT vs FREE-AIR TEMPERATURE 1.8 1.8 VDD = 3 V VREF = 1 V Full Scale 1.6 Fast Mode 1.4 I DD – Supply Current – mA I DD – Supply Current – mA 1.6 1.2 1.0 0.8 Slow Mode 0.6 0.4 0.2 1.2 1.0 0.8 Slow Mode 0.6 0.4 0.2 0.0 –40 –20 0 20 40 60 80 100 0.0 –40 120 –20 TA – Free-Air Temperature – C 20 40 60 80 100 120 Figure 7 TOTAL HARMONIC DISTORTION vs FREQUENCY TOTAL HARMONIC DISTORTION vs FREQUENCY 0 0 VREF = 1 V + 1 VP/P Sinewave, Output Full Scale –10 THD – Total Harmonic Distortion – dB THD – Total Harmonic Distortion – dB 0 TA – Free-Air Temperature – C Figure 6 –20 –30 –40 –50 3 V Fast Mode –60 –70 5 V Fast Mode –80 –90 VREF = 1 V + 1 VP/P Sinewave, Output Full Scale –10 –20 –30 –40 3 V Slow Mode –50 5 V Slow Mode –60 –70 –80 –90 1 10 100 1 f – Frequency – kHz 10 f – Frequency – kHz Figure 8 8 Fast Mode VDD = 5 V VREF = 2 V Full Scale 1.4 Figure 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 100 TLV5618A 2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS230H – JULY 1999 – REVISED JULY 2002 INL – Integral Nonlinearity Error – LSB TYPICAL CHARACTERISTICS INTEGRAL NONLINEARITY ERROR vs DIGITAL CODE 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 –3.5 –4.0 0 512 1024 1536 2048 2560 3072 3584 4096 Digital Code DNL – Differential Nonlinearity Error – LSB Figure 10 DIFFERENTIAL NONLINEARITY ERROR vs DIGITAL CODE 1.00 0.75 0.50 0.25 0.00 –0.25 –0.50 –0.75 –1.00 0 1024 2048 3072 4096 Digital Code Figure 11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TLV5618A 2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS230H – JULY 1999 – REVISED JULY 2002 APPLICATION INFORMATION general function The TLV5618A is a dual 12-bit, single-supply DAC, based on a resistor-string architecture. It consists of a serial interface, a speed and power down control logic, a resistor string, and a rail-to-rail output buffer. The output voltage (full scale determined by the reference) is given by: [V] 2 REF CODE 2n Where REF is the reference voltage and CODE is the digital input value within the range of 010 to 2n–1, where n=12 (bits). The 16-bit data word, consisting of control bits and the new DAC value, is illustrated in the data format section. A power-on reset initially resets the internal latches to a defined state (all bits zero). serial interface A falling edge of CS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling edges of SCLK. After 16 bits have been transferred or CS rises, the content of the shift register is moved to the target latches (DAC A, DAC B, BUFFER, CONTROL), depending on the control bits within the data word. Figure 12 shows examples of how to connect the TLV5618A to TMS320, SPI, and Microwire. TMS320 DSP FSX DX CLKX TLV5618A CS DIN SCLK SPI TLV5618A CS DIN SCLK I/O MOSI SCK Microwire I/O SO SK TLV5618A CS DIN SCLK Figure 12. Three-Wire Interface Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a falling edge on the pin connected to CS. If the word width is 8 bits (SPI and Microwire) two write operations must be performed to program the TLV5618A. After the write operation(s), the holding registers or the control register are updated automatically on the next positive clock edge following the 16th falling clock edge. serial clock frequency and update rate The maximum serial clock frequency is given by: f sclkmax + t whmin 1 )t + 20 MHz wlmin The maximum update rate is: f updatemax + 1 ǒ whmin ) twlminǓ + 1.25 MHz 16 t Note that the maximum update rate is just a theoretical value for the serial interface, as the settling time of the TLV5618A should also be considered. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5618A 2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS230H – JULY 1999 – REVISED JULY 2002 APPLICATION INFORMATION data format The 16-bit data word for the TLV5618A consists of two parts: D Program bits D New data (D15..D12) (D11..D0) D15 D14 D13 D12 D11 R1 SPD PWR R0 MSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 12 Data bits D0 LSB SPD: Speed control bit 1 → fast mode 0 → slow mode PWR: Power control bit 1 → power down 0 → normal operation On power up, SPD and PWD are reset to 0 (slow mode and normal operation) The following table lists all possible combinations of register-select bits: register-select bits R1 R0 REGISTER 0 0 Write data to DAC B and BUFFER 0 1 Write data to BUFFER 1 0 Write data to DAC A and update DAC B with BUFFER content 1 1 Reserved The meaning of the 12 data bits depends on the register. If one of the DAC registers or the BUFFER is selected, then the 12 data bits determine the new DAC value: examples of operation D Set DAC A output, select fast mode: Write new DAC A value and update DAC A output: D15 D14 D13 D12 1 1 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D3 D2 D1 D0 New DAC A output value The DAC A output is updated on the rising clock edge after D0 is sampled. D Set DAC B output, select fast mode: Write new DAC B value to BUFFER and update DAC B output: D15 D14 D13 D12 0 1 0 0 D11 D10 D9 D8 D7 D6 D5 D4 New BUFFER content and DAC B output value The DAC A output is updated on the rising clock edge after D0 is sampled. D Set DAC A value, set DAC B value, update both simultaneously, select slow mode: 1. Write data for DAC B to BUFFER: D15 D14 D13 D12 0 0 0 1 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D4 D3 D2 D1 D0 New DAC B value 2. Write new DAC A value and update DAC A and B simultaneously: D15 D14 D13 D12 1 0 0 0 D11 D10 D9 D8 D7 D6 D5 New DAC A value POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TLV5618A 2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS230H – JULY 1999 – REVISED JULY 2002 APPLICATION INFORMATION examples of operation (continued) Both outputs are updated on the rising clock edge after D0 from the DAC A data word is sampled. D Set power-down mode: D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X 1 X X X X X X X X X X X X X X = Don’t care linearity, offset, and gain error using single ended supplies When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset, the output voltage may not change with the first code, depending on the magnitude of the offset voltage. The output amplifier attempts to drive the output to a negative voltage. However, because the most negative supply rail is ground, the output cannot drive below ground and clamps the output at 0 V. The output voltage then remains at zero until the input code value produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in Figure 13. Output Voltage 0V DAC Code Negative Offset Figure 13. Effect of Negative Offset (Single Supply) This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the dotted line if the output buffer could drive below the ground rail. For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is measured between full-scale code and the lowest code that produces a positive output voltage. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5618A 2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS230H – JULY 1999 – REVISED JULY 2002 APPLICATION INFORMATION definitions of specifications and terminology integral nonlinearity (INL) The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. differential nonlinearity (DNL) The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. zero-scale error (EZS) Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0. gain error (EG) Gain error is the error in slope of the DAC transfer function. total harmonic distortion (THD) THD is the ratio of the rms value of the first six harmonic components to the value of the fundamental signal. The value for THD is expressed in decibels. signal-to-noise ratio + distortion (S/N+D) S/N+D is the ratio of the rms value of the output signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels. spurious free dynamic range (SFDR) Spurious free dynamic range is the difference between the rms value of the output signal and the rms value of the largest spurious signal within a specified bandwidth. The value for SFDR is expressed in decibels. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TLV5618A 2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS230H – JULY 1999 – REVISED JULY 2002 MECHANICAL DATA D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PIN SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 0.010 (0,25) M 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 0.010 (0,25) 1 7 0°–ā8° A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047 / D 10/96 NOTES: A. B. C. D. 14 All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5618A 2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS230H – JULY 1999 – REVISED JULY 2002 MECHANICAL DATA FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINALS SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.740 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 25 5 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / C 11/95 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold-plated. Falls within JEDEC MS-004 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TLV5618A 2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS230H – JULY 1999 – REVISED JULY 2002 MECHANICAL DATA JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.400 (10,16) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 0.063 (1,60) 0.015 (0,38) 4 0.065 (1,65) 0.045 (1,14) 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0°–15° 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) 4040107/C 08/96 NOTES: A. B. C. D. E. 16 All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification. Falls within MIL STD 1835 GDIP1-T8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5618A 2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS230H – JULY 1999 – REVISED JULY 2002 MECHANICAL DATA P (R-PDIP-T8) PLASTIC DUAL-IN-LINE PACKAGE 0.400 (10,60) 0.355 (9,02) 8 5 0.260 (6,60) 0.240 (6,10) 1 4 0.070 (1,78) MAX 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0°–ā15° 0.010 (0,25) M 0.010 (0,25) NOM 4040082 / B 03/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) 5962-9955701Q2A ACTIVE LCCC FK 20 1 TBD 5962-9955701QPA ACTIVE CDIP JG 8 1 TBD POST-PLATE N / A for Pkg Type A42 SNPB TLV5618ACD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5618ACDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5618ACDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5618ACDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5618ACP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLV5618ACPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLV5618AID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5618AIDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5618AIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5618AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5618AIP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLV5618AIPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLV5618AMFKB ACTIVE LCCC FK 20 1 TBD TLV5618AMJG ACTIVE CDIP JG 8 1 TBD A42 SNPB N / A for Pkg Type TLV5618AMJGB ACTIVE CDIP JG 8 1 TBD A42 SNPB N / A for Pkg Type TLV5618AQD ACTIVE SOIC D 8 75 TBD CU NIPDAU Level-1-220C-UNLIM TLV5618AQDR ACTIVE SOIC D 8 2500 TBD CU NIPDAU Level-1-220C-UNLIM N / A for Pkg Type POST-PLATE N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MCER001A – JANUARY 1995 – REVISED JANUARY 1997 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.400 (10,16) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 0.063 (1,60) 0.015 (0,38) 4 0.065 (1,65) 0.045 (1,14) 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0°–15° 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) 4040107/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification. Falls within MIL STD 1835 GDIP1-T8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MLCC006B – OCTOBER 1996 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MPDI001A – JANUARY 1995 – REVISED JUNE 1999 P (R-PDIP-T8) PLASTIC DUAL-IN-LINE 0.400 (10,60) 0.355 (9,02) 8 5 0.260 (6,60) 0.240 (6,10) 1 4 0.070 (1,78) MAX 0.325 (8,26) 0.300 (7,62) 0.020 (0,51) MIN 0.015 (0,38) Gage Plane 0.200 (5,08) MAX Seating Plane 0.010 (0,25) NOM 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.430 (10,92) MAX 0.010 (0,25) M 4040082/D 05/98 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. 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